opcodes/ChangeLog

   1 2016-06-07  Alan Modra  <amodra@gmail.com>
   2
   3         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
   4         cpu for "vle" to e500.
   5         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
   6         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
   7         (PPCNONE): Delete, substitute throughout.
   8         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
   9         except for major opcode 4 and 31.
  10         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
  11
  12 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
  13
  14         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
  15         ARM_EXT_RAS in relevant entries.
  16
  17 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
  18
  19         PR binutils/20196
  20         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
  21         opcodes for E6500.
  22
  23 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
  24
  25         PR binutis/18386
  26         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
  27         (indir_v_mode): New.
  28         Add comments for '&'.
  29         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
  30         (putop): Handle '&'.
  31         (intel_operand_size): Handle indir_v_mode.
  32         (OP_E_register): Likewise.
  33         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
  34         64-bit indirect call/jmp for AMD64.
  35         * i386-tbl.h: Regenerated
  36
  37 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
  38
  39         * arc-dis.c (struct arc_operand_iterator): New structure.
  40         (find_format_from_table): All the old content from find_format,
  41         with some minor adjustments, and parameter renaming.
  42         (find_format_long_instructions): New function.
  43         (find_format): Rewritten.
  44         (arc_insn_length): Add LSB parameter.
  45         (extract_operand_value): New function.
  46         (operand_iterator_next): New function.
  47         (print_insn_arc): Use new functions to find opcode, and iterator
  48         over operands.
  49         * arc-opc.c (insert_nps_3bit_dst_short): New function.
  50         (extract_nps_3bit_dst_short): New function.
  51         (insert_nps_3bit_src2_short): New function.
  52         (extract_nps_3bit_src2_short): New function.
  53         (insert_nps_bitop1_size): New function.
  54         (extract_nps_bitop1_size): New function.
  55         (insert_nps_bitop2_size): New function.
  56         (extract_nps_bitop2_size): New function.
  57         (insert_nps_bitop_mod4_msb): New function.
  58         (extract_nps_bitop_mod4_msb): New function.
  59         (insert_nps_bitop_mod4_lsb): New function.
  60         (extract_nps_bitop_mod4_lsb): New function.
  61         (insert_nps_bitop_dst_pos3_pos4): New function.
  62         (extract_nps_bitop_dst_pos3_pos4): New function.
  63         (insert_nps_bitop_ins_ext): New function.
  64         (extract_nps_bitop_ins_ext): New function.
  65         (arc_operands): Add new operands.
  66         (arc_long_opcodes): New global array.
  67         (arc_num_long_opcodes): New global.
  68         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
  69
  70 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
  71
  72         * nds32-asm.h: Add extern "C".
  73         * sh-opc.h: Likewise.
  74
  75 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
  76
  77         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
  78         0,b,limm to the rflt instruction.
  79
  80 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
  81
  82         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
  83         constant.
  84
  85 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
  86
  87         PR gas/20145
  88         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
  89         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
  90         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
  91         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
  92         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
  93         * i386-init.h: Regenerated.
  94
  95 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
  96
  97         PR gas/20145
  98         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
  99         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
 100         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
 101         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
 102         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
 103         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
 104         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
 105         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
 106         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
 107         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
 108         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
 109         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
 110         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
 111         CpuRegMask for AVX512.
 112         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
 113         and CpuRegMask.
 114         (set_bitfield_from_cpu_flag_init): New function.
 115         (set_bitfield): Remove const on f.  Call
 116         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
 117         * i386-opc.h (CpuRegMMX): New.
 118         (CpuRegXMM): Likewise.
 119         (CpuRegYMM): Likewise.
 120         (CpuRegZMM): Likewise.
 121         (CpuRegMask): Likewise.
 122         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
 123         and cpuregmask.
 124         * i386-init.h: Regenerated.
 125         * i386-tbl.h: Likewise.
 126
 127 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 128
 129         PR gas/20154
 130         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
 131         (opcode_modifiers): Add AMD64 and Intel64.
 132         (main): Properly verify CpuMax.
 133         * i386-opc.h (CpuAMD64): Removed.
 134         (CpuIntel64): Likewise.
 135         (CpuMax): Set to CpuNo64.
 136         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 137         (AMD64): New.
 138         (Intel64): Likewise.
 139         (i386_opcode_modifier): Add amd64 and intel64.
 140         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 141         on call and jmp.
 142         * i386-init.h: Regenerated.
 143         * i386-tbl.h: Likewise.
 144
 145 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 146
 147         PR gas/20154
 148         * i386-gen.c (main): Fail if CpuMax is incorrect.
 149         * i386-opc.h (CpuMax): Set to CpuIntel64.
 150         * i386-tbl.h: Regenerated.
 151
 152 2016-05-27  Nick Clifton  <nickc@redhat.com>
 153
 154         PR target/20150
 155         * msp430-dis.c (msp430dis_read_two_bytes): New function.
 156         (msp430dis_opcode_unsigned): New function.
 157         (msp430dis_opcode_signed): New function.
 158         (msp430_singleoperand): Use the new opcode reading functions.
 159         Only disassenmble bytes if they were successfully read.
 160         (msp430_doubleoperand): Likewise.
 161         (msp430_branchinstr): Likewise.
 162         (msp430x_callx_instr): Likewise.
 163         (print_insn_msp430): Check that it is safe to read bytes before
 164         attempting disassembly.  Use the new opcode reading functions.
 165
 166 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
 167
 168         * ppc-opc.c (CY): New define.  Document it.
 169         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
 170
 171 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 172
 173         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
 174         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
 175         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
 176         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
 177         CPU_ANY_AVX_FLAGS.
 178         * i386-init.h: Regenerated.
 179
 180 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 181
 182         PR gas/20141
 183         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 184         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 185         * i386-init.h: Regenerated.
 186
 187 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 188
 189         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 190         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 191         * i386-init.h: Regenerated.
 192
 193 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 194
 195         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 196         information.
 197         (print_insn_arc): Set insn_type information.
 198         * arc-opc.c (C_CC): Add F_CLASS_COND.
 199         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 200         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 201         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 202         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 203         (brne, brne_s, jeq_s, jne_s): Likewise.
 204
 205 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 206
 207         * arc-tbl.h (neg): New instruction variant.
 208
 209 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 210
 211         * arc-dis.c (find_format, find_format, get_auxreg)
 212         (print_insn_arc): Changed.
 213         * arc-ext.h (INSERT_XOP): Likewise.
 214
 215 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 216
 217         * tic54x-dis.c (sprint_mmr): Adjust.
 218         * tic54x-opc.c: Likewise.
 219
 220 2016-05-19  Alan Modra  <amodra@gmail.com>
 221
 222         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
 223
 224 2016-05-19  Alan Modra  <amodra@gmail.com>
 225
 226         * ppc-opc.c: Formatting.
 227         (NSISIGNOPT): Define.
 228         (powerpc_opcodes <subis>): Use NSISIGNOPT.
 229
 230 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
 231
 232         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
 233         replacing references to `micromips_ase' throughout.
 234         (_print_insn_mips): Don't use file-level microMIPS annotation to
 235         determine the disassembly mode with the symbol table.
 236
 237 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
 238
 239         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
 240
 241 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
 242
 243         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
 244         mips64r6.
 245         * mips-opc.c (D34): New macro.
 246         (mips_builtin_opcodes): Define bposge32c for DSPr3.
 247
 248 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
 249
 250         * i386-dis.c (prefix_table): Add RDPID instruction.
 251         * i386-gen.c (cpu_flag_init): Add RDPID flag.
 252         (cpu_flags): Add RDPID bitfield.
 253         * i386-opc.h (enum): Add RDPID element.
 254         (i386_cpu_flags): Add RDPID field.
 255         * i386-opc.tbl: Add RDPID instruction.
 256         * i386-init.h: Regenerate.
 257         * i386-tbl.h: Regenerate.
 258
 259 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 260
 261         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
 262         branch type of a symbol.
 263         (print_insn): Likewise.
 264
 265 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 266
 267         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
 268         Mainline Security Extensions instructions.
 269         (thumb_opcodes): Add entries for narrow ARMv8-M Security
 270         Extensions instructions.
 271         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
 272         instructions.
 273         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
 274         special registers.
 275
 276 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
 277
 278         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
 279
 280 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
 281
 282         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
 283         (arcExtMap_genOpcode): Likewise.
 284         * arc-opc.c (arg_32bit_rc): Define new variable.
 285         (arg_32bit_u6): Likewise.
 286         (arg_32bit_limm): Likewise.
 287
 288 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 289
 290         * aarch64-gen.c (VERIFIER): Define.
 291         * aarch64-opc.c (VERIFIER): Define.
 292         (verify_ldpsw): Use static linkage.
 293         * aarch64-opc.h (verify_ldpsw): Remove.
 294         * aarch64-tbl.h: Use VERIFIER for verifiers.
 295
 296 2016-04-28  Nick Clifton  <nickc@redhat.com>
 297
 298         PR target/19722
 299         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
 300         * aarch64-opc.c (verify_ldpsw): New function.
 301         * aarch64-opc.h (verify_ldpsw): New prototype.
 302         * aarch64-tbl.h: Add initialiser for verifier field.
 303         (LDPSW): Set verifier to verify_ldpsw.
 304
 305 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
 306
 307         PR binutils/19983
 308         PR binutils/19984
 309         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
 310         smaller than address size.
 311
 312 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 313
 314         * alpha-dis.c: Regenerate.
 315         * crx-dis.c: Likewise.
 316         * disassemble.c: Likewise.
 317         * epiphany-opc.c: Likewise.
 318         * fr30-opc.c: Likewise.
 319         * frv-opc.c: Likewise.
 320         * ip2k-opc.c: Likewise.
 321         * iq2000-opc.c: Likewise.
 322         * lm32-opc.c: Likewise.
 323         * lm32-opinst.c: Likewise.
 324         * m32c-opc.c: Likewise.
 325         * m32r-opc.c: Likewise.
 326         * m32r-opinst.c: Likewise.
 327         * mep-opc.c: Likewise.
 328         * mt-opc.c: Likewise.
 329         * or1k-opc.c: Likewise.
 330         * or1k-opinst.c: Likewise.
 331         * tic80-opc.c: Likewise.
 332         * xc16x-opc.c: Likewise.
 333         * xstormy16-opc.c: Likewise.
 334
 335 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 336
 337         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
 338         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
 339         calcsd, and calcxd instructions.
 340         * arc-opc.c (insert_nps_bitop_size): Delete.
 341         (extract_nps_bitop_size): Delete.
 342         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
 343         (extract_nps_qcmp_m3): Define.
 344         (extract_nps_qcmp_m2): Define.
 345         (extract_nps_qcmp_m1): Define.
 346         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
 347         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
 348         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
 349         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
 350         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
 351         NPS_QCMP_M3.
 352
 353 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 354
 355         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
 356
 357 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 358
 359         * Makefile.in: Regenerated with automake 1.11.6.
 360         * aclocal.m4: Likewise.
 361
 362 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 363
 364         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
 365         instructions.
 366         * arc-opc.c (insert_nps_cmem_uimm16): New function.
 367         (extract_nps_cmem_uimm16): New function.
 368         (arc_operands): Add NPS_XLDST_UIMM16 operand.
 369
 370 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 371
 372         * arc-dis.c (arc_insn_length): New function.
 373         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
 374         (find_format): Change insnLen parameter to unsigned.
 375
 376 2016-04-13  Nick Clifton  <nickc@redhat.com>
 377
 378         PR target/19937
 379         * v850-opc.c (v850_opcodes): Correct masks for long versions of
 380         the LD.B and LD.BU instructions.
 381
 382 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 383
 384         * arc-dis.c (find_format): Check for extension flags.
 385         (print_flags): New function.
 386         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
 387         .extAuxRegister.
 388         * arc-ext.c (arcExtMap_coreRegName): Use
 389         LAST_EXTENSION_CORE_REGISTER.
 390         (arcExtMap_coreReadWrite): Likewise.
 391         (dump_ARC_extmap): Update printing.
 392         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
 393         (arc_aux_regs): Add cpu field.
 394         * arc-regs.h: Add cpu field, lower case name aux registers.
 395
 396 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 397
 398         * arc-tbl.h: Add rtsc, sleep with no arguments.
 399
 400 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 401
 402         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
 403         Initialize.
 404         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
 405         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
 406         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
 407         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
 408         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
 409         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
 410         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
 411         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
 412         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
 413         (arc_opcode arc_opcodes): Null terminate the array.
 414         (arc_num_opcodes): Remove.
 415         * arc-ext.h (INSERT_XOP): Define.
 416         (extInstruction_t): Likewise.
 417         (arcExtMap_instName): Delete.
 418         (arcExtMap_insn): New function.
 419         (arcExtMap_genOpcode): Likewise.
 420         * arc-ext.c (ExtInstruction): Remove.
 421         (create_map): Zero initialize instruction fields.
 422         (arcExtMap_instName): Remove.
 423         (arcExtMap_insn): New function.
 424         (dump_ARC_extmap): More info while debuging.
 425         (arcExtMap_genOpcode): New function.
 426         * arc-dis.c (find_format): New function.
 427         (print_insn_arc): Use find_format.
 428         (arc_get_disassembler): Enable dump_ARC_extmap only when
 429         debugging.
 430
 431 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
 432
 433         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
 434         instruction bits out.
 435
 436 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 437
 438         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
 439         * arc-opc.c (arc_flag_operands): Add new flags.
 440         (arc_flag_classes): Add new classes.
 441
 442 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 443
 444         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
 445
 446 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
 447
 448         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
 449         encode1, rflt, crc16, and crc32 instructions.
 450         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
 451         (arc_flag_classes): Add C_NPS_R.
 452         (insert_nps_bitop_size_2b): New function.
 453         (extract_nps_bitop_size_2b): Likewise.
 454         (insert_nps_bitop_uimm8): Likewise.
 455         (extract_nps_bitop_uimm8): Likewise.
 456         (arc_operands): Add new operand entries.
 457
 458 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
 459
 460         * arc-regs.h: Add a new subclass field.  Add double assist
 461         accumulator register values.
 462         * arc-tbl.h: Use DPA subclass to mark the double assist
 463         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
 464         * arc-opc.c (RSP): Define instead of SP.
 465         (arc_aux_regs): Add the subclass field.
 466
 467 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
 468
 469         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
 470
 471 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
 472
 473         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
 474         NPS_R_SRC1.
 475
 476 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
 477
 478         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
 479         issues.  No functional changes.
 480
 481 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
 482
 483         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
 484         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
 485         (RTT): Remove duplicate.
 486         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
 487         (PCT_CONFIG*): Remove.
 488         (D1L, D1H, D2H, D2L): Define.
 489
 490 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 491
 492         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
 493
 494 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 495
 496         * arc-tbl.h (invld07): Remove.
 497         * arc-ext-tbl.h: New file.
 498         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
 499         * arc-opc.c (arc_opcodes): Add ext-tbl include.
 500
 501 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
 502
 503         Fix -Wstack-usage warnings.
 504         * aarch64-dis.c (print_operands): Substitute size.
 505         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
 506
 507 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 508
 509         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
 510         to get a proper diagnostic when an invalid ASR register is used.
 511
 512 2016-03-22  Nick Clifton  <nickc@redhat.com>
 513
 514         * configure: Regenerate.
 515
 516 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 517
 518         * arc-nps400-tbl.h: New file.
 519         * arc-opc.c: Add top level comment.
 520         (insert_nps_3bit_dst): New function.
 521         (extract_nps_3bit_dst): New function.
 522         (insert_nps_3bit_src2): New function.
 523         (extract_nps_3bit_src2): New function.
 524         (insert_nps_bitop_size): New function.
 525         (extract_nps_bitop_size): New function.
 526         (arc_flag_operands): Add nps400 entries.
 527         (arc_flag_classes): Add nps400 entries.
 528         (arc_operands): Add nps400 entries.
 529         (arc_opcodes): Add nps400 include.
 530
 531 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 532
 533         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
 534         the new class enum values.
 535
 536 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 537
 538         * arc-dis.c (print_insn_arc): Handle nps400.
 539
 540 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 541
 542         * arc-opc.c (BASE): Delete.
 543
 544 2016-03-18  Nick Clifton  <nickc@redhat.com>
 545
 546         PR target/19721
 547         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
 548         of MOV insn that aliases an ORR insn.
 549
 550 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
 551
 552         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
 553
 554 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 555
 556         * mcore-opc.h: Add const qualifiers.
 557         * microblaze-opc.h (struct op_code_struct): Likewise.
 558         * sh-opc.h: Likewise.
 559         * tic4x-dis.c (tic4x_print_indirect): Likewise.
 560         (tic4x_print_op): Likewise.
 561
 562 2016-03-02  Alan Modra  <amodra@gmail.com>
 563
 564         * or1k-desc.h: Regenerate.
 565         * fr30-ibld.c: Regenerate.
 566         * rl78-decode.c: Regenerate.
 567
 568 2016-03-01  Nick Clifton  <nickc@redhat.com>
 569
 570         PR target/19747
 571         * rl78-dis.c (print_insn_rl78_common): Fix typo.
 572
 573 2016-02-24  Renlin Li  <renlin.li@arm.com>
 574
 575         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
 576         (print_insn_coprocessor): Support fp16 instructions.
 577
 578 2016-02-24  Renlin Li  <renlin.li@arm.com>
 579
 580         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
 581         vminnm, vrint(mpna).
 582
 583 2016-02-24  Renlin Li  <renlin.li@arm.com>
 584
 585         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
 586         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
 587
 588 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
 589
 590         * i386-dis.c (print_insn): Parenthesize expression to prevent
 591         truncated addresses.
 592         (OP_J): Likewise.
 593
 594 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
 595             Janek van Oirschot  <jvanoirs@synopsys.com>
 596
 597         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
 598         variable.
 599
 600 2016-02-04  Nick Clifton  <nickc@redhat.com>
 601
 602         PR target/19561
 603         * msp430-dis.c (print_insn_msp430): Add a special case for
 604         decoding an RRC instruction with the ZC bit set in the extension
 605         word.
 606
 607 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 608
 609         * cgen-ibld.in (insert_normal): Rework calculation of shift.
 610         * epiphany-ibld.c: Regenerate.
 611         * fr30-ibld.c: Regenerate.
 612         * frv-ibld.c: Regenerate.
 613         * ip2k-ibld.c: Regenerate.
 614         * iq2000-ibld.c: Regenerate.
 615         * lm32-ibld.c: Regenerate.
 616         * m32c-ibld.c: Regenerate.
 617         * m32r-ibld.c: Regenerate.
 618         * mep-ibld.c: Regenerate.
 619         * mt-ibld.c: Regenerate.
 620         * or1k-ibld.c: Regenerate.
 621         * xc16x-ibld.c: Regenerate.
 622         * xstormy16-ibld.c: Regenerate.
 623
 624 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 625
 626         * epiphany-dis.c: Regenerated from latest cpu files.
 627
 628 2016-02-01  Michael McConville  <mmcco@mykolab.com>
 629
 630         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
 631         test bit.
 632
 633 2016-01-25  Renlin Li  <renlin.li@arm.com>
 634
 635         * arm-dis.c (mapping_symbol_for_insn): New function.
 636         (find_ifthen_state): Call mapping_symbol_for_insn().
 637
 638 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
 639
 640         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
 641         of MSR UAO immediate operand.
 642
 643 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
 644
 645         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
 646         instruction support.
 647
 648 2016-01-17  Alan Modra  <amodra@gmail.com>
 649
 650         * configure: Regenerate.
 651
 652 2016-01-14  Nick Clifton  <nickc@redhat.com>
 653
 654         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
 655         instructions that can support stack pointer operations.
 656         * rl78-decode.c: Regenerate.
 657         * rl78-dis.c: Fix display of stack pointer in MOVW based
 658         instructions.
 659
 660 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
 661
 662         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
 663         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
 664         erxtatus_el1 and erxaddr_el1.
 665
 666 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
 667
 668         * arm-dis.c (arm_opcodes): Add "esb".
 669         (thumb_opcodes): Likewise.
 670
 671 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
 672
 673         * ppc-opc.c <xscmpnedp>: Delete.
 674         <xvcmpnedp>: Likewise.
 675         <xvcmpnedp.>: Likewise.
 676         <xvcmpnesp>: Likewise.
 677         <xvcmpnesp.>: Likewise.
 678
 679 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
 680
 681         PR gas/13050
 682         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
 683         addition to ISA_A.
 684
 685 2016-01-01  Alan Modra  <amodra@gmail.com>
 686
 687         Update year range in copyright notice of all files.
 688
 689 For older changes see ChangeLog-2015
 690 \f
 691 Copyright (C) 2016 Free Software Foundation, Inc.
 692
 693 Copying and distribution of this file, with or without modification,
 694 are permitted in any medium without royalty provided the copyright
 695 notice and this notice are preserved.
 696
 697 Local Variables:
 698 mode: change-log
 699 left-margin: 8
 700 fill-column: 74
 701 version-control: never
 702 End: