1 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
3 * i386-dis.c (RM_0FAE_REG_5): Removed.
4 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
5 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
6 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
7 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
8 PREFIX_MOD_3_0F01_REG_5_RM_0.
9 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
10 PREFIX_MOD_3_0FAE_REG_5.
11 (mod_table): Update MOD_0FAE_REG_5.
12 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
13 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
14 * i386-tbl.h: Regenerated.
16 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
18 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
19 * i386-opc.tbl: Likewise.
20 * i386-tbl.h: Regenerated.
22 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
24 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
26 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
29 2017-06-19 Nick Clifton <nickc@redhat.com>
32 * score-dis.c (score_opcodes): Add sentinel.
34 2017-06-16 Alan Modra <amodra@gmail.com>
36 * rx-decode.c: Regenerate.
38 2017-06-15 H.J. Lu <hongjiu.lu@intel.com>
41 * i386-dis.c (OP_E_register): Check valid bnd register.
44 2017-06-15 Nick Clifton <nickc@redhat.com>
47 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
50 2017-06-15 Nick Clifton <nickc@redhat.com>
53 * rl78-decode.opc (OP_BUF_LEN): Define.
54 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
55 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
57 * rl78-decode.c: Regenerate.
59 2017-06-15 Nick Clifton <nickc@redhat.com>
62 * bfin-dis.c (gregs): Clip index to prevent overflow.
67 2017-06-14 Nick Clifton <nickc@redhat.com>
70 * score7-dis.c (score_opcodes): Add sentinel.
72 2017-06-14 Yao Qi <yao.qi@linaro.org>
74 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
75 * arm-dis.c: Likewise.
76 * ia64-dis.c: Likewise.
77 * mips-dis.c: Likewise.
78 * spu-dis.c: Likewise.
79 * disassemble.h (print_insn_aarch64): New declaration, moved from
81 (print_insn_big_arm, print_insn_big_mips): Likewise.
82 (print_insn_i386, print_insn_ia64): Likewise.
83 (print_insn_little_arm, print_insn_little_mips): Likewise.
85 2017-06-14 Nick Clifton <nickc@redhat.com>
88 * rx-decode.opc: Include libiberty.h
89 (GET_SCALE): New macro - validates access to SCALE array.
90 (GET_PSCALE): New macro - validates access to PSCALE array.
91 (DIs, SIs, S2Is, rx_disp): Use new macros.
92 * rx-decode.c: Regenerate.
94 2017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
96 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
98 2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
100 * arc-dis.c (enforced_isa_mask): Declare.
101 (cpu_types): Likewise.
102 (parse_cpu_option): New function.
103 (parse_disassembler_options): Use it.
104 (print_insn_arc): Use enforced_isa_mask.
105 (print_arc_disassembler_options): Document new options.
107 2017-05-24 Yao Qi <yao.qi@linaro.org>
109 * alpha-dis.c: Include disassemble.h, don't include
111 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
112 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
113 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
114 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
115 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
116 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
117 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
118 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
119 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
120 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
121 * moxie-dis.c, msp430-dis.c, mt-dis.c:
122 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
123 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
124 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
125 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
126 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
127 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
128 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
129 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
130 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
131 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
132 * z80-dis.c, z8k-dis.c: Likewise.
133 * disassemble.h: New file.
135 2017-05-24 Yao Qi <yao.qi@linaro.org>
137 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
138 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
140 2017-05-24 Yao Qi <yao.qi@linaro.org>
142 * disassemble.c (disassembler): Add arguments a, big and mach.
145 2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
147 * i386-dis.c (NOTRACK_Fixup): New.
149 (NOTRACK_PREFIX): Likewise.
150 (last_active_prefix): Likewise.
151 (reg_table): Use NOTRACK on indirect call and jmp.
152 (ckprefix): Set last_active_prefix.
153 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
154 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
155 * i386-opc.h (NoTrackPrefixOk): New.
156 (i386_opcode_modifier): Add notrackprefixok.
157 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
159 * i386-tbl.h: Regenerated.
161 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
163 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
165 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
167 (print_insn_sparc): Handle new operand types.
168 * sparc-opc.c (MASK_M8): Define.
170 (v6notlet): Likewise.
181 (v9andleon): Likewise.
184 (HWS2_VM8): Likewise.
185 (sparc_opcode_archs): Add entry for "m8".
186 (sparc_opcodes): Add OSA2017 and M8 instructions
187 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
189 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
190 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
191 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
192 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
193 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
194 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
195 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
196 ASI_CORE_SELECT_COMMIT_NHT.
198 2017-05-18 Alan Modra <amodra@gmail.com>
200 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
201 * aarch64-dis.c: Likewise.
202 * aarch64-gen.c: Likewise.
203 * aarch64-opc.c: Likewise.
205 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
206 Matthew Fortune <matthew.fortune@imgtec.com>
208 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
209 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
210 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
211 (print_insn_arg) <OP_REG28>: Add handler.
212 (validate_insn_args) <OP_REG28>: Handle.
213 (print_mips16_insn_arg): Handle MIPS16 instructions that require
214 32-bit encoding and 9-bit immediates.
215 (print_insn_mips16): Handle MIPS16 instructions that require
216 32-bit encoding and MFC0/MTC0 operand decoding.
217 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
218 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
219 (RD_C0, WR_C0, E2, E2MT): New macros.
220 (mips16_opcodes): Add entries for MIPS16e2 instructions:
221 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
222 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
223 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
224 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
225 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
226 instructions, "swl", "swr", "sync" and its "sync_acquire",
227 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
228 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
229 regular/extended entries for original MIPS16 ISA revision
230 instructions whose extended forms are subdecoded in the MIPS16e2
231 ISA revision: "li", "sll" and "srl".
233 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
235 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
236 reference in CP0 move operand decoding.
238 2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
240 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
242 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
244 2017-05-11 Maciej W. Rozycki <macro@imgtec.com>
246 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
247 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
248 "sync_rmb" and "sync_wmb" as aliases.
249 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
250 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
252 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
254 * arc-dis.c (parse_option): Update quarkse_em option..
255 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
257 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
259 2017-05-03 Kito Cheng <kito.cheng@gmail.com>
261 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
263 2017-05-01 Michael Clark <michaeljclark@mac.com>
265 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
268 2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
270 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
271 and branches and not synthetic data instructions.
273 2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
275 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
277 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
279 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
280 * arc-opc.c (insert_r13el): New function.
282 * arc-tbl.h: Add new enter/leave variants.
284 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
286 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
288 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
290 * mips-dis.c (print_mips_disassembler_options): Add
293 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
295 * mips16-opc.c (AL): New macro.
296 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
297 of "ld" and "lw" as aliases.
299 2017-04-24 Tamar Christina <tamar.christina@arm.com>
301 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
304 2017-04-22 Alexander Fedotov <alfedotov@gmail.com>
305 Alan Modra <amodra@gmail.com>
307 * ppc-opc.c (ELEV): Define.
308 (vle_opcodes): Add se_rfgi and e_sc.
309 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
312 2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
314 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
316 2017-04-21 Nick Clifton <nickc@redhat.com>
319 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
322 2017-04-13 Alan Modra <amodra@gmail.com>
324 * epiphany-desc.c: Regenerate.
325 * fr30-desc.c: Regenerate.
326 * frv-desc.c: Regenerate.
327 * ip2k-desc.c: Regenerate.
328 * iq2000-desc.c: Regenerate.
329 * lm32-desc.c: Regenerate.
330 * m32c-desc.c: Regenerate.
331 * m32r-desc.c: Regenerate.
332 * mep-desc.c: Regenerate.
333 * mt-desc.c: Regenerate.
334 * or1k-desc.c: Regenerate.
335 * xc16x-desc.c: Regenerate.
336 * xstormy16-desc.c: Regenerate.
338 2017-04-11 Alan Modra <amodra@gmail.com>
340 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
341 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
342 PPC_OPCODE_TMR for e6500.
343 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
344 (PPCVEC3): Define as PPC_OPCODE_POWER9.
345 (PPCVSX2): Define as PPC_OPCODE_POWER8.
346 (PPCVSX3): Define as PPC_OPCODE_POWER9.
347 (PPCHTM): Define as PPC_OPCODE_POWER8.
348 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
350 2017-04-10 Alan Modra <amodra@gmail.com>
352 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
353 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
354 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
355 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
357 2017-04-09 Pip Cet <pipcet@gmail.com>
359 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
360 appropriate floating-point precision directly.
362 2017-04-07 Alan Modra <amodra@gmail.com>
364 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
365 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
366 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
367 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
368 vector instructions with E6500 not PPCVEC2.
370 2017-04-06 Pip Cet <pipcet@gmail.com>
372 * Makefile.am: Add wasm32-dis.c.
373 * configure.ac: Add wasm32-dis.c to wasm32 target.
374 * disassemble.c: Add wasm32 disassembler code.
375 * wasm32-dis.c: New file.
376 * Makefile.in: Regenerate.
377 * configure: Regenerate.
378 * po/POTFILES.in: Regenerate.
379 * po/opcodes.pot: Regenerate.
381 2017-04-05 Pedro Alves <palves@redhat.com>
383 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
384 * arm-dis.c (parse_arm_disassembler_options): Constify.
385 * ppc-dis.c (powerpc_init_dialect): Constify local.
386 * vax-dis.c (parse_disassembler_options): Constify.
388 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
390 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
393 2017-03-30 Pip Cet <pipcet@gmail.com>
395 * configure.ac: Add (empty) bfd_wasm32_arch target.
396 * configure: Regenerate
397 * po/opcodes.pot: Regenerate.
399 2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
401 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
403 * opcodes/sparc-opc.c (asi_table): New ASIs.
405 2017-03-29 Alan Modra <amodra@gmail.com>
407 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
409 (lookup_powerpc): Don't special case -1 dialect. Handle
411 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
412 lookup_powerpc call, pass it on second.
414 2017-03-27 Alan Modra <amodra@gmail.com>
417 * ppc-dis.c (struct ppc_mopt): Comment.
418 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
420 2017-03-27 Rinat Zelig <rinat@mellanox.com>
422 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
423 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
424 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
425 (insert_nps_misc_imm_offset): New function.
426 (extract_nps_misc imm_offset): New function.
427 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
428 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
430 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
432 * s390-mkopc.c (main): Remove vx2 check.
433 * s390-opc.txt: Remove vx2 instruction flags.
435 2017-03-21 Rinat Zelig <rinat@mellanox.com>
437 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
438 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
439 (insert_nps_imm_offset): New function.
440 (extract_nps_imm_offset): New function.
441 (insert_nps_imm_entry): New function.
442 (extract_nps_imm_entry): New function.
444 2017-03-17 Alan Modra <amodra@gmail.com>
447 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
448 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
449 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
451 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
453 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
457 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
459 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
461 2017-03-13 Andrew Waterman <andrew@sifive.com>
463 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
468 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
470 * i386-gen.c (opcode_modifiers): Replace S with Load.
471 * i386-opc.h (S): Removed.
473 (i386_opcode_modifier): Replace s with load.
474 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
475 and {evex}. Replace S with Load.
476 * i386-tbl.h: Regenerated.
478 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
480 * i386-opc.tbl: Use CpuCET on rdsspq.
481 * i386-tbl.h: Regenerated.
483 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
485 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
486 <vsx>: Do not use PPC_OPCODE_VSX3;
488 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
490 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
492 2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
494 * i386-dis.c (REG_0F1E_MOD_3): New enum.
495 (MOD_0F1E_PREFIX_1): Likewise.
496 (MOD_0F38F5_PREFIX_2): Likewise.
497 (MOD_0F38F6_PREFIX_0): Likewise.
498 (RM_0F1E_MOD_3_REG_7): Likewise.
499 (PREFIX_MOD_0_0F01_REG_5): Likewise.
500 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
501 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
502 (PREFIX_0F1E): Likewise.
503 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
504 (PREFIX_0F38F5): Likewise.
505 (dis386_twobyte): Use PREFIX_0F1E.
506 (reg_table): Add REG_0F1E_MOD_3.
507 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
508 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
509 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
510 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
511 (three_byte_table): Use PREFIX_0F38F5.
512 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
513 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
514 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
515 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
516 PREFIX_MOD_3_0F01_REG_5_RM_2.
517 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
518 (cpu_flags): Add CpuCET.
519 * i386-opc.h (CpuCET): New enum.
520 (CpuUnused): Commented out.
521 (i386_cpu_flags): Add cpucet.
522 * i386-opc.tbl: Add Intel CET instructions.
523 * i386-init.h: Regenerated.
524 * i386-tbl.h: Likewise.
526 2017-03-06 Alan Modra <amodra@gmail.com>
529 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
530 (extract_raq, extract_ras, extract_rbx): New functions.
531 (powerpc_operands): Use opposite corresponding insert function.
533 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
534 register restriction.
536 2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
538 * disassemble.c Include "safe-ctype.h".
539 (disassemble_init_for_target): Handle s390 init.
540 (remove_whitespace_and_extra_commas): New function.
541 (disassembler_options_cmp): Likewise.
542 * arm-dis.c: Include "libiberty.h".
544 (regnames): Use long disassembler style names.
545 Add force-thumb and no-force-thumb options.
546 (NUM_ARM_REGNAMES): Rename from this...
547 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
548 (get_arm_regname_num_options): Delete.
549 (set_arm_regname_option): Likewise.
550 (get_arm_regnames): Likewise.
551 (parse_disassembler_options): Likewise.
552 (parse_arm_disassembler_option): Rename from this...
553 (parse_arm_disassembler_options): ...to this. Make static.
554 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
555 (print_insn): Use parse_arm_disassembler_options.
556 (disassembler_options_arm): New function.
557 (print_arm_disassembler_options): Handle updated regnames.
558 * ppc-dis.c: Include "libiberty.h".
559 (ppc_opts): Add "32" and "64" entries.
560 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
561 (powerpc_init_dialect): Add break to switch statement.
562 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
563 (disassembler_options_powerpc): New function.
564 (print_ppc_disassembler_options): Use ARRAY_SIZE.
565 Remove printing of "32" and "64".
566 * s390-dis.c: Include "libiberty.h".
567 (init_flag): Remove unneeded variable.
568 (struct s390_options_t): New structure type.
569 (options): New structure.
570 (init_disasm): Rename from this...
571 (disassemble_init_s390): ...to this. Add initializations for
572 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
573 (print_insn_s390): Delete call to init_disasm.
574 (disassembler_options_s390): New function.
575 (print_s390_disassembler_options): Print using information from
577 * po/opcodes.pot: Regenerate.
579 2017-02-28 Jan Beulich <jbeulich@suse.com>
581 * i386-dis.c (PCMPESTR_Fixup): New.
582 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
583 (prefix_table): Use PCMPESTR_Fixup.
584 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
586 (vex_w_table): Delete VPCMPESTR{I,M} entries.
587 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
588 Split 64-bit and non-64-bit variants.
589 * opcodes/i386-tbl.h: Re-generate.
591 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
593 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
594 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
595 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
596 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
597 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
598 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
599 (OP_SVE_V_HSD): New macros.
600 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
601 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
602 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
603 (aarch64_opcode_table): Add new SVE instructions.
604 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
605 for rotation operands. Add new SVE operands.
606 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
607 (ins_sve_quad_index): Likewise.
608 (ins_imm_rotate): Split into...
609 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
610 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
611 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
613 (aarch64_ins_sve_addr_ri_s4): New function.
614 (aarch64_ins_sve_quad_index): Likewise.
615 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
616 * aarch64-asm-2.c: Regenerate.
617 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
618 (ext_sve_quad_index): Likewise.
619 (ext_imm_rotate): Split into...
620 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
621 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
622 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
624 (aarch64_ext_sve_addr_ri_s4): New function.
625 (aarch64_ext_sve_quad_index): Likewise.
626 (aarch64_ext_sve_index): Allow quad indices.
627 (do_misc_decoding): Likewise.
628 * aarch64-dis-2.c: Regenerate.
629 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
631 (OPD_F_OD_MASK): Widen by one bit.
632 (OPD_F_NO_ZR): Bump accordingly.
633 (get_operand_field_width): New function.
634 * aarch64-opc.c (fields): Add new SVE fields.
635 (operand_general_constraint_met_p): Handle new SVE operands.
636 (aarch64_print_operand): Likewise.
637 * aarch64-opc-2.c: Regenerate.
639 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
641 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
642 (aarch64_feature_compnum): ...this.
643 (SIMD_V8_3): Replace with...
645 (CNUM_INSN): New macro.
646 (aarch64_opcode_table): Use it for the complex number instructions.
648 2017-02-24 Jan Beulich <jbeulich@suse.com>
650 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
652 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
654 Add support for associating SPARC ASIs with an architecture level.
655 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
656 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
657 decoding of SPARC ASIs.
659 2017-02-23 Jan Beulich <jbeulich@suse.com>
661 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
662 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
664 2017-02-21 Jan Beulich <jbeulich@suse.com>
666 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
667 1 (instead of to itself). Correct typo.
669 2017-02-14 Andrew Waterman <andrew@sifive.com>
671 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
674 2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
676 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
677 (aarch64_sys_reg_supported_p): Handle them.
679 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
681 * arc-opc.c (UIMM6_20R): Define.
682 (SIMM12_20): Use above.
683 (SIMM12_20R): Define.
684 (SIMM3_5_S): Use above.
685 (UIMM7_A32_11R_S): Define.
686 (UIMM7_9_S): Use above.
687 (UIMM3_13R_S): Define.
688 (SIMM11_A32_7_S): Use above.
690 (UIMM10_A32_8_S): Use above.
691 (UIMM8_8R_S): Define.
693 (arc_relax_opcodes): Use all above defines.
695 2017-02-15 Vineet Gupta <vgupta@synopsys.com>
697 * arc-regs.h: Distinguish some of the registers different on
698 ARC700 and HS38 cpus.
700 2017-02-14 Alan Modra <amodra@gmail.com>
703 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
704 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
706 2017-02-11 Stafford Horne <shorne@gmail.com>
707 Alan Modra <amodra@gmail.com>
709 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
710 Use insn_bytes_value and insn_int_value directly instead. Don't
711 free allocated memory until function exit.
713 2017-02-10 Nicholas Piggin <npiggin@gmail.com>
715 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
717 2017-02-03 Nick Clifton <nickc@redhat.com>
720 * aarch64-opc.c (print_register_list): Ensure that the register
721 list index will fir into the tb buffer.
722 (print_register_offset_address): Likewise.
723 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
725 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
728 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
729 instructions when the previous fetch packet ends with a 32-bit
732 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
734 * pru-opc.c: Remove vague reference to a future GDB port.
736 2017-01-20 Nick Clifton <nickc@redhat.com>
738 * po/ga.po: Updated Irish translation.
740 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
742 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
744 2017-01-13 Yao Qi <yao.qi@linaro.org>
746 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
747 if FETCH_DATA returns 0.
748 (m68k_scan_mask): Likewise.
749 (print_insn_m68k): Update code to handle -1 return value.
751 2017-01-13 Yao Qi <yao.qi@linaro.org>
753 * m68k-dis.c (enum print_insn_arg_error): New.
754 (NEXTBYTE): Replace -3 with
755 PRINT_INSN_ARG_MEMORY_ERROR.
756 (NEXTULONG): Likewise.
757 (NEXTSINGLE): Likewise.
758 (NEXTDOUBLE): Likewise.
759 (NEXTDOUBLE): Likewise.
760 (NEXTPACKED): Likewise.
761 (FETCH_ARG): Likewise.
762 (FETCH_DATA): Update comments.
763 (print_insn_arg): Update comments. Replace magic numbers with
765 (match_insn_m68k): Likewise.
767 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
769 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
770 * i386-dis-evex.h (evex_table): Updated.
771 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
772 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
773 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
774 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
775 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
776 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
777 * i386-init.h: Regenerate.
780 2017-01-12 Yao Qi <yao.qi@linaro.org>
782 * msp430-dis.c (msp430_singleoperand): Return -1 if
783 msp430dis_opcode_signed returns false.
784 (msp430_doubleoperand): Likewise.
785 (msp430_branchinstr): Return -1 if
786 msp430dis_opcode_unsigned returns false.
787 (msp430x_calla_instr): Likewise.
788 (print_insn_msp430): Likewise.
790 2017-01-05 Nick Clifton <nickc@redhat.com>
793 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
794 could not be matched.
795 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
798 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
800 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
801 (aarch64_opcode_table): Use RCPC_INSN.
803 2017-01-03 Kito Cheng <kito.cheng@gmail.com>
805 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
807 * riscv-opcodes/all-opcodes: Likewise.
809 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
811 * riscv-dis.c (print_insn_args): Add fall through comment.
813 2017-01-03 Nick Clifton <nickc@redhat.com>
815 * po/sr.po: New Serbian translation.
816 * configure.ac (ALL_LINGUAS): Add sr.
817 * configure: Regenerate.
819 2017-01-02 Alan Modra <amodra@gmail.com>
821 * epiphany-desc.h: Regenerate.
822 * epiphany-opc.h: Regenerate.
823 * fr30-desc.h: Regenerate.
824 * fr30-opc.h: Regenerate.
825 * frv-desc.h: Regenerate.
826 * frv-opc.h: Regenerate.
827 * ip2k-desc.h: Regenerate.
828 * ip2k-opc.h: Regenerate.
829 * iq2000-desc.h: Regenerate.
830 * iq2000-opc.h: Regenerate.
831 * lm32-desc.h: Regenerate.
832 * lm32-opc.h: Regenerate.
833 * m32c-desc.h: Regenerate.
834 * m32c-opc.h: Regenerate.
835 * m32r-desc.h: Regenerate.
836 * m32r-opc.h: Regenerate.
837 * mep-desc.h: Regenerate.
838 * mep-opc.h: Regenerate.
839 * mt-desc.h: Regenerate.
840 * mt-opc.h: Regenerate.
841 * or1k-desc.h: Regenerate.
842 * or1k-opc.h: Regenerate.
843 * xc16x-desc.h: Regenerate.
844 * xc16x-opc.h: Regenerate.
845 * xstormy16-desc.h: Regenerate.
846 * xstormy16-opc.h: Regenerate.
848 2017-01-02 Alan Modra <amodra@gmail.com>
850 Update year range in copyright notice of all files.
852 For older changes see ChangeLog-2016
854 Copyright (C) 2017 Free Software Foundation, Inc.
856 Copying and distribution of this file, with or without modification,
857 are permitted in any medium without royalty provided the copyright
858 notice and this notice are preserved.
864 version-control: never