opcodes/ChangeLog

   1 2015-12-22  Yoshinori Sato <ysato@users.sourceforge.jp>
   2
   3 opcodes/
   4         * rx-decode.opc (movco): Use uniqe id.
   5         (movli): Likewise.
   6         (stnz): Condition fix.
   7         (mvtacgu): Destination fix.
   8         * rx-decode.c: Regenerate.
   9
  10 2015-12-14  Yoshinori Sato <ysato@users.sourceforge.jp>
  11
  12         * rx-deocde.opc: Add new instructions pattern.
  13         * rx-deocde.c: Regenerate.
  14         * rx-dis.c (register_name): Add new register.
  15
  16 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  17
  18         * aarch64-asm-2.c: Regenerate.
  19         * aarch64-dis-2.c: Regenerate.
  20         * aarch64-opc-2.c: Regenerate.
  21         * aarch64-tbl.h (QL_SSHIFT_H): New.
  22         (aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
  23         and fcvtzu to the Adv.SIMD scalar shift by immediate group.
  24
  25 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  26
  27         * aarch64-asm-2.c: Regenerate.
  28         * aarch64-dis-2.c: Regenerate.
  29         * aarch64-opc-2.c: Regenerate.
  30         * aarch64-tbl.h (QL_VSHIFT_H): New.
  31         (aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
  32         and fcvtzu to the Adv.SIMD shift by immediate group.
  33
  34 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  35
  36         * aarch64-asm-2.c: Regenerate.
  37         * aarch64-dis-2.c: Regenerate.
  38         * aarch64-opc-2.c: Regenerate.
  39         * aarch64-tbl.h (QL_SISD_PAIR_H): New.
  40         (aarch64_opcode_table): Add fp16 versions of fmaxnmp, faddp,
  41         fmaxp, fminnmp, fminp to the Adv.SIMD scalar pairwise group.
  42
  43 2015-12-14  Matthew Wahab  <matthew.wahab@arm.coM>
  44
  45         * aarch64-dis.c (get_vreg_qualifier_from_value): Update comment
  46         and adjust calculation to ignore qualifier for type 2H.
  47         * aarch64-opc.c (aarch64_opnd_qualifier): Add "2H".
  48
  49 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  50
  51         * aarch64-asm-2.c: Regenerate.
  52         * aarch64-dis-2.c: Regenerate.
  53         * aarch64-opc-2.c: Regenerate.
  54         * aarch64-tbl.h (QL_SIMD_IMM_H): New.
  55         (aarch64_opcode_table): Add fp16 version of fmov to the Adv.SIMD
  56         modified immediate group.
  57
  58 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  59
  60         * aarch64-asm-2.c: Regenerate.
  61         * aarch64-dis-2.c: Regenerate.
  62         * aarch64-opc-2.c: Regenerate.
  63         * aarch64-tbl.h (QL_XLANES_FP_H): New.
  64         (aarch64_opcode_table): Add fp16 versions of fmaxnmv, fmaxv,
  65         fminnmv, fminv to the Adv.SIMD across lanes group.
  66
  67 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  68
  69         * aarch64-asm-2.c: Regenerate.
  70         * aarch64-dis-2.c: Regenerate.
  71         * aarch64-opc-2.c: Regenerate.
  72         * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of fmla,
  73         fmls, fmul and fmulx to the scalar indexed element group.
  74
  75 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  76
  77         * aarch64-asm-2.c: Regenerate.
  78         * aarch64-dis-2.c: Regenerate.
  79         * aarch64-opc-2.c: Regenerate.
  80         * aarch64-tbl.h (QL_ELEMENT_FP_H): New.
  81         (aarch64_opcode_table): Add fp16 versions of fmla, fmls, fmul and
  82         fmulx to the vector indexed element group.
  83
  84 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  85
  86         * aarch64-asm-2.c: Regenerate.
  87         * aarch64-dis-2.c: Regenerate.
  88         * aarch64-opc-2.c: Regenerate.
  89         * aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
  90         (QL_S_2SAMEH): New.
  91         (aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
  92         fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
  93         frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
  94         fcvtzu and frsqrte to the scalar two register misc. group.
  95
  96 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  97
  98         * aarch64-asm-2.c: Regenerate.
  99         * aarch64-dis-2.c: Regenerate.
 100         * aarch64-opc-2.c: Regenerate.
 101         * aarch64-tbl.h (QL_V2SAMEH): New.
 102         (aarch64_opcode_table): Add fp16 versions of frintn, frintm,
 103         fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
 104         frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
 105         fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
 106         and fsqrt to the vector register misc. group.
 107
 108 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
 109
 110         * aarch64-asm-2.c: Regenerate.
 111         * aarch64-dis-2.c: Regenerate.
 112         * aarch64-opc-2.c: Regenerate.
 113         * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
 114         fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and facgt
 115         to the scalar three same group.
 116
 117 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
 118
 119         * aarch64-asm-2.c: Regenerate.
 120         * aarch64-dis-2.c: Regenerate.
 121         * aarch64-opc-2.c: Regenerate.
 122         * aarch64-tbl.h (QL_V3SAMEH): New.
 123         (aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
 124         fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
 125         fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
 126         fcmgt, facgt and fminp to the vector three same group.
 127
 128 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
 129
 130         * aarch64-tbl.h (aarch64_feature_simd_f16): New.
 131         (SIMD_F16): New.
 132
 133 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
 134
 135         * aarch64-opc.c (aarch64_sys_reg_supported_p): Add mistakenly
 136         removed statement.
 137         (aarch64_pstatefield_supported_p): Move feature checks for AT
 138         registers ..
 139         (aarch64_sys_ins_reg_supported_p): .. to here.
 140
 141 2015-12-12  Alan Modra  <amodra@gmail.com>
 142
 143         PR 19359
 144         * ppc-opc.c (insert_fxm): Remove "ignored" from error message.
 145         (powerpc_opcodes): Remove single-operand mfcr.
 146
 147 2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
 148
 149         * aarch64-asm.c (aarch64_ins_hint): New.
 150         * aarch64-asm.h (aarch64_ins_hint): Declare.
 151         * aarch64-dis.c (aarch64_ext_hint): New.
 152         * aarch64-dis.h (aarch64_ext_hint): Declare.
 153         * aarch64-opc-2.c: Regenerate.
 154         * aarch64-opc.c (aarch64_hint_options): New.
 155         * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.
 156
 157 2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
 158
 159         * aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.
 160
 161 2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
 162
 163         * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
 164         pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
 165         pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
 166         pmscr_el2.
 167         (aarch64_sys_reg_supported_p): Add architecture feature tests for
 168         the new registers.
 169
 170 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 171
 172         * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
 173         (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
 174         feature test for "s1e1rp" and "s1e1wp".
 175
 176 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 177
 178         * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
 179         (aarch64_sys_ins_reg_supported_p): New.
 180
 181 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 182
 183         * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
 184         with aarch64_sys_ins_reg_has_xt.
 185         (aarch64_ext_sysins_op): Likewise.
 186         * aarch64-opc.c (operand_general_constraint_met_p): Likewise.
 187         (F_HASXT): New.
 188         (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
 189         (aarch64_sys_regs_dc): Likewise.
 190         (aarch64_sys_regs_at): Likewise.
 191         (aarch64_sys_regs_tlbi): Likewise.
 192         (aarch64_sys_ins_reg_has_xt): New.
 193
 194 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 195
 196         * aarch64-opc.c (aarch64_sys_regs): Add "uao".
 197         (aarch64_sys_reg_supported_p): Add comment.  Add checks for "uao".
 198         (aarch64_pstatefields): Add "uao".
 199         (aarch64_pstatefield_supported_p): Add checks for "uao".
 200
 201 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 202
 203         * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
 204         "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
 205         "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
 206         (aarch64_sys_reg_supported_p): Add architecture feature tests for
 207         new registers.
 208
 209 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 210
 211         * aarch64-asm-2.c: Regenerate.
 212         * aarch64-dis-2.c: Regenerate.
 213         * aarch64-tbl.h (aarch64_feature_ras): New.
 214         (RAS): New.
 215         (aarch64_opcode_table): Add "esb".
 216
 217 2015-12-09  H.J. Lu  <hongjiu.lu@intel.com>
 218
 219         * i386-dis.c (MOD_0F01_REG_5): New.
 220         (RM_0F01_REG_5): Likewise.
 221         (reg_table): Use MOD_0F01_REG_5.
 222         (mod_table): Add MOD_0F01_REG_5.
 223         (rm_table): Add RM_0F01_REG_5.
 224         * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
 225         (cpu_flags): Add CpuOSPKE.
 226         * i386-opc.h (CpuOSPKE): New.
 227         (i386_cpu_flags): Add cpuospke.
 228         * i386-opc.tbl: Add rdpkru and wrpkru instructions.
 229         * i386-init.h: Regenerated.
 230         * i386-tbl.h: Likewise.
 231
 232 2015-12-07  DJ Delorie  <dj@redhat.com>
 233
 234         * rl78-decode.opc: Enable MULU for all ISAs.
 235         * rl78-decode.c: Regenerate.
 236
 237 2015-12-07  Alan Modra  <amodra@gmail.com>
 238
 239         * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
 240         major opcode/xop.
 241
 242 2015-12-04  Claudiu Zissulescu  <claziss@synopsys.com>
 243
 244         * arc-dis.c (special_flag_p): Match full mnemonic.
 245         * arc-opc.c (print_insn_arc): Check section size to read
 246         appropriate number of bytes. Fix printing.
 247         * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
 248         arguments.
 249
 250 2015-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 251
 252         * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
 253         <ldah>: ... to this.
 254
 255 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 256
 257         * aarch64-asm-2.c: Regenerate.
 258         * aarch64-dis-2.c: Regenerate.
 259         * aarch64-opc-2.c: Regenerate.
 260         * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
 261         (QL_INT2FP_H, QL_FP2INT_H): New.
 262         (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
 263         (QL_DST_H): New.
 264         (QL_FCCMP_H): New.
 265         (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
 266         fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
 267         fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
 268         fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
 269         frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
 270         fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
 271         fcsel.
 272
 273 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 274
 275         * aarch64-opc.c (half_conv_t): New.
 276         (expand_fp_imm): Replace is_dp flag with the parameter size to
 277         specify the number of bytes for the required expansion.  Treat
 278         a 16-bit expansion like a 32-bit expansion.  Add check for an
 279         unsupported size request.  Update comment.
 280         (aarch64_print_operand): Update to support 16-bit floating point
 281         values.  Update for changes to expand_fp_imm.
 282
 283 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 284
 285         * aarch64-tbl.h (aarch64_feature_fp_f16): New.
 286         (FP_F16): New.
 287
 288 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 289
 290         * aarch64-asm-2.c: Regenerate.
 291         * aarch64-dis-2.c: Regenerate.
 292         * aarch64-opc-2.c: Regenerate.
 293         * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
 294         "rev64".
 295
 296 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 297
 298         * aarch64-asm-2.c: Regenerate.
 299         * aarch64-asm.c (convert_bfc_to_bfm): New.
 300         (convert_to_real): Add case for OP_BFC.
 301         * aarch64-dis-2.c: Regenerate.
 302         * aarch64-dis.c: (convert_bfm_to_bfc): New.
 303         (convert_to_alias): Add case for OP_BFC.
 304         * aarch64-opc-2.c: Regenerate.
 305         * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
 306         to allow width operand in three-operand instructions.
 307         * aarch64-tbl.h (QL_BF1): New.
 308         (aarch64_feature_v8_2): New.
 309         (ARMV8_2): New.
 310         (aarch64_opcode_table): Add "bfc".
 311
 312 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 313
 314         * aarch64-asm-2.c: Regenerate.
 315         * aarch64-dis-2.c: Regenerate.
 316         * aarch64-dis.c: Weaken assert.
 317         * aarch64-gen.c: Include the instruction in the list of its
 318         possible aliases.
 319
 320 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 321
 322         * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
 323         (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
 324         feature test.
 325
 326 2015-11-23  Tristan Gingold  <gingold@adacore.com>
 327
 328         * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
 329
 330 2015-11-20  Matthew Wahab  <matthew.wahab@arm.com>
 331
 332         * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
 333         sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
 334         tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
 335         amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
 336         cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
 337         cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
 338         cnthv_ctl_el2, cnthv_cval_el2.
 339         (aarch64_sys_reg_supported_p): Update for the new system
 340         registers.
 341
 342 2015-11-20  Nick Clifton  <nickc@redhat.com>
 343
 344         PR binutils/19224
 345         * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
 346
 347 2015-11-20  Nick Clifton  <nickc@redhat.com>
 348
 349         * po/zh_CN.po: Updated simplified Chinese translation.
 350
 351 2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>
 352
 353         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
 354         of MSR PAN immediate operand.
 355
 356 2015-11-16  Nick Clifton  <nickc@redhat.com>
 357
 358         * rx-dis.c (condition_names): Replace always and never with
 359         invalid, since the always/never conditions can never be legal.
 360
 361 2015-11-13  Tristan Gingold  <gingold@adacore.com>
 362
 363         * configure: Regenerate.
 364
 365 2015-11-11  Alan Modra  <amodra@gmail.com>
 366             Peter Bergner <bergner@vnet.ibm.com>
 367
 368         * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
 369         Add PPC_OPCODE_VSX3 to the vsx entry.
 370         (powerpc_init_dialect): Set default dialect to power9.
 371         * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
 372         insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
 373         extract_l1 insert_xtq6, extract_xtq6): New static functions.
 374         (insert_esync): Test for illegal L operand value.
 375         (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
 376         XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
 377         XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
 378         XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
 379         PPCVSX3): New defines.
 380         (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
 381         fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
 382         <mcrxr>: Use XBFRARB_MASK.
 383         <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
 384         bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
 385         cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
 386         cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
 387         lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
 388         lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
 389         modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
 390         rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
 391         stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
 392         subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
 393         vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
 394         vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
 395         vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
 396         vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
 397         vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
 398         vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
 399         vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
 400         xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
 401         xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
 402         xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
 403         xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
 404         xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
 405         xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
 406         xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
 407         xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
 408         xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
 409         xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
 410         xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
 411         xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
 412         xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
 413         <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
 414         <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
 415
 416 2015-11-02  Nick Clifton  <nickc@redhat.com>
 417
 418         * rx-decode.opc (rx_decode_opcode): Decode extra NOP
 419         instructions.
 420         * rx-decode.c: Regenerate.
 421
 422 2015-11-02  Nick Clifton  <nickc@redhat.com>
 423
 424         * rx-decode.opc (rx_disp): If the displacement is zero, set the
 425         type to RX_Operand_Zero_Indirect.
 426         * rx-decode.c: Regenerate.
 427         * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
 428
 429 2015-10-28  Yao Qi  <yao.qi@linaro.org>
 430
 431         * aarch64-dis.c (aarch64_decode_insn): Add one argument
 432         noaliases_p.  Update comments.  Pass noaliases_p rather than
 433         no_aliases to aarch64_opcode_decode.
 434         (print_insn_aarch64_word): Pass no_aliases to
 435         aarch64_decode_insn.
 436
 437 2015-10-27  Vinay  <Vinay.G@kpit.com>
 438
 439         PR binutils/19159
 440         * rl78-decode.opc (MOV): Added offset to DE register in index
 441         addressing mode.
 442         * rl78-decode.c: Regenerate.
 443
 444 2015-10-27  Vinay Kumar  <vinay.g@kpit.com>
 445
 446         PR binutils/19158
 447         * rl78-decode.opc: Add 's' print operator to instructions that
 448         access system registers.
 449         * rl78-decode.c: Regenerate.
 450         * rl78-dis.c (print_insn_rl78_common): Decode all system
 451         registers.
 452
 453 2015-10-27  Vinay Kumar  <vinay.g@kpit.com>
 454
 455         PR binutils/19157
 456         * rl78-decode.opc: Add 'a' print operator to mov instructions
 457         using stack pointer plus index addressing.
 458         * rl78-decode.c: Regenerate.
 459
 460 2015-10-14  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 461
 462         * s390-opc.c: Fix comment.
 463         * s390-opc.txt: Change instruction type for troo, trot, trto, and
 464         trtt to RRF_U0RER since the second parameter does not need to be a
 465         register pair.
 466
 467 2015-10-08  Nick Clifton  <nickc@redhat.com>
 468
 469         * arc-dis.c (print_insn_arc): Initiallise insn array.
 470
 471 2015-10-07  Yao Qi  <yao.qi@linaro.org>
 472
 473         * aarch64-dis.c (aarch64_ext_sysins_op): Access field
 474         'name' rather than 'template'.
 475         * aarch64-opc.c (aarch64_print_operand): Likewise.
 476
 477 2015-10-07  Claudiu Zissulescu <claziss@synopsys.com>
 478
 479         * arc-dis.c: Revamped file for ARC support
 480         * arc-dis.h: Likewise.
 481         * arc-ext.c: Likewise.
 482         * arc-ext.h: Likewise.
 483         * arc-opc.c: Likewise.
 484         * arc-fxi.h: New file.
 485         * arc-regs.h: Likewise.
 486         * arc-tbl.h: Likewise.
 487
 488 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 489
 490         * aarch64-dis.c (disas_aarch64_insn): Remove static.  Change
 491         argument insn type to aarch64_insn.  Rename to ...
 492         (aarch64_decode_insn): ... it.
 493         (print_insn_aarch64_word): Caller updated.
 494
 495 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 496
 497         * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
 498         (print_insn_aarch64_word): Caller updated.
 499
 500 2015-09-29  Dominik Vogt  <vogt@linux.vnet.ibm.com>
 501
 502         * s390-mkopc.c (main): Parse htm and vx flag.
 503         * s390-opc.txt: Mark instructions from the hardware transactional
 504         memory and vector facilities with the "htm"/"vx" flag.
 505
 506 2015-09-28  Nick Clifton  <nickc@redhat.com>
 507
 508         * po/de.po: Updated German translation.
 509
 510 2015-09-28  Tom Rix  <tom@bumblecow.com>
 511
 512         * ppc-opc.c (PPC500): Mark some opcodes as invalid
 513
 514 2015-09-23  Nick Clifton  <nickc@redhat.com>
 515
 516         * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
 517         function.
 518         * tic30-dis.c (print_branch): Likewise.
 519         * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
 520         value before left shifting.
 521         * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
 522         * hppa-dis.c (print_insn_hppa): Likewise.
 523         * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
 524         array.
 525         * msp430-dis.c (msp430_singleoperand): Likewise.
 526         (msp430_doubleoperand): Likewise.
 527         (print_insn_msp430): Likewise.
 528         * nds32-asm.c (parse_operand): Likewise.
 529         * sh-opc.h (MASK): Likewise.
 530         * v850-dis.c (get_operand_value): Likewise.
 531
 532 2015-09-22  Nick Clifton  <nickc@redhat.com>
 533
 534         * rx-decode.opc (bwl): Use RX_Bad_Size.
 535         (sbwl): Likewise.
 536         (ubwl): Likewise.  Rename to ubw.
 537         (uBWL): Rename to uBW.
 538         Replace all references to uBWL with uBW.
 539         * rx-decode.c: Regenerate.
 540         * rx-dis.c (size_names): Add entry for RX_Bad_Size.
 541         (opsize_names): Likewise.
 542         (print_insn_rx): Detect and report RX_Bad_Size.
 543
 544 2015-09-22  Anton Blanchard  <anton@samba.org>
 545
 546         * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
 547
 548 2015-08-25  Jose E. Marchesi  <jose.marchesi@oracle.com>
 549
 550         * sparc-dis.c (print_insn_sparc): Handle the privileged register
 551         %pmcdper.
 552
 553 2015-08-24  Jan Stancek  <jstancek@redhat.com>
 554
 555         * i386-dis.c (print_insn): Fix decoding of three byte operands.
 556
 557 2015-08-21  Alexander Fomin  <alexander.fomin@intel.com>
 558
 559         PR binutils/18257
 560         * i386-dis.c: Use MOD_TABLE for most of mask instructions.
 561         (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
 562         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 563         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 564         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 565         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 566         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 567         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 568         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 569         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 570         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 571         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 572         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 573         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 574         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 575         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 576         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 577         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 578         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 579         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 580         MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
 581         MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
 582         MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
 583         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 584         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 585         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 586         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 587         MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 588         MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 589         MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 590         MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
 591         (vex_w_table): Replace terminals with MOD_TABLE entries for
 592         most of mask instructions.
 593
 594 2015-08-17  Alan Modra  <amodra@gmail.com>
 595
 596         * cgen.sh: Trim trailing space from cgen output.
 597         * ia64-gen.c (print_dependency_table): Don't generate trailing space.
 598         (print_dis_table): Likewise.
 599         * opc2c.c (dump_lines): Likewise.
 600         (orig_filename): Warning fix.
 601         * ia64-asmtab.c: Regenerate.
 602
 603 2015-08-13  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 604
 605         * arm-dis.c (print_insn_arm): Disassembling for all targets V6
 606         and higher with ARM instruction set will now mark the 26-bit
 607         versions of teq,tst,cmn and cmp as UNPREDICTABLE.
 608         (arm_opcodes): Fix for unpredictable nop being recognized as a
 609         teq.
 610
 611 2015-08-12  Simon Dardis  <simon.dardis@imgtec.com>
 612
 613         * micromips-opc.c (micromips_opcodes): Re-order table so that move
 614         based on 'or' is first.
 615         * mips-opc.c (mips_builtin_opcodes): Ditto.
 616
 617 2015-08-11  Nick Clifton  <nickc@redhat.com>
 618
 619         PR 18800
 620         * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
 621         instruction.
 622
 623 2015-08-10  Robert Suchanek  <robert.suchanek@imgtec.com>
 624
 625         * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
 626
 627 2015-08-07  Amit Pawar <Amit.Pawar@amd.com>
 628
 629         * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
 630         * i386-init.h: Regenerated.
 631
 632 2015-07-30  H.J. Lu  <hongjiu.lu@intel.com>
 633
 634         PR binutils/13571
 635         * i386-dis.c (MOD_0FC3): New.
 636         (PREFIX_0FC3): Renamed to ...
 637         (PREFIX_MOD_0_0FC3): This.
 638         (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
 639         (prefix_table): Replace Ma with Ev on movntiS.
 640         (mod_table): Add MOD_0FC3.
 641
 642 2015-07-27  H.J. Lu  <hongjiu.lu@intel.com>
 643
 644         * configure: Regenerated.
 645
 646 2015-07-23  Alan Modra  <amodra@gmail.com>
 647
 648         PR 18708
 649         * i386-dis.c (get64): Avoid signed integer overflow.
 650
 651 2015-07-22  Alexander Fomin  <alexander.fomin@intel.com>
 652
 653         PR binutils/18631
 654         * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
 655         "EXEvexHalfBcstXmmq" for the second operand.
 656         (EVEX_W_0F79_P_2): Likewise.
 657         (EVEX_W_0F7A_P_2): Likewise.
 658         (EVEX_W_0F7B_P_2): Likewise.
 659
 660 2015-07-16  Alessandro Marzocchi  <alessandro.marzocchi@gmail.com>
 661
 662         * arm-dis.c (print_insn_coprocessor): Added support for quarter
 663         float bitfield format.
 664         (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
 665         quarter float bitfield format.
 666
 667 2015-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 668
 669         * configure: Regenerated.
 670
 671 2015-07-03  Alan Modra  <amodra@gmail.com>
 672
 673         * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
 674         * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries.  Add
 675         PPC_OPCODE_7450 to 7450 entry.  Add PPC_OPCODE_750 to 750cl entry.
 676
 677 2015-07-01  Sandra Loosemore  <sandra@codesourcery.com>
 678             Cesar Philippidis  <cesar@codesourcery.com>
 679
 680         * nios2-dis.c (nios2_extract_opcode): New.
 681         (nios2_disassembler_state): New.
 682         (nios2_find_opcode_hash): Use mach parameter to select correct
 683         disassembler state.
 684         (nios2_print_insn_arg): Extend to support new R2 argument letters
 685         and formats.
 686         (print_insn_nios2): Check for 16-bit instruction at end of memory.
 687         * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
 688         (NIOS2_NUM_OPCODES): Rename to...
 689         (NIOS2_NUM_R1_OPCODES): This.
 690         (nios2_r2_opcodes): New.
 691         (NIOS2_NUM_R2_OPCODES): New.
 692         (nios2_num_r2_opcodes): New.
 693         (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
 694         (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
 695         (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
 696         (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
 697         (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
 698
 699 2015-06-30  Amit Pawar  <Amit.Pawar@amd.com>
 700
 701         * i386-dis.c (OP_Mwaitx): New.
 702         (rm_table): Add monitorx/mwaitx.
 703         * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
 704         and CPU_ZNVER1_FLAGS.  Add CPU_MWAITX_FLAGS.
 705         (operand_type_init): Add CpuMWAITX.
 706         * i386-opc.h (CpuMWAITX): New.
 707         (i386_cpu_flags): Add cpumwaitx.
 708         * i386-opc.tbl: Add monitorx and mwaitx.
 709         * i386-init.h: Regenerated.
 710         * i386-tbl.h: Likewise.
 711
 712 2015-06-22  Peter Bergner  <bergner@vnet.ibm.com>
 713
 714         * ppc-opc.c (insert_ls): Test for invalid LS operands.
 715         (insert_esync): New function.
 716         (LS, WC): Use insert_ls.
 717         (ESYNC): Use insert_esync.
 718
 719 2015-06-22  Nick Clifton  <nickc@redhat.com>
 720
 721         * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
 722         requested region lies beyond it.
 723         * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
 724         looking for 32-bit insns.
 725         * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
 726         data.
 727         * sh-dis.c (print_insn_sh): Likewise.
 728         * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
 729         blocks of instructions.
 730         * vax-dis.c (print_insn_vax): Check that the requested address
 731         does not clash with the stop_vma.
 732
 733 2015-06-19  Peter Bergner  <bergner@vnet.ibm.com>
 734
 735         * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
 736         * ppc-opc.c (FXM4): Add non-zero optional value.
 737         (TBR): Likewise.
 738         (SXL): Likewise.
 739         (insert_fxm): Handle new default operand value.
 740         (extract_fxm): Likewise.
 741         (insert_tbr): Likewise.
 742         (extract_tbr): Likewise.
 743
 744 2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
 745
 746         * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
 747
 748 2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 749
 750         * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
 751
 752 2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>
 753
 754         * ppc-opc.c: Add comment accidentally removed by old commit.
 755         (MTMSRD_L): Delete.
 756
 757 2015-06-04  Peter Bergner  <bergner@vnet.ibm.com>
 758
 759         * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
 760
 761 2015-06-04  Nick Clifton  <nickc@redhat.com>
 762
 763         PR 18474
 764         * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
 765
 766 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 767
 768         * arm-dis.c (arm_opcodes): Add "setpan".
 769         (thumb_opcodes): Add "setpan".
 770
 771 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 772
 773         * arm-dis.c (select_arm_features): Rework to avoid used of redefined
 774         macros.
 775
 776 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 777
 778         * aarch64-tbl.h (aarch64_feature_rdma): New.
 779         (RDMA): New.
 780         (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
 781         * aarch64-asm-2.c: Regenerate.
 782         * aarch64-dis-2.c: Regenerate.
 783         * aarch64-opc-2.c: Regenerate.
 784
 785 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 786
 787         * aarch64-tbl.h (aarch64_feature_lor): New.
 788         (LOR): New.
 789         (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
 790         "stllrb", "stllrh".
 791         * aarch64-asm-2.c: Regenerate.
 792         * aarch64-dis-2.c: Regenerate.
 793         * aarch64-opc-2.c: Regenerate.
 794
 795 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
 796
 797         * aarch64-opc.c (F_ARCHEXT): New.
 798         (aarch64_sys_regs): Add "pan".
 799         (aarch64_sys_reg_supported_p): New.
 800         (aarch64_pstatefields): Add "pan".
 801         (aarch64_pstatefield_supported_p): New.
 802
 803 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 804
 805         * i386-tbl.h: Regenerate.
 806
 807 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 808
 809         * i386-dis.c (print_insn): Swap rounding mode specifier and
 810         general purpose register in Intel mode.
 811
 812 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 813
 814         * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
 815         * i386-tbl.h: Regenerate.
 816
 817 2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
 818
 819         * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
 820         * i386-init.h: Regenerated.
 821
 822 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 823
 824         PR binutis/18386
 825         * i386-dis.c: Add comments for '@'.
 826         (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
 827         (enum x86_64_isa): New.
 828         (isa64): Likewise.
 829         (print_i386_disassembler_options): Add amd64 and intel64.
 830         (print_insn): Handle amd64 and intel64.
 831         (putop): Handle '@'.
 832         (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
 833         * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
 834         * i386-opc.h (AMD64): New.
 835         (CpuIntel64): Likewise.
 836         (i386_cpu_flags): Add cpuamd64 and cpuintel64.
 837         * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
 838         Mark direct call/jmp without Disp16|Disp32 as Intel64.
 839         * i386-init.h: Regenerated.
 840         * i386-tbl.h: Likewise.
 841
 842 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
 843
 844         * ppc-opc.c (IH) New define.
 845         (powerpc_opcodes) <wait>: Do not enable for POWER7.
 846         <tlbie>: Add RS operand for POWER7.
 847         <slbia>: Add IH operand for POWER6.
 848
 849 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 850
 851         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
 852         direct branch.
 853         (jmp): Likewise.
 854         * i386-tbl.h: Regenerated.
 855
 856 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 857
 858         * configure.ac: Support bfd_iamcu_arch.
 859         * disassemble.c (disassembler): Support bfd_iamcu_arch.
 860         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
 861         CPU_IAMCU_COMPAT_FLAGS.
 862         (cpu_flags): Add CpuIAMCU.
 863         * i386-opc.h (CpuIAMCU): New.
 864         (i386_cpu_flags): Add cpuiamcu.
 865         * configure: Regenerated.
 866         * i386-init.h: Likewise.
 867         * i386-tbl.h: Likewise.
 868
 869 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
 870
 871         PR binutis/18386
 872         * i386-dis.c (X86_64_E8): New.
 873         (X86_64_E9): Likewise.
 874         Update comments on 'T', 'U', 'V'.  Add comments for '^'.
 875         (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
 876         (x86_64_table): Add X86_64_E8 and X86_64_E9.
 877         (mod_table): Replace {T|} with ^ on Jcall/Jmp.
 878         (putop): Handle '^'.
 879         (OP_J): Ignore the operand size prefix in 64-bit.  Don't check
 880         REX_W.
 881
 882 2015-04-30  DJ Delorie  <dj@redhat.com>
 883
 884         * disassemble.c (disassembler): Choose suitable disassembler based
 885         on E_ABI.
 886         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
 887         it to decode mul/div insns.
 888         * rl78-decode.c: Regenerate.
 889         * rl78-dis.c (print_insn_rl78): Rename to...
 890         (print_insn_rl78_common): ...this, take ISA parameter.
 891         (print_insn_rl78): New.
 892         (print_insn_rl78_g10): New.
 893         (print_insn_rl78_g13): New.
 894         (print_insn_rl78_g14): New.
 895         (rl78_get_disassembler): New.
 896
 897 2015-04-29  Nick Clifton  <nickc@redhat.com>
 898
 899         * po/fr.po: Updated French translation.
 900
 901 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
 902
 903         * ppc-opc.c (DCBT_EO): New define.
 904         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
 905         <lharx>: Likewise.
 906         <stbcx.>: Likewise.
 907         <sthcx.>: Likewise.
 908         <waitrsv>: Do not enable for POWER7 and later.
 909         <waitimpl>: Likewise.
 910         <dcbt>: Default to the two operand form of the instruction for all
 911         "old" cpus.  For "new" cpus, use the operand ordering that matches
 912         whether the cpu is server or embedded.
 913         <dcbtst>: Likewise.
 914
 915 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 916
 917         * s390-opc.c: New instruction type VV0UU2.
 918         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
 919         and WFC.
 920
 921 2015-04-23  Jan Beulich  <jbeulich@suse.com>
 922
 923         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
 924         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
 925         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
 926         (vfpclasspd, vfpclassps): Add %XZ.
 927
 928 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 929
 930         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
 931         (PREFIX_UD_REPZ): Likewise.
 932         (PREFIX_UD_REPNZ): Likewise.
 933         (PREFIX_UD_DATA): Likewise.
 934         (PREFIX_UD_ADDR): Likewise.
 935         (PREFIX_UD_LOCK): Likewise.
 936
 937 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 938
 939         * i386-dis.c (prefix_requirement): Removed.
 940         (print_insn): Don't set prefix_requirement.  Check
 941         dp->prefix_requirement instead of prefix_requirement.
 942
 943 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 944
 945         PR binutils/17898
 946         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
 947         (PREFIX_MOD_0_0FC7_REG_6): This.
 948         (PREFIX_MOD_3_0FC7_REG_6): New.
 949         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
 950         (prefix_table): Replace PREFIX_0FC7_REG_6 with
 951         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
 952         PREFIX_MOD_3_0FC7_REG_7.
 953         (mod_table): Replace PREFIX_0FC7_REG_6 with
 954         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
 955         PREFIX_MOD_3_0FC7_REG_7.
 956
 957 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 958
 959         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
 960         (PREFIX_MANDATORY_REPNZ): Likewise.
 961         (PREFIX_MANDATORY_DATA): Likewise.
 962         (PREFIX_MANDATORY_ADDR): Likewise.
 963         (PREFIX_MANDATORY_LOCK): Likewise.
 964         (PREFIX_MANDATORY): Likewise.
 965         (PREFIX_UD_SHIFT): Set to 8
 966         (PREFIX_UD_REPZ): Updated.
 967         (PREFIX_UD_REPNZ): Likewise.
 968         (PREFIX_UD_DATA): Likewise.
 969         (PREFIX_UD_ADDR): Likewise.
 970         (PREFIX_UD_LOCK): Likewise.
 971         (PREFIX_IGNORED_SHIFT): New.
 972         (PREFIX_IGNORED_REPZ): Likewise.
 973         (PREFIX_IGNORED_REPNZ): Likewise.
 974         (PREFIX_IGNORED_DATA): Likewise.
 975         (PREFIX_IGNORED_ADDR): Likewise.
 976         (PREFIX_IGNORED_LOCK): Likewise.
 977         (PREFIX_OPCODE): Likewise.
 978         (PREFIX_IGNORED): Likewise.
 979         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 980         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 981         (three_byte_table): Likewise.
 982         (mod_table): Likewise.
 983         (mandatory_prefix): Renamed to ...
 984         (prefix_requirement): This.
 985         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 986         Update PREFIX_90 entry.
 987         (get_valid_dis386): Check prefix_requirement to see if a prefix
 988         should be ignored.
 989         (print_insn): Replace mandatory_prefix with prefix_requirement.
 990
 991 2015-04-15  Renlin Li  <renlin.li@arm.com>
 992
 993         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
 994         use it for ssat and ssat16.
 995         (print_insn_thumb32): Add handle case for 'D' control code.
 996
 997 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
 998             H.J. Lu  <hongjiu.lu@intel.com>
 999
1000         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
1001         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
1002         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
1003         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
1004         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
1005         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
1006         Fill prefix_requirement field.
1007         (struct dis386): Add prefix_requirement field.
1008         (dis386): Fill prefix_requirement field.
1009         (dis386_twobyte): Ditto.
1010         (twobyte_has_mandatory_prefix_: Remove.
1011         (reg_table): Fill prefix_requirement field.
1012         (prefix_table): Ditto.
1013         (x86_64_table): Ditto.
1014         (three_byte_table): Ditto.
1015         (xop_table): Ditto.
1016         (vex_table): Ditto.
1017         (vex_len_table): Ditto.
1018         (vex_w_table): Ditto.
1019         (mod_table): Ditto.
1020         (bad_opcode): Ditto.
1021         (print_insn): Use prefix_requirement.
1022         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
1023         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
1024         (float_reg): Ditto.
1025
1026 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
1027
1028         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
1029
1030 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
1031
1032         * Makefile.in: Regenerated.
1033
1034 2015-03-25  Anton Blanchard  <anton@samba.org>
1035
1036         * ppc-dis.c (disassemble_init_powerpc): Only initialise
1037         powerpc_opcd_indices and vle_opcd_indices once.
1038
1039 2015-03-25  Anton Blanchard  <anton@samba.org>
1040
1041         * ppc-opc.c (powerpc_opcodes): Add slbfee.
1042
1043 2015-03-24  Terry Guo  <terry.guo@arm.com>
1044
1045         * arm-dis.c (opcode32): Updated to use new arm feature struct.
1046         (opcode16): Likewise.
1047         (coprocessor_opcodes): Replace bit with feature struct.
1048         (neon_opcodes): Likewise.
1049         (arm_opcodes): Likewise.
1050         (thumb_opcodes): Likewise.
1051         (thumb32_opcodes): Likewise.
1052         (print_insn_coprocessor): Likewise.
1053         (print_insn_arm): Likewise.
1054         (select_arm_features): Follow new feature struct.
1055
1056 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
1057
1058         * i386-dis.c (rm_table): Add clzero.
1059         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
1060         Add CPU_CLZERO_FLAGS.
1061         (cpu_flags): Add CpuCLZERO.
1062         * i386-opc.h: Add CpuCLZERO.
1063         * i386-opc.tbl: Add clzero.
1064         * i386-init.h: Re-generated.
1065         * i386-tbl.h: Re-generated.
1066
1067 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
1068
1069         * mips-opc.c (decode_mips_operand): Fix constraint issues
1070         with u and y operands.
1071
1072 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
1073
1074         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
1075
1076 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1077
1078         * s390-opc.c: Add new IBM z13 instructions.
1079         * s390-opc.txt: Likewise.
1080
1081 2015-03-10  Renlin Li  <renlin.li@arm.com>
1082
1083         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
1084         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
1085         related alias.
1086         * aarch64-asm-2.c: Regenerate.
1087         * aarch64-dis-2.c: Likewise.
1088         * aarch64-opc-2.c: Likewise.
1089
1090 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
1091
1092         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
1093
1094 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
1095
1096         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
1097         arch_sh_up.
1098         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
1099         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
1100
1101 2015-02-23  Vinay  <Vinay.G@kpit.com>
1102
1103         * rl78-decode.opc (MOV): Added space between two operands for
1104         'mov' instruction in index addressing mode.
1105         * rl78-decode.c: Regenerate.
1106
1107 2015-02-19  Pedro Alves  <palves@redhat.com>
1108
1109         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
1110
1111 2015-02-10  Pedro Alves  <palves@redhat.com>
1112             Tom Tromey  <tromey@redhat.com>
1113
1114         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
1115         microblaze_and, microblaze_xor.
1116         * microblaze-opc.h (opcodes): Adjust.
1117
1118 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
1119
1120         * Makefile.am: Add FT32 files.
1121         * configure.ac: Handle FT32.
1122         * disassemble.c (disassembler): Call print_insn_ft32.
1123         * ft32-dis.c: New file.
1124         * ft32-opc.c: New file.
1125         * Makefile.in: Regenerate.
1126         * configure: Regenerate.
1127         * po/POTFILES.in: Regenerate.
1128
1129 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
1130
1131         * nds32-asm.c (keyword_sr): Add new system registers.
1132
1133 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1134
1135         * s390-dis.c (s390_extract_operand): Support vector register
1136         operands.
1137         (s390_print_insn_with_opcode): Support new operands types and add
1138         new handling of optional operands.
1139         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
1140         and include opcode/s390.h instead.
1141         (struct op_struct): New field `flags'.
1142         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
1143         (dumpTable): Dump flags.
1144         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
1145         string.
1146         * s390-opc.c: Add new operands types, instruction formats, and
1147         instruction masks.
1148         (s390_opformats): Add new formats for .insn.
1149         * s390-opc.txt: Add new instructions.
1150
1151 2015-01-01  Alan Modra  <amodra@gmail.com>
1152
1153         Update year range in copyright notice of all files.
1154
1155 For older changes see ChangeLog-2014
1156 \f
1157 Copyright (C) 2015 Free Software Foundation, Inc.
1158
1159 Copying and distribution of this file, with or without modification,
1160 are permitted in any medium without royalty provided the copyright
1161 notice and this notice are preserved.
1162
1163 Local Variables:
1164 mode: change-log
1165 left-margin: 8
1166 fill-column: 74
1167 version-control: never
1168 End: