opcodes/ChangeLog

   1 2014-11-17  Ilya Tocar  <ilya.tocar@intel.com>
   2
   3         * i386-dis-evex.c (evex_table): Add vpmadd52luq, vpmadd52huq.
   4         * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F38B4,
   5         PREFIX_EVEX_0F38B5.
   6         * i386-gen.c (cpu_flag_init): Add CPU_AVX512IFMA_FLAGS.
   7         (cpu_flags): Add CpuAVX512IFMA.
   8         * i386-opc.h (enum): Add CpuAVX512IFMA.
   9         (i386_cpu_flags): Add cpuavx512ifma.
  10         * i386-opc.tbl: Add vpmadd52huq, vpmadd52luq.
  11         * i386-init.h: Regenerated.
  12         * i386-tbl.h: Likewise.
  13
  14 2014-11-17  Ilya Tocar  <ilya.tocar@intel.com>
  15
  16         * i386-dis.c (PREFIX enum): Add PREFIX_RM_0_0FAE_REG_7.
  17         (prefix_table): Add pcommit.
  18         * i386-gen.c (cpu_flag_init): Add CPU_PCOMMIT_FLAGS.
  19         (cpu_flags): Add CpuPCOMMIT.
  20         * i386-opc.h (enum): Add CpuPCOMMIT.
  21         (i386_cpu_flags): Add cpupcommit.
  22         * i386-opc.tbl: Add pcommit.
  23         * i386-init.h: Regenerated.
  24         * i386-tbl.h: Likewise.
  25
  26 2014-11-17  Ilya Tocar  <ilya.tocar@intel.com>
  27
  28         * i386-dis.c (PREFIX enum): Add PREFIX_0FAE_REG_6.
  29         (prefix_table): Add clwb.
  30         * i386-gen.c (cpu_flag_init): Add CPU_CLWB_FLAGS.
  31         (cpu_flags): Add CpuCLWB.
  32         * i386-opc.h (enum): Add CpuCLWB.
  33         (i386_cpu_flags): Add cpuclwb.
  34         * i386-opc.tbl: Add clwb.
  35         * i386-init.h: Regenerated.
  36         * i386-tbl.h: Likewise.
  37
  38 2014-11-06  Sandra Loosemore  <sandra@codesourcery.com>
  39
  40         * nios2-dis.c (nios2_find_opcode_hash): Add mach parameter.
  41         (nios2_disassemble): Adjust call to nios2_find_opcode_hash.
  42
  43 2014-11-03  Nick Clifton  <nickc@redhat.com>
  44
  45         * po/fi.po: Updated Finnish translation.
  46
  47 2014-10-31  Andrew Pinski  <apinski@cavium.com>
  48             Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>
  49
  50         * mips-dis.c (mips_arch_choices): Add octeon3.
  51         * mips-opc.c (IOCT): Include INSN_OCTEON3.
  52         (IOCT2): Likewise.
  53         (IOCT3): New define.
  54         (IVIRT): New define.
  55         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
  56         tlbinv, tlbinvf, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp, tlti
  57         IVIRT instructions.
  58         Extend mtm0, mtm1, mtm2, mtp0, mtp1, mtp2 instructions to take another
  59         operand for IOCT3.
  60
  61 2014-10-29  Nick Clifton  <nickc@redhat.com>
  62
  63         * po/de.po: Updated German translation.
  64
  65 2014-10-23  Sandra Loosemore  <sandra@codesourcery.com>
  66
  67         * nios2-opc.c (nios2_builtin_regs): Add regtype field initializers.
  68         (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.  Use new
  69         MATCH_R1_<insn> and MASK_R1_<insn> macros in initializers.  Add
  70         size and format initializers.  Merge 'b' arguments into 'j'.
  71         (NIOS2_NUM_OPCODES): Adjust definition.
  72         (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
  73         (nios2_opcodes): Adjust.
  74         (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
  75         * nios2-dis.c (INSNLEN): Update comment.
  76         (nios2_hash_init, nios2_hash): Delete.
  77         (OPCODE_HASH_SIZE): New.
  78         (nios2_r1_extract_opcode): New.
  79         (nios2_disassembler_state): New.
  80         (nios2_r1_disassembler_state): New.
  81         (nios2_init_opcode_hash): Add state parameter.  Adjust to use it.
  82         (nios2_find_opcode_hash): Use state object.
  83         (bad_opcode): New.
  84         (nios2_print_insn_arg): Add op parameter.  Use it to access
  85         format.  Remove 'b' case.
  86         (nios2_disassemble): Remove special case for nop.  Remove
  87         hard-coded instruction size.
  88
  89 2014-10-21  Jan Beulich  <jbeulich@suse.com>
  90
  91         * ppc-opc.c (powerpc_opcodes): Enable msgclr and msgsnd on Power8.
  92
  93 2014-10-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
  94
  95         * sparc-opc.c (sparc-opcodes): Fix several misplaced hwcap
  96         entries.
  97         Annotate several instructions with the HWCAP2_VIS3B hwcap.
  98
  99 2014-10-15  Tristan Gingold  <gingold@adacore.com>
 100
 101         * configure: Regenerate.
 102
 103 2014-10-09  Jose E. Marchesi  &lt;jose.marchesi@oracle.com&gt;
 104
 105         * sparc-opc.c (sparc-opcodes): Remove instructions `chkpt',
 106         `commit', `random', `wr r,r,%cps', `wr r,i,%cps' and `rd %cps,r'.
 107         Annotate table with HWCAP2 bits.
 108         Add instructions xmontmul, xmontsqr, xmpmul.
 109         (sparc-opcodes): Add the `mwait',  `wr r,r,%mwait', `wr
 110         r,i,%mwait' and `rd %mwait,r' instructions.
 111         Add rd/wr instructions for accessing the %mcdper ancillary state
 112         register.
 113         (sparc-opcodes): Add sparc5/vis4.0 instructions:
 114         subxc, subxccc, fpadd8, fpadds8, fpaddus8, fpaddus16, fpcmple8,
 115         fpcmpgt8, fpcmpule16, fpcmpugt16, fpcmpule32, fpcmpugt32, fpmax8,
 116         fpmax16, fpmax32, fpmaxu8, fpmaxu16, fpmaxu32, fpmin8, fpmin16,
 117         fpmin32, fpminu8, fpminu16, fpminu32, fpsub8, fpsubs8, fpsubus8,
 118         fpsubus16, and faligndatai.
 119         * sparc-dis.c (v9a_asr_reg_names): Add the %mwait (%asr28)
 120         ancillary state register to the table.
 121         (print_insn_sparc): Handle the %mcdper ancillary state register.
 122         (print_insn_sparc): Handle new operand type '}'.
 123
 124 2014-09-22  H.J. Lu  <hongjiu.lu@intel.com>
 125
 126         * i386-dis.c (MOD_0F20): Removed.
 127         (MOD_0F21): Likewise.
 128         (MOD_0F22): Likewise.
 129         (MOD_0F23): Likewise.
 130         (dis386_twobyte): Replace MOD_0F20, MOD_0F21, MOD_0F22 and
 131         MOD_0F23 with "movZ".
 132         (mod_table): Remove MOD_0F20, MOD_0F21, MOD_0F22 and MOD_0F23.
 133         (OP_R): Check mod/rm byte and call OP_E_register.
 134
 135 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 136
 137         * nds32-asm.c (nds32_opcodes, operand_fields, keyword_im5_i,
 138         keyword_im5_m, keyword_accumulator, keyword_aridx, keyword_aridx2,
 139         keyword_aridxi): Add audio ISA extension.
 140         (keyword_gpr, keyword_usr, keyword_sr, keyword_cp, keyword_cpr,
 141         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm, keyword_dpref_st,
 142         keyword_cctl_lv, keyword_standby_st, keyword_msync_st): Adjust scrope
 143         for nds32-dis.c using.
 144         (build_opcode_syntax): Remove dead code.
 145         (parse_re, parse_a30b20, parse_rt21, parse_rte_start, parse_rte_end,
 146         parse_rte69_start, parse_rte69_end, parse_im5_ip, parse_im5_mr,
 147         parse_im6_ip, parse_im6_iq, parse_im6_mr, parse_im6_ms): Add audio ISA
 148         operand parser.
 149         * nds32-asm.h: Declare.
 150         * nds32-dis.c: Use array nds32_opcodes to disassemble instead of
 151         decoding by switch.
 152
 153 2014-09-15  Andrew Bennett  <andrew.bennett@imgtec.com>
 154             Matthew Fortune  <matthew.fortune@imgtec.com>
 155
 156         * mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
 157         mips64r6.
 158         (parse_mips_dis_option): Allow MSA and virtualization support for
 159         mips64r6.
 160         (mips_print_arg_state): Add fields dest_regno and seen_dest.
 161         (mips_seen_register): New function.
 162         (print_insn_arg): Refactored code to use mips_seen_register
 163         function.  Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
 164         OP_NON_ZERO_REG.  Changed OP_REPEAT_DEST_REG case to print out
 165         the register rather than aborting.
 166         (print_insn_args): Add length argument.  Add code to correctly
 167         calculate the instruction address for pc relative instructions.
 168         (validate_insn_args): New static function.
 169         (print_insn_mips): Prevent jalx disassembling for r6.  Use
 170         validate_insn_args.
 171         (print_insn_micromips): Use validate_insn_args.
 172         all the arguments are valid.
 173         * mips-formats.h (PREV_CHECK): New define.
 174         * mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
 175         -t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
 176         (RD_pc): New define.
 177         (FS): New define.
 178         (I37): New define.
 179         (I69): New define.
 180         (mips_builtin_opcodes): Add MIPS R6 instructions.  Exclude recoded
 181         MIPS R6 instructions from MIPS R2 instructions.
 182
 183 2014-09-10  H.J. Lu  <hongjiu.lu@intel.com>
 184
 185         * i386-dis.c (dis386): Replace "P" with "%LP" for iret and sysret.
 186         (putop): Handle "%LP".
 187
 188 2014-09-03  Jiong Wang  <jiong.wang@arm.com>
 189
 190         * aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
 191         * aarch64-dis-2.c: Update auto-generated file.
 192
 193 2014-09-03  Jiong Wang  <jiong.wang@arm.com>
 194
 195         * aarch64-tbl.h (QL_R4NIL): New qualifiers.
 196         (aarch64_feature_lse): New feature added.
 197         (LSE): New Added.
 198         (aarch64_opcode_table): New LSE instructions added.  Improve
 199         descriptions for ldarb/ldarh/ldar.
 200         (aarch64_opcode_table): Describe PAIRREG.
 201         * aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
 202         * aarch64-opc.c (fields): Add entry for F_LSE_SZ.
 203         (aarch64_print_operand): Recognize PAIRREG.
 204         (operand_general_constraint_met_p): Check reg pair constraints for CASP
 205         instructions.
 206         * aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
 207         (do_special_decoding): Recognize F_LSE_SZ.
 208         * aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.
 209
 210 2014-08-26  Maciej W. Rozycki  <macro@codesourcery.com>
 211
 212         * micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
 213         (micromips_opcodes): Use "+J" in place of "B" for "hypcall",
 214         "sdbbp", "syscall" and "wait".
 215
 216 2014-08-21  Nathan Sidwell  <nathan@codesourcery.com>
 217             Maciej W. Rozycki  <macro@codesourcery.com>
 218
 219         * arm-dis.c (print_arm_address): Negate the GPR-relative offset
 220         returned if the U bit is set.
 221
 222 2014-08-21  Maciej W. Rozycki  <macro@codesourcery.com>
 223
 224         * micromips-opc.c (micromips_opcodes): Remove #ifdef-ed out
 225         48-bit "li" encoding.
 226
 227 2014-08-19  Andreas Arnez  <arnez@linux.vnet.ibm.com>
 228
 229         * s390-dis.c (s390_insn_length, s390_insn_matches_opcode)
 230         (s390_print_insn_with_opcode, opcode_mask_more_specific): New
 231         static functions, code was moved from...
 232         (print_insn_s390): ...here.
 233         (s390_extract_operand): Adjust comment.  Change type of first
 234         parameter from 'unsigned char *' to 'const bfd_byte *'.
 235         (union operand_value): New.
 236         (s390_extract_operand): Change return type to union operand_value.
 237         Also avoid integer overflow in sign-extension.
 238         (s390_print_insn_with_opcode): Adjust to changed return value from
 239         s390_extract_operand().  Change "%i" printf format to "%u" for
 240         unsigned values.
 241         (init_disasm): Simplify initialization of opc_index[].  This also
 242         fixes an access after the last element of s390_opcodes[].
 243         (print_insn_s390): Simplify the opcode search loop.
 244         Check architecture mask against all searched opcodes, not just the
 245         first matching one.
 246         (s390_print_insn_with_opcode): Drop function pointer dereferences
 247         without effect.
 248         (print_insn_s390): Likewise.
 249         (s390_insn_length): Simplify formula for return value.
 250         (s390_print_insn_with_opcode): Avoid special handling for the
 251         separator before the first operand.  Use new local variable
 252         'flags' in place of 'operand->flags'.
 253
 254 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 255
 256         * bfin-dis.c (struct private): Change int's to bfd_boolean's.
 257         (decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
 258         decode_dagMODik_0, decode_LDIMMhalf_0, decode_linkage_0):
 259         Change assignment of 1 to priv->comment to TRUE.
 260         (print_insn_bfin): Change legal to a bfd_boolean.  Change
 261         assignment of 0/1 with priv comment and parallel and legal
 262         to FALSE/TRUE.
 263
 264 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 265
 266         * bfin-dis.c (OUT): Define.
 267         (decode_CC2stat_0): Declare new op_names array.
 268         Replace multiple if statements with a single one.
 269
 270 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 271
 272         * bfin-dis.c (struct private): Add iw0.
 273         (_print_insn_bfin): Assign iw0 to priv.iw0.
 274         (print_insn_bfin): Drop ifetch and use priv.iw0.
 275
 276 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 277
 278         * bfin-dis.c (comment, parallel): Move from global scope ...
 279         (struct private): ... to this new struct.
 280         (decode_ProgCtrl_0, decode_CaCTRL_0, decode_PushPopReg_0,
 281         decode_PushPopMultiple_0, decode_ccMV_0, decode_CCflag_0,
 282         decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
 283         decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
 284         decode_dagMODik_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
 285         decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
 286         decode_pseudoOChar_0, decode_pseudodbg_assert_0, _print_insn_bfin,
 287         print_insn_bfin): Declare private struct.  Use priv's comment and
 288         parallel members.
 289
 290 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 291
 292         * bfin-dis.c (ifetch): Do not align pc to 2 bytes.
 293         (_print_insn_bfin): Add check for unaligned pc.
 294
 295 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 296
 297         * bfin-dis.c (ifetch): New function.
 298         (_print_insn_bfin, print_insn_bfin): Call new ifetch and return
 299         -1 when it errors.
 300
 301 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
 302
 303         * micromips-opc.c (COD): Rename throughout to...
 304         (CM): New define, update to use INSN_COPROC_MOVE.
 305         (LCD): Rename throughout to...
 306         (LC): New define, update to use INSN_LOAD_COPROC.
 307         * mips-opc.c: Likewise.
 308
 309 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
 310
 311         * micromips-opc.c (COD, LCD) New macros.
 312         (cfc1, ctc1): Remove FP_S attribute.
 313         (dmfc1, mfc1, mfhc1): Add LCD attribute.
 314         (dmtc1, mtc1, mthc1): Add COD attribute.
 315         * mips-opc.c (cfc1, cftc1, ctc, cttc1): Remove FP_S attribute.
 316
 317 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 318             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 319             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 320             Sergey Lega  <sergey.s.lega@intel.com>
 321             Anna Tikhonova  <anna.tikhonova@intel.com>
 322             Ilya Tocar  <ilya.tocar@intel.com>
 323             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 324             Ilya Verbin  <ilya.verbin@intel.com>
 325             Kirill Yukhin  <kirill.yukhin@intel.com>
 326             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 327
 328         * i386-dis-evex.h: Updated.
 329         * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
 330         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0F3A16,
 331         PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51,
 332         PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
 333         PREFIX_EVEX_0F3A67.
 334         (VEX_LEN enum): Add VEX_LEN_0F92_P_2, VEX_LEN_0F93_P_2,
 335         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_2_LEN_0.
 336         (VEX_W enum): Add EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 337         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, EVEX_W_0F57_P_0,
 338         EVEX_W_0F57_P_2, EVEX_W_0F78_P_2, EVEX_W_0F79_P_2, EVEX_W_0F7A_P_2,
 339         EVEX_W_0F7B_P_2, EVEX_W_0F3838_P_1, EVEX_W_0F3839_P_1,
 340         EVEX_W_0F3A16_P_2, EVEX_W_0F3A22_P_2, EVEX_W_0F3A50_P_2,
 341         EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2,
 342         EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2.
 343         (prefix_table): Add entries for new instructions.
 344         (vex_len_table): Ditto.
 345         (vex_w_table): Ditto.
 346         (OP_E_memory): Update xmmq_mode handling.
 347         * i386-gen.c (cpu_flag_init): Add CPU_AVX512DQ_FLAGS.
 348         (cpu_flags): Add CpuAVX512DQ.
 349         * i386-init.h: Regenerared.
 350         * i386-opc.h (CpuAVX512DQ): New.
 351         (i386_cpu_flags): Add cpuavx512dq.
 352         * i386-opc.tbl: Add AVX512DQ instructions.
 353         * i386-tbl.h: Regenerate.
 354
 355 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 356             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 357             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 358             Sergey Lega  <sergey.s.lega@intel.com>
 359             Anna Tikhonova  <anna.tikhonova@intel.com>
 360             Ilya Tocar  <ilya.tocar@intel.com>
 361             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 362             Ilya Verbin  <ilya.verbin@intel.com>
 363             Kirill Yukhin  <kirill.yukhin@intel.com>
 364             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 365
 366         * i386-dis-evex.h: Add new instructions (prefixes bellow).
 367         * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE.
 368         (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71.
 369         (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31,
 370         PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63,
 371         PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
 372         PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4,
 373         PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7,
 374         PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
 375         PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9,
 376         PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
 377         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4,
 378         PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA,
 379         PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
 380         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9,
 381         PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804,
 382         PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D,
 383         PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830,
 384         PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866,
 385         PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A,
 386         PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F,
 387         PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E,
 388         PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42.
 389         (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2,
 390         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 391         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2,
 392         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0,
 393         VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1,
 394         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1,
 395         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 396         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0,
 397         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0,
 398         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0,
 399         VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0.
 400         (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3,
 401         EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2,
 402         EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1,
 403         EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2,
 404         EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2,
 405         EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2,
 406         EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2.
 407         (prefix_table): Add entries for new instructions.
 408         (vex_table) : Ditto.
 409         (vex_len_table): Ditto.
 410         (vex_w_table): Ditto.
 411         (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode,
 412         mask_bd_mode handling.
 413         (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode
 414         handling.
 415         (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode
 416         handling.
 417         (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling.
 418         (OP_EX): Add dqw_swap_mode handling.
 419         (OP_VEX): Add mask_bd_mode handling.
 420         (OP_Mask): Add mask_bd_mode handling.
 421         * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS.
 422         (cpu_flags): Add CpuAVX512BW.
 423         * i386-init.h: Regenerated.
 424         * i386-opc.h (CpuAVX512BW): New.
 425         (i386_cpu_flags): Add cpuavx512bw.
 426         * i386-opc.tbl: Add AVX512BW instructions.
 427         * i386-tbl.h: Regenerate.
 428
 429 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 430             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 431             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 432             Sergey Lega  <sergey.s.lega@intel.com>
 433             Anna Tikhonova  <anna.tikhonova@intel.com>
 434             Ilya Tocar  <ilya.tocar@intel.com>
 435             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 436             Ilya Verbin  <ilya.verbin@intel.com>
 437             Kirill Yukhin  <kirill.yukhin@intel.com>
 438             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 439
 440         * i386-opc.tbl: Add AVX512VL and AVX512CD instructions.
 441         * i386-tbl.h: Regenerate.
 442
 443 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 444             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 445             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 446             Sergey Lega  <sergey.s.lega@intel.com>
 447             Anna Tikhonova  <anna.tikhonova@intel.com>
 448             Ilya Tocar  <ilya.tocar@intel.com>
 449             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 450             Ilya Verbin  <ilya.verbin@intel.com>
 451             Kirill Yukhin  <kirill.yukhin@intel.com>
 452             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 453
 454         * i386-dis.c (intel_operand_size): Support 128/256 length in
 455         vex_vsib_q_w_dq_mode.
 456         (OP_E_memory): Add ymmq_mode handling, handle new broadcast.
 457         * i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS.
 458         (cpu_flags): Add CpuAVX512VL.
 459         * i386-init.h: Regenerated.
 460         * i386-opc.h (CpuAVX512VL): New.
 461         (i386_cpu_flags): Add cpuavx512vl.
 462         (BROADCAST_1TO4, BROADCAST_1TO2): Define.
 463         * i386-opc.tbl: Add AVX512VL instructions.
 464         * i386-tbl.h: Regenerate.
 465
 466 2014-07-20  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>
 467
 468         * or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
 469         * or1k-opinst.c: Regenerate.
 470
 471 2014-07-08  Ilya Tocar  <ilya.tocar@intel.com>
 472
 473         * i386-dis-evex.h (EVEX_W_0F10_P_1_M_1): Fix vmovss.
 474         (EVEX_W_0F10_P_3_M_1): Fix vmovsd.
 475
 476 2014-07-04  Alan Modra  <amodra@gmail.com>
 477
 478         * configure.ac: Rename from configure.in.
 479         * Makefile.in: Regenerate.
 480         * config.in: Regenerate.
 481
 482 2014-07-04  Alan Modra  <amodra@gmail.com>
 483
 484         * configure.in: Include bfd/version.m4.
 485         (AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
 486         (BFD_VERSION): Delete.
 487         * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
 488         * configure: Regenerate.
 489         * Makefile.in: Regenerate.
 490
 491 2014-07-01  Barney Stratford   <barney_stratford@fastmail.fm>
 492             Senthil Kumar Selvaraj  <senthil_kumar.selvaraj@atmel.com>
 493             Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 494             Soundararajan  <Sounderarajan.D@atmel.com>
 495
 496         * avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
 497         (print_insn_avr): Do not select opcode if insn ISA is avrtiny and
 498         machine is not avrtiny.
 499
 500 2014-06-26  Philippe De Muyter <phdm@macqel.be>
 501
 502         * or1k-desc.h (spr_field_masks): Add U suffix to the end of long
 503         constants.
 504
 505 2014-06-12  Alan Modra  <amodra@gmail.com>
 506
 507         * or1k-asm.c, * or1k-desc.c, * or1k-desc.h, * or1k-dis.c,
 508         * or1k-ibld.c, * or1k-opc.c, * or1k-opc.h, * or1k-opinst.c: Regenerate.
 509
 510 2014-06-10  H.J. Lu  <hongjiu.lu@intel.com>
 511
 512         * i386-dis.c (fwait_prefix): New.
 513         (ckprefix): Set fwait_prefix.
 514         (print_insn): Properly print prefixes before fwait.
 515
 516 2014-06-07  Alan Modra  <amodra@gmail.com>
 517
 518         * ppc-opc.c (UISIGNOPT): Define and use with cmpli.
 519
 520 2014-06-05  Joel Brobecker  <brobecker@adacore.com>
 521
 522         * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
 523         bfd's development.sh.
 524         * Makefile.in, configure: Regenerate.
 525
 526 2014-06-03  Nick Clifton  <nickc@redhat.com>
 527
 528         * msp430-dis.c (msp430_doubleoperand): Use extension_word to
 529         decide when extended addressing is being used.
 530
 531 2014-06-02  Eric Botcazou  <ebotcazou@adacore.com>
 532
 533         * sparc-opc.c (cas): Disable for LEON.
 534         (casl): Likewise.
 535
 536 2014-05-20  Alan Modra  <amodra@gmail.com>
 537
 538         * m68k-dis.c: Don't include setjmp.h.
 539
 540 2014-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 541
 542         * i386-dis.c (ADDR16_PREFIX): Removed.
 543         (ADDR32_PREFIX): Likewise.
 544         (DATA16_PREFIX): Likewise.
 545         (DATA32_PREFIX): Likewise.
 546         (prefix_name): Updated.
 547         (print_insn): Simplify data and address size prefixes processing.
 548
 549 2014-05-08  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>
 550
 551         * or1k-desc.c: Regenerated.
 552         * or1k-desc.h: Likewise.
 553         * or1k-opc.c: Likewise.
 554         * or1k-opc.h: Likewise.
 555         * or1k-opinst.c: Likewise.
 556
 557 2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
 558
 559         * mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
 560         (I34): New define.
 561         (I36): New define.
 562         (I66): New define.
 563         (I68): New define.
 564         * mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
 565         mips64r5.
 566         (parse_mips_dis_option): Update MSA and virtualization support to
 567         allow mips64r3 and mips64r5.
 568
 569 2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
 570
 571         * mips-opc.c (G3): Remove I4.
 572
 573 2014-05-05  H.J. Lu  <hongjiu.lu@intel.com>
 574
 575         PR binutils/16893
 576         * i386-dis.c (twobyte_has_mandatory_prefix): New variable.
 577         (end_codep): Likewise.
 578         (mandatory_prefix): Likewise.
 579         (active_seg_prefix): Likewise.
 580         (ckprefix): Set active_seg_prefix to the active segment register
 581         prefix.
 582         (seg_prefix): Removed.
 583         (get_valid_dis386): Use the last of PREFIX_REPNZ and PREFIX_REPZ
 584         for prefix index.  Ignore the index if it is invalid and the
 585         mandatory prefix isn't required.
 586         (print_insn): Set mandatory_prefix if the PREFIX_XXX prefix is
 587         mandatory.  Don't set PREFIX_REPZ/PREFIX_REPNZ/PREFIX_LOCK bits
 588         in used_prefixes here.  Don't print unused prefixes.  Check
 589         active_seg_prefix for the active segment register prefix.
 590         Restore the DFLAG bit in sizeflag if the data size prefix is
 591         unused.  Check the unused mandatory PREFIX_XXX prefixes
 592         (append_seg): Only print the segment register which gets used.
 593         (OP_E_memory): Check active_seg_prefix for the segment register
 594         prefix.
 595         (OP_OFF): Likewise.
 596         (OP_OFF64): Likewise.
 597         (OP_DSreg): Set active_seg_prefix to PREFIX_DS if it is unset.
 598
 599 2014-05-02  H.J. Lu  <hongjiu.lu@intel.com>
 600
 601         PR binutils/16886
 602         * config.in: Regenerated.
 603         * configure: Likewise.
 604         * configure.in: Check if sigsetjmp is available.
 605         * h8500-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 606         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 607         (print_insn_h8500): Replace setjmp with OPCODES_SIGSETJMP.
 608         * i386-dis.c (dis_private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 609         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 610         (print_insn): Replace setjmp with OPCODES_SIGSETJMP.
 611         * ns32k-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 612         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 613         (print_insn_ns32k): Replace setjmp with OPCODES_SIGSETJMP.
 614         * sysdep.h (OPCODES_SIGJMP_BUF): New macro.
 615         (OPCODES_SIGSETJMP): Likewise.
 616         (OPCODES_SIGLONGJMP): Likewise.
 617         * vax-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 618         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 619         (print_insn_vax): Replace setjmp with OPCODES_SIGSETJMP.
 620         * xtensa-dis.c (dis_private): Replace jmp_buf with
 621         OPCODES_SIGJMP_BUF.
 622         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 623         (print_insn_xtensa): Replace setjmp with OPCODES_SIGSETJMP.
 624         * z8k-dis.c(instr_data_s): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 625         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 626         (print_insn_z8k): Replace setjmp with OPCODES_SIGSETJMP.
 627
 628 2014-05-01  H.J. Lu  <hongjiu.lu@intel.com>
 629
 630         PR binutils/16891
 631         * i386-dis.c (print_insn): Handle prefixes before fwait.
 632
 633 2014-04-26  Alan Modra  <amodra@gmail.com>
 634
 635         * po/POTFILES.in: Regenerate.
 636
 637 2014-04-23  Andrew Bennett  <andrew.bennett@imgtec.com>
 638
 639         * mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
 640         to allow the MIPS XPA ASE.
 641         (parse_mips_dis_option): Process the -Mxpa option.
 642         * mips-opc.c (XPA): New define.
 643         (mips_builtin_opcodes): Add MIPS XPA instructions and move the
 644         locations of the ctc0 and cfc0 instructions.
 645
 646 2014-04-22  Christian Svensson  <blue@cmd.nu>
 647
 648         * Makefile.am: Remove openrisc and or32 support.  Add support for or1k.
 649         * configure.in: Likewise.
 650         * disassemble.c: Likewise.
 651         * or1k-asm.c: New file.
 652         * or1k-desc.c: New file.
 653         * or1k-desc.h: New file.
 654         * or1k-dis.c: New file.
 655         * or1k-ibld.c: New file.
 656         * or1k-opc.c: New file.
 657         * or1k-opc.h: New file.
 658         * or1k-opinst.c: New file.
 659         * Makefile.in: Regenerate.
 660         * configure: Regenerate.
 661         * openrisc-asm.c: Delete.
 662         * openrisc-desc.c: Delete.
 663         * openrisc-desc.h: Delete.
 664         * openrisc-dis.c: Delete.
 665         * openrisc-ibld.c: Delete.
 666         * openrisc-opc.c: Delete.
 667         * openrisc-opc.h: Delete.
 668         * or32-dis.c: Delete.
 669         * or32-opc.c: Delete.
 670
 671 2014-04-04  Ilya Tocar  <ilya.tocar@intel.com>
 672
 673         * i386-dis.c (rm_table): Add encls, enclu.
 674         * i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
 675         (cpu_flags): Add CpuSE1.
 676         * i386-opc.h (enum): Add CpuSE1.
 677         (i386_cpu_flags): Add cpuse1.
 678         * i386-opc.tbl: Add encls, enclu.
 679         * i386-init.h: Regenerated.
 680         * i386-tbl.h: Likewise.
 681
 682 2014-04-02  Anthony Green  <green@moxielogic.com>
 683
 684         * moxie-opc.c (moxie_form1_opc_info): Add sign-extension
 685         instructions, sex.b and sex.s.
 686
 687 2014-03-26  Jiong Wang  <jiong.wang@arm.com>
 688
 689         * aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
 690         instructions.
 691
 692 2014-03-20  Ilya Tocar  <ilya.tocar@intel.com>
 693
 694         * i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
 695         vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
 696         vscatterqps.
 697         * i386-tbl.h: Regenerate.
 698
 699 2014-03-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 700
 701         * sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
 702         %hstick_enable added.
 703
 704 2014-03-19  Nick Clifton  <nickc@redhat.com>
 705
 706         * rx-decode.opc (bwl): Allow for bogus instructions with a size
 707         field of 3.
 708         (sbwl, ubwl, SCALE): Likewise.
 709         * rx-decode.c: Regenerate.
 710
 711 2014-03-12  Alan Modra  <amodra@gmail.com>
 712
 713         * Makefile.in: Regenerate.
 714
 715 2014-03-05  Alan Modra  <amodra@gmail.com>
 716
 717         Update copyright years.
 718
 719 2014-03-04  Heiher  <r@hev.cc>
 720
 721         * mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
 722
 723 2014-03-04  Richard Sandiford  <rdsandiford@googlemail.com>
 724
 725         * mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
 726         so that they come after the Loongson extensions.
 727
 728 2014-03-03  Alan Modra  <amodra@gmail.com>
 729
 730         * i386-gen.c (process_copyright): Emit copyright notice on one line.
 731
 732 2014-02-28  Alan Modra  <amodra@gmail.com>
 733
 734         * msp430-decode.c: Regenerate.
 735
 736 2014-02-27  Jiong Wang  <jiong.wang@arm.com>
 737
 738         * aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
 739         FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.
 740
 741 2014-02-27  Yufeng Zhang  <yufeng.zhang@arm.com>
 742
 743         * aarch64-opc.c (print_register_offset_address): Call
 744         get_int_reg_name to prepare the register name.
 745
 746 2014-02-25  Ilya Tocar  <ilya.tocar@intel.com>
 747
 748         * i386-opc.tbl: Remove wrong variant of vcvtps2ph
 749         * i386-tbl.h: Regenerate.
 750
 751 2014-02-20  Ilya Tocar  <ilya.tocar@intel.com>
 752
 753         * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
 754         (cpu_flags): Add CpuPREFETCHWT1.
 755         * i386-init.h: Regenerate.
 756         * i386-opc.h (CpuPREFETCHWT1): New.
 757         (i386_cpu_flags): Add cpuprefetchwt1.
 758         * i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1.
 759         * i386-tbl.h: Regenerate.
 760
 761 2014-02-20  Ilya Tocar  <ilya.tocar@intel.com>
 762
 763         * i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD,
 764         to CpuAVX512F.
 765         * i386-tbl.h: Regenerate.
 766
 767 2014-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 768
 769         * i386-gen.c (output_cpu_flags): Don't output trailing space.
 770         (output_opcode_modifier): Likewise.
 771         (output_operand_type): Likewise.
 772         * i386-init.h: Regenerated.
 773         * i386-tbl.h: Likewise.
 774
 775 2014-02-12  Ilya Tocar  <ilya.tocar@intel.com>
 776
 777         * i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
 778         MOD_0FC7_REG_5.
 779         (PREFIX enum): Add PREFIX_0FAE_REG_7.
 780         (reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
 781         (prefix_table): Add clflusopt.
 782         (mod_table): Add xrstors, xsavec, xsaves.
 783         * i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
 784         CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
 785         (cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
 786         * i386-init.h: Regenerate.
 787         * i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
 788         xsaves64, xsavec, xsavec64.
 789         * i386-tbl.h: Regenerate.
 790
 791 2014-02-10  Alan Modra  <amodra@gmail.com>
 792
 793         * po/POTFILES.in: Regenerate.
 794         * po/opcodes.pot: Regenerate.
 795
 796 2014-01-30  Michael Zolotukhin  <michael.v.zolotukhin@gmail.com>
 797             Jan Beulich  <jbeulich@suse.com>
 798
 799         PR binutils/16490
 800         * i386-dis.c (OP_E_memory): Fix shift computation for
 801         vex_vsib_q_w_dq_mode.
 802
 803 2014-01-09  Bradley Nelson  <bradnelson@google.com>
 804             Roland McGrath  <mcgrathr@google.com>
 805
 806         * i386-dis.c (print_insn): Do not touch all_prefixes[-1] when
 807         last_rex_prefix is -1.
 808
 809 2014-01-08  H.J. Lu  <hongjiu.lu@intel.com>
 810
 811         * i386-gen.c (process_copyright): Update copyright year to 2014.
 812
 813 2014-01-03  Maciej W. Rozycki  <macro@codesourcery.com>
 814
 815         * nds32-asm.c (parse_operand): Fix out-of-range integer constant.
 816
 817 For older changes see ChangeLog-2013
 818 \f
 819 Copyright (C) 2014 Free Software Foundation, Inc.
 820
 821 Copying and distribution of this file, with or without modification,
 822 are permitted in any medium without royalty provided the copyright
 823 notice and this notice are preserved.
 824
 825 Local Variables:
 826 mode: change-log
 827 left-margin: 8
 828 fill-column: 74
 829 version-control: never
 830 End: