1 2018-09-13 Jan Beulich <jbeulich@suse.com>
3 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
5 * i386-tbl.h: Re-generate.
7 2018-09-13 Jan Beulich <jbeulich@suse.com>
9 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
11 * i386-tbl.h: Re-generate.
13 2018-09-13 Jan Beulich <jbeulich@suse.com>
15 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
16 * i386-tbl.h: Re-generate.
18 2018-09-13 Jan Beulich <jbeulich@suse.com>
20 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
21 * i386-tbl.h: Re-generate.
23 2018-09-13 Jan Beulich <jbeulich@suse.com>
25 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
26 * i386-tbl.h: Re-generate.
28 2018-09-13 Jan Beulich <jbeulich@suse.com>
30 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
32 * i386-tbl.h: Re-generate.
34 2018-09-13 Jan Beulich <jbeulich@suse.com>
36 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
38 * i386-tbl.h: Re-generate.
40 2018-09-13 Jan Beulich <jbeulich@suse.com>
42 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
44 * i386-tbl.h: Re-generate.
46 2018-09-13 Jan Beulich <jbeulich@suse.com>
48 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
49 * i386-tbl.h: Re-generate.
51 2018-09-13 Jan Beulich <jbeulich@suse.com>
53 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
54 * i386-tbl.h: Re-generate.
56 2018-09-13 Jan Beulich <jbeulich@suse.com>
58 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
59 * i386-tbl.h: Re-generate.
61 2018-09-13 Jan Beulich <jbeulich@suse.com>
63 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
64 (vpbroadcastw, rdpid): Drop NoRex64.
65 * i386-tbl.h: Re-generate.
67 2018-09-13 Jan Beulich <jbeulich@suse.com>
69 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
70 store templates, adding D.
71 * i386-tbl.h: Re-generate.
73 2018-09-13 Jan Beulich <jbeulich@suse.com>
75 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
76 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
77 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
78 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
79 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
80 Fold load and store templates where possible, adding D. Drop
81 IgnoreSize where it was pointlessly present. Drop redundant
83 * i386-tbl.h: Re-generate.
85 2018-09-13 Jan Beulich <jbeulich@suse.com>
87 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
88 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
89 (intel_operand_size): Handle v_bndmk_mode.
90 (OP_E_memory): Likewise. Produce (bad) when also riprel.
92 2018-09-08 John Darrington <john@darrington.wattle.id.au>
94 * disassemble.c (ARCH_s12z): Define if ARCH_all.
96 2018-08-31 Kito Cheng <kito@andestech.com>
98 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
99 compressed floating point instructions.
101 2018-08-30 Kito Cheng <kito@andestech.com>
103 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
104 riscv_opcode.xlen_requirement.
105 * riscv-opc.c (riscv_opcodes): Update for struct change.
107 2018-08-29 Martin Aberg <maberg@gaisler.com>
109 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
110 psr (PWRPSR) instruction.
112 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
114 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
116 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
118 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
120 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
122 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
123 loongson3a as an alias of gs464 for compatibility.
124 * mips-opc.c (mips_opcodes): Change Comments.
126 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
128 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
130 (print_mips_disassembler_options): Document -M loongson-ext.
131 * mips-opc.c (LEXT2): New macro.
132 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
134 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
136 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
138 (parse_mips_ase_option): Handle -M loongson-ext option.
139 (print_mips_disassembler_options): Document -M loongson-ext.
140 * mips-opc.c (IL3A): Delete.
141 * mips-opc.c (LEXT): New macro.
142 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
145 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
147 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
149 (parse_mips_ase_option): Handle -M loongson-cam option.
150 (print_mips_disassembler_options): Document -M loongson-cam.
151 * mips-opc.c (LCAM): New macro.
152 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
155 2018-08-21 Alan Modra <amodra@gmail.com>
157 * ppc-dis.c (operand_value_powerpc): Init "invalid".
158 (skip_optional_operands): Count optional operands, and update
159 ppc_optional_operand_value call.
160 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
161 (extract_vlensi): Likewise.
162 (extract_fxm): Return default value for missing optional operand.
163 (extract_ls, extract_raq, extract_tbr): Likewise.
164 (insert_sxl, extract_sxl): New functions.
165 (insert_esync, extract_esync): Remove Power9 handling and simplify.
166 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
167 flag and extra entry.
168 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
171 2018-08-20 Alan Modra <amodra@gmail.com>
173 * sh-opc.h (MASK): Simplify.
175 2018-08-18 John Darrington <john@darrington.wattle.id.au>
177 * s12z-dis.c (bm_decode): Deal with cases where the mode is
178 BM_RESERVED0 or BM_RESERVED1
179 (bm_rel_decode, bm_n_bytes): Ditto.
181 2018-08-18 John Darrington <john@darrington.wattle.id.au>
185 2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
187 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
188 address with the addr32 prefix and without base nor index
191 2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
193 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
194 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
195 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
196 (cpu_flags): Add CpuCMOV and CpuFXSR.
197 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
198 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
199 * i386-init.h: Regenerated.
200 * i386-tbl.h: Likewise.
202 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
204 * arc-regs.h: Update auxiliary registers.
206 2018-08-06 Jan Beulich <jbeulich@suse.com>
208 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
209 (RegIP, RegIZ): Define.
210 * i386-reg.tbl: Adjust comments.
211 (rip): Use Qword instead of BaseIndex. Use RegIP.
212 (eip): Use Dword instead of BaseIndex. Use RegIP.
213 (riz): Add Qword. Use RegIZ.
214 (eiz): Add Dword. Use RegIZ.
215 * i386-tbl.h: Re-generate.
217 2018-08-03 Jan Beulich <jbeulich@suse.com>
219 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
220 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
221 vpmovzxdq, vpmovzxwd): Remove NoRex64.
222 * i386-tbl.h: Re-generate.
224 2018-08-03 Jan Beulich <jbeulich@suse.com>
226 * i386-gen.c (operand_types): Remove Mem field.
227 * i386-opc.h (union i386_operand_type): Remove mem field.
228 * i386-init.h, i386-tbl.h: Re-generate.
230 2018-08-01 Alan Modra <amodra@gmail.com>
232 * po/POTFILES.in: Regenerate.
234 2018-07-31 Nick Clifton <nickc@redhat.com>
236 * po/sv.po: Updated Swedish translation.
238 2018-07-31 Jan Beulich <jbeulich@suse.com>
240 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
241 * i386-init.h, i386-tbl.h: Re-generate.
243 2018-07-31 Jan Beulich <jbeulich@suse.com>
245 * i386-opc.h (ZEROING_MASKING) Rename to ...
246 (DYNAMIC_MASKING): ... this. Adjust comment.
247 * i386-opc.tbl (MaskingMorZ): Define.
248 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
249 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
250 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
251 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
252 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
253 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
254 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
255 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
256 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
258 2018-07-31 Jan Beulich <jbeulich@suse.com>
260 * i386-opc.tbl: Use element rather than vector size for AVX512*
261 scatter/gather insns.
262 * i386-tbl.h: Re-generate.
264 2018-07-31 Jan Beulich <jbeulich@suse.com>
266 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
267 (cpu_flags): Drop CpuVREX.
268 * i386-opc.h (CpuVREX): Delete.
269 (union i386_cpu_flags): Remove cpuvrex.
270 * i386-init.h, i386-tbl.h: Re-generate.
272 2018-07-30 Jim Wilson <jimw@sifive.com>
274 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
276 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
278 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
280 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
281 * Makefile.in: Regenerated.
282 * configure.ac: Add C-SKY.
283 * configure: Regenerated.
284 * csky-dis.c: New file.
285 * csky-opc.h: New file.
286 * disassemble.c (ARCH_csky): Define.
287 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
288 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
290 2018-07-27 Alan Modra <amodra@gmail.com>
292 * ppc-opc.c (insert_sprbat): Correct function parameter and
294 (extract_sprbat): Likewise, variable too.
296 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
297 Alan Modra <amodra@gmail.com>
299 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
300 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
301 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
302 support disjointed BAT.
303 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
304 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
305 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
307 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
308 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
310 * i386-gen.c (adjust_broadcast_modifier): New function.
311 (process_i386_opcode_modifier): Add an argument for operands.
312 Adjust the Broadcast value based on operands.
313 (output_i386_opcode): Pass operand_types to
314 process_i386_opcode_modifier.
315 (process_i386_opcodes): Pass NULL as operands to
316 process_i386_opcode_modifier.
317 * i386-opc.h (BYTE_BROADCAST): New.
318 (WORD_BROADCAST): Likewise.
319 (DWORD_BROADCAST): Likewise.
320 (QWORD_BROADCAST): Likewise.
321 (i386_opcode_modifier): Expand broadcast to 3 bits.
322 * i386-tbl.h: Regenerated.
324 2018-07-24 Alan Modra <amodra@gmail.com>
327 * or1k-desc.h: Regenerate.
329 2018-07-24 Jan Beulich <jbeulich@suse.com>
331 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
332 vcvtusi2ss, and vcvtusi2sd.
333 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
334 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
335 * i386-tbl.h: Re-generate.
337 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
339 * arc-opc.c (extract_w6): Fix extending the sign.
341 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
343 * arc-tbl.h (vewt): Allow it for ARC EM family.
345 2018-07-23 Alan Modra <amodra@gmail.com>
348 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
349 opcode variants for mtspr/mfspr encodings.
351 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
352 Maciej W. Rozycki <macro@mips.com>
354 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
355 loongson3a descriptors.
356 (parse_mips_ase_option): Handle -M loongson-mmi option.
357 (print_mips_disassembler_options): Document -M loongson-mmi.
358 * mips-opc.c (LMMI): New macro.
359 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
362 2018-07-19 Jan Beulich <jbeulich@suse.com>
364 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
365 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
366 IgnoreSize and [XYZ]MMword where applicable.
367 * i386-tbl.h: Re-generate.
369 2018-07-19 Jan Beulich <jbeulich@suse.com>
371 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
372 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
373 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
374 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
375 * i386-tbl.h: Re-generate.
377 2018-07-19 Jan Beulich <jbeulich@suse.com>
379 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
380 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
381 VPCLMULQDQ templates into their respective AVX512VL counterparts
382 where possible, using Disp8ShiftVL and CheckRegSize instead of
383 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
384 * i386-tbl.h: Re-generate.
386 2018-07-19 Jan Beulich <jbeulich@suse.com>
388 * i386-opc.tbl: Fold AVX512DQ templates into their respective
389 AVX512VL counterparts where possible, using Disp8ShiftVL and
390 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
391 IgnoreSize) as appropriate.
392 * i386-tbl.h: Re-generate.
394 2018-07-19 Jan Beulich <jbeulich@suse.com>
396 * i386-opc.tbl: Fold AVX512BW templates into their respective
397 AVX512VL counterparts where possible, using Disp8ShiftVL and
398 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
399 IgnoreSize) as appropriate.
400 * i386-tbl.h: Re-generate.
402 2018-07-19 Jan Beulich <jbeulich@suse.com>
404 * i386-opc.tbl: Fold AVX512CD templates into their respective
405 AVX512VL counterparts where possible, using Disp8ShiftVL and
406 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
407 IgnoreSize) as appropriate.
408 * i386-tbl.h: Re-generate.
410 2018-07-19 Jan Beulich <jbeulich@suse.com>
412 * i386-opc.h (DISP8_SHIFT_VL): New.
413 * i386-opc.tbl (Disp8ShiftVL): Define.
414 (various): Fold AVX512VL templates into their respective
415 AVX512F counterparts where possible, using Disp8ShiftVL and
416 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
417 IgnoreSize) as appropriate.
418 * i386-tbl.h: Re-generate.
420 2018-07-19 Jan Beulich <jbeulich@suse.com>
422 * Makefile.am: Change dependencies and rule for
423 $(srcdir)/i386-init.h.
424 * Makefile.in: Re-generate.
425 * i386-gen.c (process_i386_opcodes): New local variable
426 "marker". Drop opening of input file. Recognize marker and line
428 * i386-opc.tbl (OPCODE_I386_H): Define.
429 (i386-opc.h): Include it.
432 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
435 * i386-opc.h (Byte): Update comments.
444 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
446 * i386-tbl.h: Regenerated.
448 2018-07-12 Sudakshina Das <sudi.das@arm.com>
450 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
451 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
452 * aarch64-asm-2.c: Regenerate.
453 * aarch64-dis-2.c: Regenerate.
454 * aarch64-opc-2.c: Regenerate.
456 2018-07-12 Tamar Christina <tamar.christina@arm.com>
459 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
460 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
461 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
462 sqdmulh, sqrdmulh): Use Em16.
464 2018-07-11 Sudakshina Das <sudi.das@arm.com>
466 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
467 csdb together with them.
468 (thumb32_opcodes): Likewise.
470 2018-07-11 Jan Beulich <jbeulich@suse.com>
472 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
473 requiring 32-bit registers as operands 2 and 3. Improve
475 (mwait, mwaitx): Fold templates. Improve comments.
476 OPERAND_TYPE_INOUTPORTREG.
477 * i386-tbl.h: Re-generate.
479 2018-07-11 Jan Beulich <jbeulich@suse.com>
481 * i386-gen.c (operand_type_init): Remove
482 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
483 OPERAND_TYPE_INOUTPORTREG.
484 * i386-init.h: Re-generate.
486 2018-07-11 Jan Beulich <jbeulich@suse.com>
488 * i386-opc.tbl (wrssd, wrussd): Add Dword.
489 (wrssq, wrussq): Add Qword.
490 * i386-tbl.h: Re-generate.
492 2018-07-11 Jan Beulich <jbeulich@suse.com>
494 * i386-opc.h: Rename OTMax to OTNum.
495 (OTNumOfUints): Adjust calculation.
496 (OTUnused): Directly alias to OTNum.
498 2018-07-09 Maciej W. Rozycki <macro@mips.com>
500 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
502 (lea_reg_xys): Likewise.
503 (print_insn_loop_primitive): Rename `reg' local variable to
506 2018-07-06 Tamar Christina <tamar.christina@arm.com>
509 * aarch64-tbl.h (ldarh): Fix disassembly mask.
511 2018-07-06 Tamar Christina <tamar.christina@arm.com>
514 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
515 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
517 2018-07-02 Maciej W. Rozycki <macro@mips.com>
520 * mips-dis.c (mips_option_arg_t): New enumeration.
521 (mips_options): New variable.
522 (disassembler_options_mips): New function.
523 (print_mips_disassembler_options): Reimplement in terms of
524 `disassembler_options_mips'.
525 * arm-dis.c (disassembler_options_arm): Adapt to using the
526 `disasm_options_and_args_t' structure.
527 * ppc-dis.c (disassembler_options_powerpc): Likewise.
528 * s390-dis.c (disassembler_options_s390): Likewise.
530 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
532 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
534 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
535 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
536 * testsuite/ld-arm/tls-longplt.d: Likewise.
538 2018-06-29 Tamar Christina <tamar.christina@arm.com>
541 * aarch64-asm-2.c: Regenerate.
542 * aarch64-dis-2.c: Likewise.
543 * aarch64-opc-2.c: Likewise.
544 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
545 * aarch64-opc.c (operand_general_constraint_met_p,
546 aarch64_print_operand): Likewise.
547 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
548 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
550 (AARCH64_OPERANDS): Add Em2.
552 2018-06-26 Nick Clifton <nickc@redhat.com>
554 * po/uk.po: Updated Ukranian translation.
555 * po/de.po: Updated German translation.
556 * po/pt_BR.po: Updated Brazilian Portuguese translation.
558 2018-06-26 Nick Clifton <nickc@redhat.com>
560 * nfp-dis.c: Fix spelling mistake.
562 2018-06-24 Nick Clifton <nickc@redhat.com>
564 * configure: Regenerate.
565 * po/opcodes.pot: Regenerate.
567 2018-06-24 Nick Clifton <nickc@redhat.com>
571 2018-06-19 Tamar Christina <tamar.christina@arm.com>
573 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
574 * aarch64-asm-2.c: Regenerate.
575 * aarch64-dis-2.c: Likewise.
577 2018-06-21 Maciej W. Rozycki <macro@mips.com>
579 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
580 `-M ginv' option description.
582 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
585 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
588 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
590 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
591 * configure.ac: Remove AC_PREREQ.
592 * Makefile.in: Re-generate.
593 * aclocal.m4: Re-generate.
594 * configure: Re-generate.
596 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
598 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
599 mips64r6 descriptors.
600 (parse_mips_ase_option): Handle -Mginv option.
601 (print_mips_disassembler_options): Document -Mginv.
602 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
604 (mips_opcodes): Define ginvi and ginvt.
606 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
607 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
609 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
610 * mips-opc.c (CRC, CRC64): New macros.
611 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
612 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
615 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
618 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
619 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
621 2018-06-06 Alan Modra <amodra@gmail.com>
623 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
624 setjmp. Move init for some other vars later too.
626 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
628 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
629 (dis_private): Add new fields for property section tracking.
630 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
631 (xtensa_instruction_fits): New functions.
632 (fetch_data): Bump minimal fetch size to 4.
633 (print_insn_xtensa): Make struct dis_private static.
634 Load and prepare property table on section change.
635 Don't disassemble literals. Don't disassemble instructions that
636 cross property table boundaries.
638 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
640 * configure: Regenerated.
642 2018-06-01 Jan Beulich <jbeulich@suse.com>
644 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
645 * i386-tbl.h: Re-generate.
647 2018-06-01 Jan Beulich <jbeulich@suse.com>
649 * i386-opc.tbl (sldt, str): Add NoRex64.
650 * i386-tbl.h: Re-generate.
652 2018-06-01 Jan Beulich <jbeulich@suse.com>
654 * i386-opc.tbl (invpcid): Add Oword.
655 * i386-tbl.h: Re-generate.
657 2018-06-01 Alan Modra <amodra@gmail.com>
659 * sysdep.h (_bfd_error_handler): Don't declare.
660 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
661 * rl78-decode.opc: Likewise.
662 * msp430-decode.c: Regenerate.
663 * rl78-decode.c: Regenerate.
665 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
667 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
668 * i386-init.h : Regenerated.
670 2018-05-25 Alan Modra <amodra@gmail.com>
672 * Makefile.in: Regenerate.
673 * po/POTFILES.in: Regenerate.
675 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
677 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
678 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
679 (insert_bab, extract_bab, insert_btab, extract_btab,
680 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
681 (BAT, BBA VBA RBS XB6S): Delete macros.
682 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
683 (BB, BD, RBX, XC6): Update for new macros.
684 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
685 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
686 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
687 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
689 2018-05-18 John Darrington <john@darrington.wattle.id.au>
691 * Makefile.am: Add support for s12z architecture.
692 * configure.ac: Likewise.
693 * disassemble.c: Likewise.
694 * disassemble.h: Likewise.
695 * Makefile.in: Regenerate.
696 * configure: Regenerate.
697 * s12z-dis.c: New file.
700 2018-05-18 Alan Modra <amodra@gmail.com>
702 * nfp-dis.c: Don't #include libbfd.h.
703 (init_nfp3200_priv): Use bfd_get_section_contents.
704 (nit_nfp6000_mecsr_sec): Likewise.
706 2018-05-17 Nick Clifton <nickc@redhat.com>
708 * po/zh_CN.po: Updated simplified Chinese translation.
710 2018-05-16 Tamar Christina <tamar.christina@arm.com>
713 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
714 * aarch64-dis-2.c: Regenerate.
716 2018-05-15 Tamar Christina <tamar.christina@arm.com>
719 * aarch64-asm.c (opintl.h): Include.
720 (aarch64_ins_sysreg): Enforce read/write constraints.
721 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
722 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
723 (F_REG_READ, F_REG_WRITE): New.
724 * aarch64-opc.c (aarch64_print_operand): Generate notes for
726 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
727 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
728 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
729 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
730 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
731 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
732 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
733 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
734 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
735 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
736 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
737 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
738 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
739 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
740 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
741 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
742 msr (F_SYS_WRITE), mrs (F_SYS_READ).
744 2018-05-15 Tamar Christina <tamar.christina@arm.com>
747 * aarch64-dis.c (no_notes: New.
748 (parse_aarch64_dis_option): Support notes.
749 (aarch64_decode_insn, print_operands): Likewise.
750 (print_aarch64_disassembler_options): Document notes.
751 * aarch64-opc.c (aarch64_print_operand): Support notes.
753 2018-05-15 Tamar Christina <tamar.christina@arm.com>
756 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
757 and take error struct.
758 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
759 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
760 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
761 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
762 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
763 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
764 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
765 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
766 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
767 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
768 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
769 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
770 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
771 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
772 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
773 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
774 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
775 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
776 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
777 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
778 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
779 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
780 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
781 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
782 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
783 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
784 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
785 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
786 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
787 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
788 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
789 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
790 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
791 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
792 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
793 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
794 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
795 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
796 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
797 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
798 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
799 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
800 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
801 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
802 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
803 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
804 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
805 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
806 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
807 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
808 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
809 (determine_disassembling_preference, aarch64_decode_insn,
810 print_insn_aarch64_word, print_insn_data): Take errors struct.
811 (print_insn_aarch64): Use errors.
812 * aarch64-asm-2.c: Regenerate.
813 * aarch64-dis-2.c: Regenerate.
814 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
815 boolean in aarch64_insert_operan.
816 (print_operand_extractor): Likewise.
817 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
819 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
821 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
823 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
825 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
827 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
829 * cr16-opc.c (cr16_instruction): Comment typo fix.
830 * hppa-dis.c (print_insn_hppa): Likewise.
832 2018-05-08 Jim Wilson <jimw@sifive.com>
834 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
835 (match_c_slli64, match_srxi_as_c_srxi): New.
836 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
837 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
838 <c.slli, c.srli, c.srai>: Use match_s_slli.
839 <c.slli64, c.srli64, c.srai64>: New.
841 2018-05-08 Alan Modra <amodra@gmail.com>
843 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
844 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
845 partition opcode space for index lookup.
847 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
849 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
850 <insn_length>: ...with this. Update usage.
851 Remove duplicate call to *info->memory_error_func.
853 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
854 H.J. Lu <hongjiu.lu@intel.com>
856 * i386-dis.c (Gva): New.
857 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
858 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
859 (prefix_table): New instructions (see prefix above).
860 (mod_table): New instructions (see prefix above).
861 (OP_G): Handle va_mode.
862 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
864 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
865 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
866 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
867 * i386-opc.tbl: Add movidir{i,64b}.
868 * i386-init.h: Regenerated.
869 * i386-tbl.h: Likewise.
871 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
873 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
875 * i386-opc.h (AddrPrefixOp0): Renamed to ...
876 (AddrPrefixOpReg): This.
877 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
878 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
880 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
882 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
883 (vle_num_opcodes): Likewise.
884 (spe2_num_opcodes): Likewise.
885 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
887 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
888 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
891 2018-05-01 Tamar Christina <tamar.christina@arm.com>
893 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
895 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
897 Makefile.am: Added nfp-dis.c.
898 configure.ac: Added bfd_nfp_arch.
899 disassemble.h: Added print_insn_nfp prototype.
900 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
901 nfp-dis.c: New, for NFP support.
902 po/POTFILES.in: Added nfp-dis.c to the list.
903 Makefile.in: Regenerate.
904 configure: Regenerate.
906 2018-04-26 Jan Beulich <jbeulich@suse.com>
908 * i386-opc.tbl: Fold various non-memory operand AVX512VL
909 templates into their base ones.
910 * i386-tlb.h: Re-generate.
912 2018-04-26 Jan Beulich <jbeulich@suse.com>
914 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
915 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
916 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
917 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
918 * i386-init.h: Re-generate.
920 2018-04-26 Jan Beulich <jbeulich@suse.com>
922 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
923 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
924 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
925 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
927 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
929 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
931 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
932 cpuregzmm, and cpuregmask.
933 * i386-init.h: Re-generate.
934 * i386-tbl.h: Re-generate.
936 2018-04-26 Jan Beulich <jbeulich@suse.com>
938 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
939 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
940 * i386-init.h: Re-generate.
942 2018-04-26 Jan Beulich <jbeulich@suse.com>
944 * i386-gen.c (VexImmExt): Delete.
945 * i386-opc.h (VexImmExt, veximmext): Delete.
946 * i386-opc.tbl: Drop all VexImmExt uses.
947 * i386-tlb.h: Re-generate.
949 2018-04-25 Jan Beulich <jbeulich@suse.com>
951 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
953 * i386-tlb.h: Re-generate.
955 2018-04-25 Tamar Christina <tamar.christina@arm.com>
957 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
959 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
961 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
963 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
964 (cpu_flags): Add CpuCLDEMOTE.
965 * i386-init.h: Regenerate.
966 * i386-opc.h (enum): Add CpuCLDEMOTE,
967 (i386_cpu_flags): Add cpucldemote.
968 * i386-opc.tbl: Add cldemote.
969 * i386-tbl.h: Regenerate.
971 2018-04-16 Alan Modra <amodra@gmail.com>
973 * Makefile.am: Remove sh5 and sh64 support.
974 * configure.ac: Likewise.
975 * disassemble.c: Likewise.
976 * disassemble.h: Likewise.
977 * sh-dis.c: Likewise.
978 * sh64-dis.c: Delete.
979 * sh64-opc.c: Delete.
980 * sh64-opc.h: Delete.
981 * Makefile.in: Regenerate.
982 * configure: Regenerate.
983 * po/POTFILES.in: Regenerate.
985 2018-04-16 Alan Modra <amodra@gmail.com>
987 * Makefile.am: Remove w65 support.
988 * configure.ac: Likewise.
989 * disassemble.c: Likewise.
990 * disassemble.h: Likewise.
993 * Makefile.in: Regenerate.
994 * configure: Regenerate.
995 * po/POTFILES.in: Regenerate.
997 2018-04-16 Alan Modra <amodra@gmail.com>
999 * configure.ac: Remove we32k support.
1000 * configure: Regenerate.
1002 2018-04-16 Alan Modra <amodra@gmail.com>
1004 * Makefile.am: Remove m88k support.
1005 * configure.ac: Likewise.
1006 * disassemble.c: Likewise.
1007 * disassemble.h: Likewise.
1008 * m88k-dis.c: Delete.
1009 * Makefile.in: Regenerate.
1010 * configure: Regenerate.
1011 * po/POTFILES.in: Regenerate.
1013 2018-04-16 Alan Modra <amodra@gmail.com>
1015 * Makefile.am: Remove i370 support.
1016 * configure.ac: Likewise.
1017 * disassemble.c: Likewise.
1018 * disassemble.h: Likewise.
1019 * i370-dis.c: Delete.
1020 * i370-opc.c: Delete.
1021 * Makefile.in: Regenerate.
1022 * configure: Regenerate.
1023 * po/POTFILES.in: Regenerate.
1025 2018-04-16 Alan Modra <amodra@gmail.com>
1027 * Makefile.am: Remove h8500 support.
1028 * configure.ac: Likewise.
1029 * disassemble.c: Likewise.
1030 * disassemble.h: Likewise.
1031 * h8500-dis.c: Delete.
1032 * h8500-opc.h: Delete.
1033 * Makefile.in: Regenerate.
1034 * configure: Regenerate.
1035 * po/POTFILES.in: Regenerate.
1037 2018-04-16 Alan Modra <amodra@gmail.com>
1039 * configure.ac: Remove tahoe support.
1040 * configure: Regenerate.
1042 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1044 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1046 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1048 * i386-tbl.h: Regenerated.
1050 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1052 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1053 PREFIX_MOD_1_0FAE_REG_6.
1055 (OP_E_register): Use va_mode.
1056 * i386-dis-evex.h (prefix_table):
1057 New instructions (see prefixes above).
1058 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1059 (cpu_flags): Likewise.
1060 * i386-opc.h (enum): Likewise.
1061 (i386_cpu_flags): Likewise.
1062 * i386-opc.tbl: Add umonitor, umwait, tpause.
1063 * i386-init.h: Regenerate.
1064 * i386-tbl.h: Likewise.
1066 2018-04-11 Alan Modra <amodra@gmail.com>
1068 * opcodes/i860-dis.c: Delete.
1069 * opcodes/i960-dis.c: Delete.
1070 * Makefile.am: Remove i860 and i960 support.
1071 * configure.ac: Likewise.
1072 * disassemble.c: Likewise.
1073 * disassemble.h: Likewise.
1074 * Makefile.in: Regenerate.
1075 * configure: Regenerate.
1076 * po/POTFILES.in: Regenerate.
1078 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1081 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1083 (print_insn): Clear vex instead of vex.evex.
1085 2018-04-04 Nick Clifton <nickc@redhat.com>
1087 * po/es.po: Updated Spanish translation.
1089 2018-03-28 Jan Beulich <jbeulich@suse.com>
1091 * i386-gen.c (opcode_modifiers): Delete VecESize.
1092 * i386-opc.h (VecESize): Delete.
1093 (struct i386_opcode_modifier): Delete vecesize.
1094 * i386-opc.tbl: Drop VecESize.
1095 * i386-tlb.h: Re-generate.
1097 2018-03-28 Jan Beulich <jbeulich@suse.com>
1099 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1100 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1101 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1102 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1103 * i386-tlb.h: Re-generate.
1105 2018-03-28 Jan Beulich <jbeulich@suse.com>
1107 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1109 * i386-tlb.h: Re-generate.
1111 2018-03-28 Jan Beulich <jbeulich@suse.com>
1113 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1114 (vex_len_table): Drop Y for vcvt*2si.
1115 (putop): Replace plain 'Y' handling by abort().
1117 2018-03-28 Nick Clifton <nickc@redhat.com>
1120 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1121 instructions with only a base address register.
1122 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1123 handle AARHC64_OPND_SVE_ADDR_R.
1124 (aarch64_print_operand): Likewise.
1125 * aarch64-asm-2.c: Regenerate.
1126 * aarch64_dis-2.c: Regenerate.
1127 * aarch64-opc-2.c: Regenerate.
1129 2018-03-22 Jan Beulich <jbeulich@suse.com>
1131 * i386-opc.tbl: Drop VecESize from register only insn forms and
1132 memory forms not allowing broadcast.
1133 * i386-tlb.h: Re-generate.
1135 2018-03-22 Jan Beulich <jbeulich@suse.com>
1137 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1138 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1139 sha256*): Drop Disp<N>.
1141 2018-03-22 Jan Beulich <jbeulich@suse.com>
1143 * i386-dis.c (EbndS, bnd_swap_mode): New.
1144 (prefix_table): Use EbndS.
1145 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1146 * i386-opc.tbl (bndmov): Move misplaced Load.
1147 * i386-tlb.h: Re-generate.
1149 2018-03-22 Jan Beulich <jbeulich@suse.com>
1151 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1152 templates allowing memory operands and folded ones for register
1154 * i386-tlb.h: Re-generate.
1156 2018-03-22 Jan Beulich <jbeulich@suse.com>
1158 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1159 256-bit templates. Drop redundant leftover Disp<N>.
1160 * i386-tlb.h: Re-generate.
1162 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
1164 * riscv-opc.c (riscv_insn_types): New.
1166 2018-03-13 Nick Clifton <nickc@redhat.com>
1168 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1170 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1172 * i386-opc.tbl: Add Optimize to clr.
1173 * i386-tbl.h: Regenerated.
1175 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1177 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1178 * i386-opc.h (OldGcc): Removed.
1179 (i386_opcode_modifier): Remove oldgcc.
1180 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1181 instructions for old (<= 2.8.1) versions of gcc.
1182 * i386-tbl.h: Regenerated.
1184 2018-03-08 Jan Beulich <jbeulich@suse.com>
1186 * i386-opc.h (EVEXDYN): New.
1187 * i386-opc.tbl: Fold various AVX512VL templates.
1188 * i386-tlb.h: Re-generate.
1190 2018-03-08 Jan Beulich <jbeulich@suse.com>
1192 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1193 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1194 vpexpandd, vpexpandq): Fold AFX512VF templates.
1195 * i386-tlb.h: Re-generate.
1197 2018-03-08 Jan Beulich <jbeulich@suse.com>
1199 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1200 Fold 128- and 256-bit VEX-encoded templates.
1201 * i386-tlb.h: Re-generate.
1203 2018-03-08 Jan Beulich <jbeulich@suse.com>
1205 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1206 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1207 vpexpandd, vpexpandq): Fold AVX512F templates.
1208 * i386-tlb.h: Re-generate.
1210 2018-03-08 Jan Beulich <jbeulich@suse.com>
1212 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1213 64-bit templates. Drop Disp<N>.
1214 * i386-tlb.h: Re-generate.
1216 2018-03-08 Jan Beulich <jbeulich@suse.com>
1218 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1219 and 256-bit templates.
1220 * i386-tlb.h: Re-generate.
1222 2018-03-08 Jan Beulich <jbeulich@suse.com>
1224 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1225 * i386-tlb.h: Re-generate.
1227 2018-03-08 Jan Beulich <jbeulich@suse.com>
1229 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1231 * i386-tlb.h: Re-generate.
1233 2018-03-08 Jan Beulich <jbeulich@suse.com>
1235 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1236 * i386-tlb.h: Re-generate.
1238 2018-03-08 Jan Beulich <jbeulich@suse.com>
1240 * i386-gen.c (opcode_modifiers): Delete FloatD.
1241 * i386-opc.h (FloatD): Delete.
1242 (struct i386_opcode_modifier): Delete floatd.
1243 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1245 * i386-tlb.h: Re-generate.
1247 2018-03-08 Jan Beulich <jbeulich@suse.com>
1249 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1251 2018-03-08 Jan Beulich <jbeulich@suse.com>
1253 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1254 * i386-tlb.h: Re-generate.
1256 2018-03-08 Jan Beulich <jbeulich@suse.com>
1258 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1260 * i386-tlb.h: Re-generate.
1262 2018-03-07 Alan Modra <amodra@gmail.com>
1264 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1266 * disassemble.h (print_insn_rs6000): Delete.
1267 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1268 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1269 (print_insn_rs6000): Delete.
1271 2018-03-03 Alan Modra <amodra@gmail.com>
1273 * sysdep.h (opcodes_error_handler): Define.
1274 (_bfd_error_handler): Declare.
1275 * Makefile.am: Remove stray #.
1276 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1278 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1279 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1280 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1281 opcodes_error_handler to print errors. Standardize error messages.
1282 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1283 and include opintl.h.
1284 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1285 * i386-gen.c: Standardize error messages.
1286 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1287 * Makefile.in: Regenerate.
1288 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1289 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1290 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1291 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1292 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1293 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1294 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1295 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1296 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1297 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1298 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1299 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1300 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1302 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1304 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1305 vpsub[bwdq] instructions.
1306 * i386-tbl.h: Regenerated.
1308 2018-03-01 Alan Modra <amodra@gmail.com>
1310 * configure.ac (ALL_LINGUAS): Sort.
1311 * configure: Regenerate.
1313 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1315 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1316 macro by assignements.
1318 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1321 * i386-gen.c (opcode_modifiers): Add Optimize.
1322 * i386-opc.h (Optimize): New enum.
1323 (i386_opcode_modifier): Add optimize.
1324 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1325 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1326 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1327 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1328 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1330 * i386-tbl.h: Regenerated.
1332 2018-02-26 Alan Modra <amodra@gmail.com>
1334 * crx-dis.c (getregliststring): Allocate a large enough buffer
1335 to silence false positive gcc8 warning.
1337 2018-02-22 Shea Levy <shea@shealevy.com>
1339 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1341 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1343 * i386-opc.tbl: Add {rex},
1344 * i386-tbl.h: Regenerated.
1346 2018-02-20 Maciej W. Rozycki <macro@mips.com>
1348 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1349 (mips16_opcodes): Replace `M' with `m' for "restore".
1351 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1353 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1355 2018-02-13 Maciej W. Rozycki <macro@mips.com>
1357 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1358 variable to `function_index'.
1360 2018-02-13 Nick Clifton <nickc@redhat.com>
1363 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1364 about truncation of printing.
1366 2018-02-12 Henry Wong <henry@stuffedcow.net>
1368 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1370 2018-02-05 Nick Clifton <nickc@redhat.com>
1372 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1374 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1376 * i386-dis.c (enum): Add pconfig.
1377 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1378 (cpu_flags): Add CpuPCONFIG.
1379 * i386-opc.h (enum): Add CpuPCONFIG.
1380 (i386_cpu_flags): Add cpupconfig.
1381 * i386-opc.tbl: Add PCONFIG instruction.
1382 * i386-init.h: Regenerate.
1383 * i386-tbl.h: Likewise.
1385 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1387 * i386-dis.c (enum): Add PREFIX_0F09.
1388 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1389 (cpu_flags): Add CpuWBNOINVD.
1390 * i386-opc.h (enum): Add CpuWBNOINVD.
1391 (i386_cpu_flags): Add cpuwbnoinvd.
1392 * i386-opc.tbl: Add WBNOINVD instruction.
1393 * i386-init.h: Regenerate.
1394 * i386-tbl.h: Likewise.
1396 2018-01-17 Jim Wilson <jimw@sifive.com>
1398 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1400 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1402 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1403 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1404 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1405 (cpu_flags): Add CpuIBT, CpuSHSTK.
1406 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1407 (i386_cpu_flags): Add cpuibt, cpushstk.
1408 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1409 * i386-init.h: Regenerate.
1410 * i386-tbl.h: Likewise.
1412 2018-01-16 Nick Clifton <nickc@redhat.com>
1414 * po/pt_BR.po: Updated Brazilian Portugese translation.
1415 * po/de.po: Updated German translation.
1417 2018-01-15 Jim Wilson <jimw@sifive.com>
1419 * riscv-opc.c (match_c_nop): New.
1420 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1422 2018-01-15 Nick Clifton <nickc@redhat.com>
1424 * po/uk.po: Updated Ukranian translation.
1426 2018-01-13 Nick Clifton <nickc@redhat.com>
1428 * po/opcodes.pot: Regenerated.
1430 2018-01-13 Nick Clifton <nickc@redhat.com>
1432 * configure: Regenerate.
1434 2018-01-13 Nick Clifton <nickc@redhat.com>
1436 2.30 branch created.
1438 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1440 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1441 * i386-tbl.h: Regenerate.
1443 2018-01-10 Jan Beulich <jbeulich@suse.com>
1445 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1446 * i386-tbl.h: Re-generate.
1448 2018-01-10 Jan Beulich <jbeulich@suse.com>
1450 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1451 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1452 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1453 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1454 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1455 Disp8MemShift of AVX512VL forms.
1456 * i386-tbl.h: Re-generate.
1458 2018-01-09 Jim Wilson <jimw@sifive.com>
1460 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1461 then the hi_addr value is zero.
1463 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1465 * arm-dis.c (arm_opcodes): Add csdb.
1466 (thumb32_opcodes): Add csdb.
1468 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1470 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1471 * aarch64-asm-2.c: Regenerate.
1472 * aarch64-dis-2.c: Regenerate.
1473 * aarch64-opc-2.c: Regenerate.
1475 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1478 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1479 Remove AVX512 vmovd with 64-bit operands.
1480 * i386-tbl.h: Regenerated.
1482 2018-01-05 Jim Wilson <jimw@sifive.com>
1484 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1487 2018-01-03 Alan Modra <amodra@gmail.com>
1489 Update year range in copyright notice of all files.
1491 2018-01-02 Jan Beulich <jbeulich@suse.com>
1493 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1494 and OPERAND_TYPE_REGZMM entries.
1496 For older changes see ChangeLog-2017
1498 Copyright (C) 2018 Free Software Foundation, Inc.
1500 Copying and distribution of this file, with or without modification,
1501 are permitted in any medium without royalty provided the copyright
1502 notice and this notice are preserved.
1508 version-control: never