opcodes/ChangeLog

   1 2021-11-25  Andrew Burgess  <aburgess@redhat.com>
   2             Simon Cook  <simon.cook@embecosm.com>
   3
   4         * riscv-dis.c (enum riscv_option_arg_t): New enum typedef.
   5         (riscv_options): New static global.
   6         (disassembler_options_riscv): New function.
   7         (print_riscv_disassembler_options): Rewrite to use
   8         disassembler_options_riscv.
   9
  10 2021-11-25  Nick Clifton  <nickc@redhat.com>
  11
  12         PR 28614
  13         * aarch64-asm.c: Replace assert(0) with real code.
  14         * aarch64-dis.c: Likewise.
  15         * aarch64-opc.c: Likewise.
  16
  17 2021-11-25  Nick Clifton  <nickc@redhat.com>
  18
  19         * po/fr.po; Updated French translation.
  20
  21 2021-10-27  Maciej W. Rozycki  <macro@embecosm.com>
  22
  23         * Makefile.am: Remove obsolete comment.
  24         * configure.ac: Refer `libbfd.la' to link shared BFD library
  25         except for Cygwin.
  26         * Makefile.in: Regenerate.
  27         * configure: Regenerate.
  28
  29 2021-09-27  Nick Alcock  <nick.alcock@oracle.com>
  30
  31         * configure: Regenerate.
  32
  33 2021-09-25  Peter Bergner  <bergner@linux.ibm.com>
  34
  35         * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
  36         on POWER5 and later.
  37
  38 2021-09-20  Andrew Burgess  <andrew.burgess@embecosm.com>
  39
  40         * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
  41         before an unknown instruction, '%d' is replaced with the
  42         instruction length.
  43
  44 2021-09-02  Nick Clifton  <nickc@redhat.com>
  45
  46         PR 28292
  47         * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
  48         of BFD_RELOC_16.
  49
  50 2021-08-17  Shahab Vahedi <shahab@synopsys.com>
  51
  52         * arc-regs.h (DEF): Fix the register numbers.
  53
  54 2021-08-10  Nick Clifton  <nickc@redhat.com>
  55
  56         * po/sr.po: Updated Serbian translation.
  57
  58 2021-07-26  Chenghua Xu  <xuchenghua@loongson.cn>
  59
  60         * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
  61
  62 2021-06-07  Andreas Krebbel  <krebbel@linux.ibm.com>
  63
  64         * s390-opc.txt: Add qpaci.
  65
  66 2021-07-03  Nick Clifton  <nickc@redhat.com>
  67
  68         * configure: Regenerate.
  69         * po/opcodes.pot: Regenerate.
  70
  71 2021-07-03  Nick Clifton  <nickc@redhat.com>
  72
  73         * 2.37 release branch created.
  74
  75 2021-07-02  Alan Modra  <amodra@gmail.com>
  76
  77         * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
  78         (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
  79         (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
  80         (nds32_opcodes, nds32_operand_fields, nds32_keywords),
  81         (nds32_keyword_gpr): Move declarations to..
  82         * nds32-asm.h: ..here, constifying to match definitions.
  83
  84 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  85
  86         * Makefile.am (GUILE): New variable.
  87         (CGEN): Use $(GUILE).
  88         * Makefile.in: Regenerate.
  89
  90 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  91
  92         * mep-asm.c (macros): Mark static & const.
  93         (lookup_macro): Change return & m to const.
  94         (expand_macro): Change mac to const.
  95         (expand_string): Change pmacro to const.
  96
  97 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  98
  99         * nds32-asm.c (operand_fields): Rename to ...
 100         (nds32_operand_fields): ... this.
 101         (keyword_gpr): Rename to ...
 102         (nds32_keyword_gpr): ... this.
 103         (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
 104         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
 105         keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
 106         keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
 107         keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
 108         Mark static.
 109         (keywords): Rename to ...
 110         (nds32_keywords): ... this.
 111         * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
 112         keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
 113
 114 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 115
 116         * z80-dis.c (opc_ed): Make const.
 117         (pref_ed): Make p const.
 118
 119 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 120
 121         * microblaze-dis.c (get_field_special): Make op const.
 122         (read_insn_microblaze): Make opr & op const.  Rename opcodes to
 123         microblaze_opcodes.
 124         (print_insn_microblaze): Make op & pop const.
 125         (get_insn_microblaze): Make op const.  Rename opcodes to
 126         microblaze_opcodes.
 127         (microblaze_get_target_address): Likewise.
 128         * microblaze-opc.h (struct op_code_struct): Make const.
 129         Rename opcodes to microblaze_opcodes.
 130
 131 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 132
 133         * aarch64-gen.c (aarch64_opcode_table): Add const.
 134         * aarch64-tbl.h (aarch64_opcode_table): Likewise.
 135
 136 2021-06-22  Andrew Burgess  <andrew.burgess@embecosm.com>
 137
 138         * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
 139         available.
 140
 141 2021-06-22  Alan Modra  <amodra@gmail.com>
 142
 143         * pj-dis.c (print_insn_pj): Don't print trailing tab.  Do
 144         print separator for pcrel insns.
 145
 146 2021-06-19  Alan Modra  <amodra@gmail.com>
 147
 148         * vax-dis.c (print_insn_vax): Avoid pointer overflow.
 149
 150 2021-06-19  Alan Modra  <amodra@gmail.com>
 151
 152         * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
 153         entire buffer.
 154
 155 2021-06-17  Alan Modra  <amodra@gmail.com>
 156
 157         * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
 158         in table.
 159
 160 2021-06-03  Alan Modra  <amodra@gmail.com>
 161
 162         PR 1202
 163         * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
 164         Use unsigned int for inst.
 165
 166 2021-06-02  Shahab Vahedi  <shahab@synopsys.com>
 167
 168         * arc-dis.c (arc_option_arg_t): New enumeration.
 169         (arc_options): New variable.
 170         (disassembler_options_arc): New function.
 171         (print_arc_disassembler_options): Reimplement in terms of
 172         "disassembler_options_arc".
 173
 174 2021-05-29  Alan Modra  <amodra@gmail.com>
 175
 176         * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
 177         Don't special case PPC_OPCODE_RAW.
 178         (lookup_prefix): Likewise.
 179         (lookup_vle, lookup_spe2): Similarly.  Add dialect parameter and..
 180         (print_insn_powerpc): ..update caller.
 181         * ppc-opc.c (EXT): Define.
 182         (powerpc_opcodes): Mark extended mnemonics with EXT.
 183         (prefix_opcodes, vle_opcodes): Likewise.
 184         (XISEL, XISEL_MASK): Add cr field and simplify.
 185         (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
 186         all isel variants to where the base mnemonic belongs.  Sort dstt,
 187         dststt and dssall.
 188
 189 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 190
 191         * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
 192         COP3 opcode instructions.
 193
 194 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 195
 196         * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
 197         "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
 198         "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
 199         "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
 200         "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
 201         "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
 202         "cop2", and "cop3" entries.
 203
 204 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 205
 206         * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
 207         entries and associated comments.
 208
 209 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 210
 211         * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
 212         of "c0".
 213
 214 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 215
 216         * mips-dis.c (mips_cp1_names_mips): New variable.
 217         (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
 218         for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
 219         "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
 220         "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
 221         "r12000", "r14000", "r16000", "mips5", "loongson2e", and
 222         "loongson2f".
 223
 224 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 225
 226         * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
 227         handling code over to...
 228         <OP_REG_CONTROL>: ... this new case.
 229         * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
 230         (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
 231         "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
 232         replacing the `G' operand code with `g'.  Update "cftc1" and
 233         "cftc2" entries replacing the `E' operand code with `y'.
 234         * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
 235         (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
 236         entries replacing the `G' operand code with `g'.
 237
 238 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 239
 240         * mips-dis.c (mips_cp0_names_r3900): New variable.
 241         (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
 242         for "r3900".
 243
 244 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 245
 246         * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
 247         and "mtthc2" to using the `G' rather than `g' operand code for
 248         the coprocessor control register referred.
 249
 250 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 251
 252         * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
 253         entries with each other.
 254
 255 2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
 256
 257         * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
 258
 259 2021-05-25  Alan Modra  <amodra@gmail.com>
 260
 261         * cris-desc.c: Regenerate.
 262         * cris-desc.h: Regenerate.
 263         * cris-opc.h: Regenerate.
 264         * po/POTFILES.in: Regenerate.
 265
 266 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
 267
 268         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
 269         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
 270         (CGEN_CPUS): Add cris.
 271         (CRIS_DEPS): Define.
 272         (stamp-cris): New rule.
 273         * cgen.sh: Handle desc action.
 274         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
 275         * Makefile.in, configure: Regenerate.
 276
 277 2021-05-18  Job Noorman  <mtvec@pm.me>
 278
 279         PR 27814
 280         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
 281         the elf objects.
 282
 283 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
 284
 285         * arm-dis.c (mve_opcodes): Fix disassembly of
 286         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
 287         (is_mve_encoding_conflict): MVE vector loads should not match
 288         when P = W = 0.
 289         (is_mve_unpredictable): It's not unpredictable to use the same
 290         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
 291
 292 2021-05-11  Nick Clifton  <nickc@redhat.com>
 293
 294         PR 27840
 295         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
 296         the end of the code buffer.
 297
 298 2021-05-06  Stafford Horne  <shorne@gmail.com>
 299
 300         PR 21464
 301         * or1k-asm.c: Regenerate.
 302
 303 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
 304
 305         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
 306         info->insn_info_valid.
 307
 308 2021-04-26  Jan Beulich  <jbeulich@suse.com>
 309
 310         * i386-opc.tbl (lea): Add Optimize.
 311         * opcodes/i386-tbl.h: Re-generate.
 312
 313 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 314
 315         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
 316         of l32r fetch and display referenced literal value.
 317
 318 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 319
 320         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
 321         to 4 for literal disassembly.
 322
 323 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 324
 325         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
 326         for TLBI instruction.
 327
 328 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 329
 330         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
 331         DC instruction.
 332
 333 2021-04-19  Jan Beulich  <jbeulich@suse.com>
 334
 335         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
 336         "qualifier".
 337         (convert_mov_to_movewide): Add initializer for "value".
 338
 339 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 340
 341         * aarch64-opc.c: Add RME system registers.
 342
 343 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
 344
 345         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
 346         "addi d,CV,z" to "c.mv d,CV".
 347
 348 2021-04-12  Alan Modra  <amodra@gmail.com>
 349
 350         * configure.ac (--enable-checking): Add support.
 351         * config.in: Regenerate.
 352         * configure: Regenerate.
 353
 354 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
 355
 356         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
 357         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 358
 359 2021-04-09  Alan Modra  <amodra@gmail.com>
 360
 361         * ppc-dis.c (struct dis_private): Add "special".
 362         (POWERPC_DIALECT): Delete.  Replace uses with..
 363         (private_data): ..this.  New inline function.
 364         (disassemble_init_powerpc): Init "special" names.
 365         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 366         field of prefix instructions.
 367         (bsearch_reloc, print_got_plt): New functions.
 368         (print_insn_powerpc): For pcrel instructions, print target address
 369         and symbol if known, and decode plt and got loads too.
 370
 371 2021-04-08  Alan Modra  <amodra@gmail.com>
 372
 373         PR 27684
 374         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 375
 376 2021-04-08  Alan Modra  <amodra@gmail.com>
 377
 378         PR 27676
 379         * ppc-opc.c (DCBT_EO): Move earlier.
 380         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 381         (powerpc_operands): Add THCT and THDS entries.
 382         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 383
 384 2021-04-06  Alan Modra  <amodra@gmail.com>
 385
 386         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 387         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 388         symbol_at_address_func.
 389
 390 2021-04-05  Alan Modra  <amodra@gmail.com>
 391
 392         * configure.ac: Don't check for limits.h, string.h, strings.h or
 393         stdlib.h.
 394         (AC_ISC_POSIX): Don't invoke.
 395         * sysdep.h: Include stdlib.h and string.h unconditionally.
 396         * i386-opc.h: Include limits.h unconditionally.
 397         * wasm32-dis.c: Likewise.
 398         * cgen-opc.c: Don't include alloca-conf.h.
 399         * config.in: Regenerate.
 400         * configure: Regenerate.
 401
 402 2021-04-01  Martin Liska  <mliska@suse.cz>
 403
 404         * arm-dis.c (strneq): Remove strneq and use startswith.
 405         * cr16-dis.c (print_insn_cr16): Likewise.
 406         * score-dis.c (streq): Likewise.
 407         (strneq): Likewise.
 408         * score7-dis.c (strneq): Likewise.
 409
 410 2021-04-01  Alan Modra  <amodra@gmail.com>
 411
 412         PR 27675
 413         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 414
 415 2021-03-31  Alan Modra  <amodra@gmail.com>
 416
 417         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 418         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 419         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 420         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 421         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 422         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 423         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 424         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 425         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 426         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 427         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 428         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 429         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 430         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 431         and TRUE with true throughout.
 432
 433 2021-03-31  Alan Modra  <amodra@gmail.com>
 434
 435         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 436         * aarch64-dis.h: Likewise.
 437         * aarch64-opc.c: Likewise.
 438         * avr-dis.c: Likewise.
 439         * csky-dis.c: Likewise.
 440         * nds32-asm.c: Likewise.
 441         * nds32-dis.c: Likewise.
 442         * nfp-dis.c: Likewise.
 443         * riscv-dis.c: Likewise.
 444         * s12z-dis.c: Likewise.
 445         * wasm32-dis.c: Likewise.
 446
 447 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 448
 449         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 450         (i386_seg_prefixes): New.
 451         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 452         (i386_seg_prefixes): Declare.
 453
 454 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 455
 456         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 457
 458 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 459
 460         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 461         * i386-reg.tbl (st): Move down.
 462         (st(0)): Delete. Extend comment.
 463         * i386-tbl.h: Re-generate.
 464
 465 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 466
 467         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 468         (cmpsd): Move next to cmps.
 469         (movsd): Move next to movs.
 470         (cmpxchg16b): Move to separate section.
 471         (fisttp, fisttpll): Likewise.
 472         (monitor, mwait): Likewise.
 473         * i386-tbl.h: Re-generate.
 474
 475 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 476
 477         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 478         (vpsadbw): Add C.
 479         * i386-tbl.h: Re-generate.
 480
 481 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 482
 483         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 484         pclmul, gfni): New templates. Use them wherever possible. Move
 485         SSE4.1 pextrw into respective section.
 486         * i386-tbl.h: Re-generate.
 487
 488 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 489
 490         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 491         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 492         "length".
 493         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 494         Convert all of their uses to representation in opcode.
 495
 496 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 497
 498         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 499         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 500         value of None. Shrink operands to 3 bits.
 501
 502 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 503
 504         * i386-gen.c (process_i386_opcode_modifier): New parameter
 505         "space".
 506         (output_i386_opcode): New local variable "space". Adjust
 507         process_i386_opcode_modifier() invocation.
 508         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 509         invocation.
 510         * i386-tbl.h: Re-generate.
 511
 512 2021-03-29  Alan Modra  <amodra@gmail.com>
 513
 514         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 515         (fp_qualifier_p, get_data_pattern): Likewise.
 516         (aarch64_get_operand_modifier_from_value): Likewise.
 517         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 518         (operand_variant_qualifier_p): Likewise.
 519         (qualifier_value_in_range_constraint_p): Likewise.
 520         (aarch64_get_qualifier_esize): Likewise.
 521         (aarch64_get_qualifier_nelem): Likewise.
 522         (aarch64_get_qualifier_standard_value): Likewise.
 523         (get_lower_bound, get_upper_bound): Likewise.
 524         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 525         (aarch64_print_operand): Likewise.
 526         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 527         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 528         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 529         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 530         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 531         (print_insn_tic6x): Likewise.
 532
 533 2021-03-29  Alan Modra  <amodra@gmail.com>
 534
 535         * arc-dis.c (extract_operand_value): Correct NULL cast.
 536         * frv-opc.h: Regenerate.
 537
 538 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 539
 540         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 541         MMX form.
 542         * i386-tbl.h: Re-generate.
 543
 544 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 545
 546         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 547         immediate in br.n instruction.
 548
 549 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 550
 551         * i386-dis.c (XMGatherD, VexGatherD): New.
 552         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 553         (print_insn): Check masking for S/G insns.
 554         (OP_E_memory): New local variable check_gather. Extend mandatory
 555         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 556         Extend check for disallowed 16-bit addressing.
 557         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 558         if()s to switch(). Check register conflicts for (VEX-encoded)
 559         gathers. Drop no longer reachable cases.
 560         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 561         vgatherdp*.
 562
 563 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 564
 565         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 566         zeroing-masking without masking.
 567
 568 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 569
 570         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 571         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 572         single-operand forms as deprecated.
 573         * i386-tbl.h: Re-generate.
 574
 575 2021-03-25  Alan Modra  <amodra@gmail.com>
 576
 577         PR 27647
 578         * ppc-opc.c (XLOCB_MASK): Delete.
 579         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 580         XLBH_MASK.
 581         (powerpc_opcodes): Accept a BH field on all extended forms of
 582         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 583
 584 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 585
 586         * i386-gen.c (output_i386_opcode): Drop processing of
 587         opcode_length. Calculate length from base_opcode. Adjust prefix
 588         encoding determination.
 589         (process_i386_opcodes): Drop output of fake opcode_length.
 590         * i386-opc.h (struct insn_template): Drop opcode_length field.
 591         * i386-opc.tbl: Drop opcode length field from all templates.
 592         * i386-tbl.h: Re-generate.
 593
 594 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 595
 596         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 597         parameter "prefix". Drop local variable "regular_encoding".
 598         Record prefix setting / check for consistency.
 599         (output_i386_opcode): Parse opcode_length and base_opcode
 600         earlier. Derive prefix encoding. Drop no longer applicable
 601         consistency checking. Adjust process_i386_opcode_modifier()
 602         invocation.
 603         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 604         invocation.
 605         * i386-tbl.h: Re-generate.
 606
 607 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 608
 609         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 610         check.
 611         * i386-opc.h (Prefix_*): Move #define-s.
 612         * i386-opc.tbl: Move pseudo prefix enumerator values to
 613         extension opcode field. Introduce pseudopfx template.
 614         * i386-tbl.h: Re-generate.
 615
 616 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 617
 618         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 619         comment.
 620         * i386-tbl.h: Re-generate.
 621
 622 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 623
 624         * i386-opc.h (struct insn_template): Move cpu_flags field past
 625         opcode_modifier one.
 626         * i386-tbl.h: Re-generate.
 627
 628 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 629
 630         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 631         * i386-opc.h (OpcodeSpace): New enumerator.
 632         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 633         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 634         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 635         (struct i386_opcode_modifier): New field opcodespace. Shrink
 636         opcodeprefix field.
 637         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 638         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 639         OpcodePrefix uses.
 640         * i386-tbl.h: Re-generate.
 641
 642 2021-03-22  Martin Liska  <mliska@suse.cz>
 643
 644         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 645         * arc-dis.c (parse_option): Likewise.
 646         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 647         * cris-dis.c (print_with_operands): Likewise.
 648         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 649         * i386-dis.c (print_insn): Likewise.
 650         * ia64-gen.c (fetch_insn_class): Likewise.
 651         (parse_resource_users): Likewise.
 652         (in_iclass): Likewise.
 653         (lookup_specifier): Likewise.
 654         (insert_opcode_dependencies): Likewise.
 655         * mips-dis.c (parse_mips_ase_option): Likewise.
 656         (parse_mips_dis_option): Likewise.
 657         * s390-dis.c (disassemble_init_s390): Likewise.
 658         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 659
 660 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 661
 662         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 663
 664 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 665
 666         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 667         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 668
 669 2021-03-12  Alan Modra  <amodra@gmail.com>
 670
 671         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 672
 673 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 674
 675         * i386-dis.c (OP_XMM): Re-order checks.
 676
 677 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 678
 679         * i386-dis.c (putop): Drop need_vex check when also checking
 680         vex.evex.
 681         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 682         checking vex.b.
 683
 684 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 685
 686         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 687         checks. Move case label past broadcast check.
 688
 689 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 690
 691         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 692         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 693         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 694         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 695         EVEX_W_0F38C7_M_0_L_2): Delete.
 696         (REG_EVEX_0F38C7_M_0_L_2): New.
 697         (intel_operand_size): Handle VEX and EVEX the same for
 698         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 699         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 700         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 701         vex_vsib_q_w_d_mode uses.
 702         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 703         0F38A1, and 0F38A3 entries.
 704         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 705         entry.
 706         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 707         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 708         0F38A3 entries.
 709
 710 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 711
 712         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 713         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 714         MOD_VEX_0FXOP_09_12): Rename to ...
 715         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 716         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 717         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 718         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 719         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 720         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 721         (reg_table): Adjust comments.
 722         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 723         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 724         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 725         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 726         (vex_len_table): Adjust opcode 0A_12 entry.
 727         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 728         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 729         (rm_table): Move hreset entry.
 730
 731 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 732
 733         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 734         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 735         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 736         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 737         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 738         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 739         (get_valid_dis386): Also handle 512-bit vector length when
 740         vectoring into vex_len_table[].
 741         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 742         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 743         entries.
 744         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 745         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 746         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 747         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 748         entries.
 749
 750 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 751
 752         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 753         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 754         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 755         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 756         entries.
 757         * i386-dis-evex-len.h (evex_len_table): Likewise.
 758         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 759
 760 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 761
 762         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 763         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 764         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 765         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 766         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 767         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 768         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 769         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 770         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 771         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 772         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 773         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 774         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 775         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 776         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 777         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 778         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 779         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 780         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 781         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 782         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 783         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 784         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 785         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 786         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 787         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 788         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 789         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 790         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 791         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 792         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 793         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 794         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 795         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 796         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 797         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 798         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 799         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 800         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 801         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 802         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 803         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 804         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 805         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 806         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 807         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 808         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 809         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 810         EVEX_W_0F3A43_L_n): New.
 811         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 812         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 813         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 814         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 815         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 816         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 817         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 818         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 819         0F385B, 0F38C6, and 0F38C7 entries.
 820         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 821         0F38C6 and 0F38C7.
 822         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 823         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 824         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 825         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 826
 827 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 828
 829         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 830         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 831         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 832         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 833         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 834         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 835         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 836         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 837         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 838         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 839         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 840         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 841         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 842         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 843         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 844         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 845         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 846         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 847         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 848         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 849         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 850         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 851         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 852         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 853         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 854         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 855         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 856         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 857         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 858         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 859         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 860         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 861         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 862         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 863         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 864         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 865         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 866         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 867         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 868         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 869         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 870         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 871         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 872         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 873         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 874         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 875         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 876         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 877         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 878         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 879         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 880         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 881         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 882         VEX_W_0F99_P_2_LEN_0): Delete.
 883         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 884         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 885         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 886         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 887         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 888         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 889         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 890         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 891         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 892         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 893         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 894         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 895         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 896         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 897         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 898         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 899         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 900         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 901         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 902         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 903         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 904         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 905         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 906         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 907         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 908         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 909         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 910         (prefix_table): No longer link to vex_len_table[] for opcodes
 911         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 912         0F92, 0F93, 0F98, and 0F99.
 913         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 914         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 915         0F98, and 0F99.
 916         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 917         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 918         0F98, and 0F99.
 919         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 920         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 921         0F98, and 0F99.
 922         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 923         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 924         0F98, and 0F99.
 925
 926 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 927
 928         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 929         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 930         REG_VEX_0F73_M_0 respectively.
 931         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 932         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 933         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 934         MOD_VEX_0F73_REG_7): Delete.
 935         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 936         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 937         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 938         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 939         PREFIX_VEX_0F3AF0_L_0 respectively.
 940         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 941         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 942         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 943         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 944         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 945         VEX_LEN_0F38F7): New.
 946         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 947         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 948         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 949         0F38F3.
 950         (prefix_table): No longer link to vex_len_table[] for opcodes
 951         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 952         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 953         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 954         0F38F6, 0F38F7, and 0F3AF0.
 955         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 956         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 957         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 958         0F73.
 959
 960 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 961
 962         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 963         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 964         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 965         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 966         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 967         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 968         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 969         73.
 970         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 971         0F72, and 0F73.
 972         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 973         0F73.
 974
 975 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 976
 977         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 978         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 979         (reg_table): Don't link to mod_table[] where not needed. Add
 980         PREFIX_IGNORED to nop entries.
 981         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 982         (mod_table): Add nop entries next to prefetch ones. Drop
 983         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 984         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 985         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 986         PREFIX_OPCODE from endbr* entries.
 987         (get_valid_dis386): Also consider entry's name when zapping
 988         vindex.
 989         (print_insn): Handle PREFIX_IGNORED.
 990
 991 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 992
 993         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 994         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 995         element.
 996         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 997         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 998         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 999         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
1000         (struct i386_opcode_modifier): Delete notrackprefixok,
1001         islockable, hleprefixok, and repprefixok fields. Add prefixok
1002         field.
1003         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
1004         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
1005         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
1006         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
1007         Replace HLEPrefixOk.
1008         * opcodes/i386-tbl.h: Re-generate.
1009
1010 2021-03-09  Jan Beulich  <jbeulich@suse.com>
1011
1012         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
1013         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
1014         64-bit form.
1015         * opcodes/i386-tbl.h: Re-generate.
1016
1017 2021-03-03  Jan Beulich  <jbeulich@suse.com>
1018
1019         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
1020         for {} instead of {0}. Don't look for '0'.
1021         * i386-opc.tbl: Drop operand count field. Drop redundant operand
1022         size specifiers.
1023
1024 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
1025
1026         PR 27158
1027         * riscv-dis.c (print_insn_args): Updated encoding macros.
1028         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
1029         (match_c_addi16sp): Updated encoding macros.
1030         (match_c_lui): Likewise.
1031         (match_c_lui_with_hint): Likewise.
1032         (match_c_addi4spn): Likewise.
1033         (match_c_slli): Likewise.
1034         (match_slli_as_c_slli): Likewise.
1035         (match_c_slli64): Likewise.
1036         (match_srxi_as_c_srxi): Likewise.
1037         (riscv_insn_types): Added .insn css/cl/cs.
1038
1039 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
1040
1041         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1042         (default_priv_spec): Updated type to riscv_spec_class.
1043         (parse_riscv_dis_option): Updated.
1044         * riscv-opc.c: Moved stuff and make the file tidy.
1045
1046 2021-02-17  Alan Modra  <amodra@gmail.com>
1047
1048         * wasm32-dis.c: Include limits.h.
1049         (CHAR_BIT): Provide backup define.
1050         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1051         Correct signed overflow checking.
1052
1053 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1054
1055         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1056         * i386-tbl.h: Re-generate.
1057
1058 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1059
1060         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1061         Oword.
1062         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1063
1064 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
1065
1066         * s390-mkopc.c (main): Accept arch14 as cpu string.
1067         * s390-opc.txt: Add new arch14 instructions.
1068
1069 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
1070
1071         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1072         favour of LIBINTL.
1073         * configure: Regenerated.
1074
1075 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
1076
1077         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1078         * tic54x-opc.c (regs): Rename to ...
1079         (tic54x_regs): ... this.
1080         (mmregs): Rename to ...
1081         (tic54x_mmregs): ... this.
1082         (condition_codes): Rename to ...
1083         (tic54x_condition_codes): ... this.
1084         (cc2_codes): Rename to ...
1085         (tic54x_cc2_codes): ... this.
1086         (cc3_codes): Rename to ...
1087         (tic54x_cc3_codes): ... this.
1088         (status_bits): Rename to ...
1089         (tic54x_status_bits): ... this.
1090         (misc_symbols): Rename to ...
1091         (tic54x_misc_symbols): ... this.
1092
1093 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
1094
1095         * riscv-opc.c (MASK_RVB_IMM): Removed.
1096         (riscv_opcodes): Removed zb* instructions.
1097         (riscv_ext_version_table): Removed versions for zb*.
1098
1099 2021-01-26  Alan Modra  <amodra@gmail.com>
1100
1101         * i386-gen.c (parse_template): Ensure entire template_instance
1102         is initialised.
1103
1104 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1105
1106         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1107         (riscv_fpr_names_abi): Likewise.
1108         (riscv_opcodes): Likewise.
1109         (riscv_insn_types): Likewise.
1110
1111 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1112
1113         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1114
1115 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1116
1117         * riscv-dis.c: Comments tidy and improvement.
1118         * riscv-opc.c: Likewise.
1119
1120 2021-01-13  Alan Modra  <amodra@gmail.com>
1121
1122         * Makefile.in: Regenerate.
1123
1124 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
1125
1126         PR binutils/26792
1127         * configure.ac: Use GNU_MAKE_JOBSERVER.
1128         * aclocal.m4: Regenerated.
1129         * configure: Likewise.
1130
1131 2021-01-12  Nick Clifton  <nickc@redhat.com>
1132
1133         * po/sr.po: Updated Serbian translation.
1134
1135 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
1136
1137         PR ld/27173
1138         * configure: Regenerated.
1139
1140 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1141
1142         * aarch64-asm-2.c: Regenerate.
1143         * aarch64-dis-2.c: Likewise.
1144         * aarch64-opc-2.c: Likewise.
1145         * aarch64-opc.c (aarch64_print_operand):
1146         Delete handling of AARCH64_OPND_CSRE_CSR.
1147         * aarch64-tbl.h (aarch64_feature_csre): Delete.
1148         (CSRE): Likewise.
1149         (_CSRE_INSN): Likewise.
1150         (aarch64_opcode_table): Delete csr.
1151
1152 2021-01-11  Nick Clifton  <nickc@redhat.com>
1153
1154         * po/de.po: Updated German translation.
1155         * po/fr.po: Updated French translation.
1156         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1157         * po/sv.po: Updated Swedish translation.
1158         * po/uk.po: Updated Ukranian translation.
1159
1160 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
1161
1162         * configure: Regenerated.
1163
1164 2021-01-09  Nick Clifton  <nickc@redhat.com>
1165
1166         * configure: Regenerate.
1167         * po/opcodes.pot: Regenerate.
1168
1169 2021-01-09  Nick Clifton  <nickc@redhat.com>
1170
1171         * 2.36 release branch crated.
1172
1173 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
1174
1175         * ppc-opc.c (insert_dw, (extract_dw): New functions.
1176         (DW, (XRC_MASK): Define.
1177         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1178
1179 2021-01-09  Alan Modra  <amodra@gmail.com>
1180
1181         * configure: Regenerate.
1182
1183 2021-01-08  Nick Clifton  <nickc@redhat.com>
1184
1185         * po/sv.po: Updated Swedish translation.
1186
1187 2021-01-08  Nick Clifton  <nickc@redhat.com>
1188
1189         PR 27129
1190         * aarch64-dis.c (determine_disassembling_preference): Move call to
1191         aarch64_match_operands_constraint outside of the assertion.
1192         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1193         Replace with a return of FALSE.
1194
1195         PR 27139
1196         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1197         core system register.
1198
1199 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
1200
1201         * configure: Regenerate.
1202
1203 2021-01-07  Nick Clifton  <nickc@redhat.com>
1204
1205         * po/fr.po: Updated French translation.
1206
1207 2021-01-07  Fredrik Noring  <noring@nocrew.org>
1208
1209         * m68k-opc.c (chkl): Change minimum architecture requirement to
1210         m68020.
1211
1212 2021-01-07  Philipp Tomsich  <prt@gnu.org>
1213
1214         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1215
1216 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
1217             Jim Wilson  <jimw@sifive.com>
1218             Andrew Waterman  <andrew@sifive.com>
1219             Maxim Blinov  <maxim.blinov@embecosm.com>
1220             Kito Cheng  <kito.cheng@sifive.com>
1221             Nelson Chu  <nelson.chu@sifive.com>
1222
1223         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1224         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1225
1226 2021-01-01  Alan Modra  <amodra@gmail.com>
1227
1228         Update year range in copyright notice of all files.
1229
1230 For older changes see ChangeLog-2020
1231 \f
1232 Copyright (C) 2021 Free Software Foundation, Inc.
1233
1234 Copying and distribution of this file, with or without modification,
1235 are permitted in any medium without royalty provided the copyright
1236 notice and this notice are preserved.
1237
1238 Local Variables:
1239 mode: change-log
1240 left-margin: 8
1241 fill-column: 74
1242 version-control: never
1243 End: