1 2015-06-01 Jan Beulich <jbeulich@suse.com>
3 * i386-dis.c (print_insn): Swap rounding mode specifier and
4 general purpose register in Intel mode.
6 2015-06-01 Jan Beulich <jbeulich@suse.com>
8 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
9 * i386-tbl.h: Regenerate.
11 2015-05-18 H.J. Lu <hongjiu.lu@intel.com>
13 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
14 * i386-init.h: Regenerated.
16 2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
19 * i386-dis.c: Add comments for '@'.
20 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
21 (enum x86_64_isa): New.
23 (print_i386_disassembler_options): Add amd64 and intel64.
24 (print_insn): Handle amd64 and intel64.
26 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
27 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
28 * i386-opc.h (AMD64): New.
29 (CpuIntel64): Likewise.
30 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
31 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
32 Mark direct call/jmp without Disp16|Disp32 as Intel64.
33 * i386-init.h: Regenerated.
34 * i386-tbl.h: Likewise.
36 2015-05-14 Peter Bergner <bergner@vnet.ibm.com>
38 * ppc-opc.c (IH) New define.
39 (powerpc_opcodes) <wait>: Do not enable for POWER7.
40 <tlbie>: Add RS operand for POWER7.
41 <slbia>: Add IH operand for POWER6.
43 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
45 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
48 * i386-tbl.h: Regenerated.
50 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
52 * configure.ac: Support bfd_iamcu_arch.
53 * disassemble.c (disassembler): Support bfd_iamcu_arch.
54 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
55 CPU_IAMCU_COMPAT_FLAGS.
56 (cpu_flags): Add CpuIAMCU.
57 * i386-opc.h (CpuIAMCU): New.
58 (i386_cpu_flags): Add cpuiamcu.
59 * configure: Regenerated.
60 * i386-init.h: Likewise.
61 * i386-tbl.h: Likewise.
63 2015-05-08 H.J. Lu <hongjiu.lu@intel.com>
66 * i386-dis.c (X86_64_E8): New.
67 (X86_64_E9): Likewise.
68 Update comments on 'T', 'U', 'V'. Add comments for '^'.
69 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
70 (x86_64_table): Add X86_64_E8 and X86_64_E9.
71 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
73 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
76 2015-04-30 DJ Delorie <dj@redhat.com>
78 * disassemble.c (disassembler): Choose suitable disassembler based
80 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
81 it to decode mul/div insns.
82 * rl78-decode.c: Regenerate.
83 * rl78-dis.c (print_insn_rl78): Rename to...
84 (print_insn_rl78_common): ...this, take ISA parameter.
85 (print_insn_rl78): New.
86 (print_insn_rl78_g10): New.
87 (print_insn_rl78_g13): New.
88 (print_insn_rl78_g14): New.
89 (rl78_get_disassembler): New.
91 2015-04-29 Nick Clifton <nickc@redhat.com>
93 * po/fr.po: Updated French translation.
95 2015-04-27 Peter Bergner <bergner@vnet.ibm.com>
97 * ppc-opc.c (DCBT_EO): New define.
98 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
102 <waitrsv>: Do not enable for POWER7 and later.
103 <waitimpl>: Likewise.
104 <dcbt>: Default to the two operand form of the instruction for all
105 "old" cpus. For "new" cpus, use the operand ordering that matches
106 whether the cpu is server or embedded.
109 2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
111 * s390-opc.c: New instruction type VV0UU2.
112 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
115 2015-04-23 Jan Beulich <jbeulich@suse.com>
117 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
118 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
119 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
120 (vfpclasspd, vfpclassps): Add %XZ.
122 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
124 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
125 (PREFIX_UD_REPZ): Likewise.
126 (PREFIX_UD_REPNZ): Likewise.
127 (PREFIX_UD_DATA): Likewise.
128 (PREFIX_UD_ADDR): Likewise.
129 (PREFIX_UD_LOCK): Likewise.
131 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
133 * i386-dis.c (prefix_requirement): Removed.
134 (print_insn): Don't set prefix_requirement. Check
135 dp->prefix_requirement instead of prefix_requirement.
137 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
140 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
141 (PREFIX_MOD_0_0FC7_REG_6): This.
142 (PREFIX_MOD_3_0FC7_REG_6): New.
143 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
144 (prefix_table): Replace PREFIX_0FC7_REG_6 with
145 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
146 PREFIX_MOD_3_0FC7_REG_7.
147 (mod_table): Replace PREFIX_0FC7_REG_6 with
148 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
149 PREFIX_MOD_3_0FC7_REG_7.
151 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
153 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
154 (PREFIX_MANDATORY_REPNZ): Likewise.
155 (PREFIX_MANDATORY_DATA): Likewise.
156 (PREFIX_MANDATORY_ADDR): Likewise.
157 (PREFIX_MANDATORY_LOCK): Likewise.
158 (PREFIX_MANDATORY): Likewise.
159 (PREFIX_UD_SHIFT): Set to 8
160 (PREFIX_UD_REPZ): Updated.
161 (PREFIX_UD_REPNZ): Likewise.
162 (PREFIX_UD_DATA): Likewise.
163 (PREFIX_UD_ADDR): Likewise.
164 (PREFIX_UD_LOCK): Likewise.
165 (PREFIX_IGNORED_SHIFT): New.
166 (PREFIX_IGNORED_REPZ): Likewise.
167 (PREFIX_IGNORED_REPNZ): Likewise.
168 (PREFIX_IGNORED_DATA): Likewise.
169 (PREFIX_IGNORED_ADDR): Likewise.
170 (PREFIX_IGNORED_LOCK): Likewise.
171 (PREFIX_OPCODE): Likewise.
172 (PREFIX_IGNORED): Likewise.
173 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
174 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
175 (three_byte_table): Likewise.
176 (mod_table): Likewise.
177 (mandatory_prefix): Renamed to ...
178 (prefix_requirement): This.
179 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
180 Update PREFIX_90 entry.
181 (get_valid_dis386): Check prefix_requirement to see if a prefix
183 (print_insn): Replace mandatory_prefix with prefix_requirement.
185 2015-04-15 Renlin Li <renlin.li@arm.com>
187 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
188 use it for ssat and ssat16.
189 (print_insn_thumb32): Add handle case for 'D' control code.
191 2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
192 H.J. Lu <hongjiu.lu@intel.com>
194 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
195 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
196 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
197 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
198 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
199 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
200 Fill prefix_requirement field.
201 (struct dis386): Add prefix_requirement field.
202 (dis386): Fill prefix_requirement field.
203 (dis386_twobyte): Ditto.
204 (twobyte_has_mandatory_prefix_: Remove.
205 (reg_table): Fill prefix_requirement field.
206 (prefix_table): Ditto.
207 (x86_64_table): Ditto.
208 (three_byte_table): Ditto.
211 (vex_len_table): Ditto.
212 (vex_w_table): Ditto.
215 (print_insn): Use prefix_requirement.
216 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
217 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
220 2015-03-30 Mike Frysinger <vapier@gentoo.org>
222 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
224 2015-03-29 H.J. Lu <hongjiu.lu@intel.com>
226 * Makefile.in: Regenerated.
228 2015-03-25 Anton Blanchard <anton@samba.org>
230 * ppc-dis.c (disassemble_init_powerpc): Only initialise
231 powerpc_opcd_indices and vle_opcd_indices once.
233 2015-03-25 Anton Blanchard <anton@samba.org>
235 * ppc-opc.c (powerpc_opcodes): Add slbfee.
237 2015-03-24 Terry Guo <terry.guo@arm.com>
239 * arm-dis.c (opcode32): Updated to use new arm feature struct.
240 (opcode16): Likewise.
241 (coprocessor_opcodes): Replace bit with feature struct.
242 (neon_opcodes): Likewise.
243 (arm_opcodes): Likewise.
244 (thumb_opcodes): Likewise.
245 (thumb32_opcodes): Likewise.
246 (print_insn_coprocessor): Likewise.
247 (print_insn_arm): Likewise.
248 (select_arm_features): Follow new feature struct.
250 2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
252 * i386-dis.c (rm_table): Add clzero.
253 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
254 Add CPU_CLZERO_FLAGS.
255 (cpu_flags): Add CpuCLZERO.
256 * i386-opc.h: Add CpuCLZERO.
257 * i386-opc.tbl: Add clzero.
258 * i386-init.h: Re-generated.
259 * i386-tbl.h: Re-generated.
261 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
263 * mips-opc.c (decode_mips_operand): Fix constraint issues
264 with u and y operands.
266 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
268 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
270 2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
272 * s390-opc.c: Add new IBM z13 instructions.
273 * s390-opc.txt: Likewise.
275 2015-03-10 Renlin Li <renlin.li@arm.com>
277 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
278 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
280 * aarch64-asm-2.c: Regenerate.
281 * aarch64-dis-2.c: Likewise.
282 * aarch64-opc-2.c: Likewise.
284 2015-03-03 Jiong Wang <jiong.wang@arm.com>
286 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
288 2015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
290 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
292 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
293 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
295 2015-02-23 Vinay <Vinay.G@kpit.com>
297 * rl78-decode.opc (MOV): Added space between two operands for
298 'mov' instruction in index addressing mode.
299 * rl78-decode.c: Regenerate.
301 2015-02-19 Pedro Alves <palves@redhat.com>
303 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
305 2015-02-10 Pedro Alves <palves@redhat.com>
306 Tom Tromey <tromey@redhat.com>
308 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
309 microblaze_and, microblaze_xor.
310 * microblaze-opc.h (opcodes): Adjust.
312 2015-01-28 James Bowman <james.bowman@ftdichip.com>
314 * Makefile.am: Add FT32 files.
315 * configure.ac: Handle FT32.
316 * disassemble.c (disassembler): Call print_insn_ft32.
317 * ft32-dis.c: New file.
318 * ft32-opc.c: New file.
319 * Makefile.in: Regenerate.
320 * configure: Regenerate.
321 * po/POTFILES.in: Regenerate.
323 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
325 * nds32-asm.c (keyword_sr): Add new system registers.
327 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
329 * s390-dis.c (s390_extract_operand): Support vector register
331 (s390_print_insn_with_opcode): Support new operands types and add
332 new handling of optional operands.
333 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
334 and include opcode/s390.h instead.
335 (struct op_struct): New field `flags'.
336 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
337 (dumpTable): Dump flags.
338 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
340 * s390-opc.c: Add new operands types, instruction formats, and
342 (s390_opformats): Add new formats for .insn.
343 * s390-opc.txt: Add new instructions.
345 2015-01-01 Alan Modra <amodra@gmail.com>
347 Update year range in copyright notice of all files.
349 For older changes see ChangeLog-2014
351 Copyright (C) 2015 Free Software Foundation, Inc.
353 Copying and distribution of this file, with or without modification,
354 are permitted in any medium without royalty provided the copyright
355 notice and this notice are preserved.
361 version-control: never