opcodes/ChangeLog

   1 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
   2
   3         * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
   4         instructions.  Fix them to use WR_MACC instead of WR_CC and
   5         add missing RD_MACCs.
   6
   7 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
   8
   9         * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
  10
  11 2013-07-29  Peter Bergner <bergner@vnet.ibm.com>
  12
  13         * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
  14
  15 2013-07-26  Sergey Guriev  <sergey.s.guriev@intel.com>
  16             Alexander Ivchenko  <alexander.ivchenko@intel.com>
  17             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
  18             Sergey Lega  <sergey.s.lega@intel.com>
  19             Anna Tikhonova  <anna.tikhonova@intel.com>
  20             Ilya Tocar  <ilya.tocar@intel.com>
  21             Andrey Turetskiy  <andrey.turetskiy@intel.com>
  22             Ilya Verbin  <ilya.verbin@intel.com>
  23             Kirill Yukhin  <kirill.yukhin@intel.com>
  24             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
  25
  26         * i386-dis-evex.h: New.
  27         * i386-dis.c (OP_Rounding): New.
  28         (VPCMP_Fixup): New.
  29         (OP_Mask): New.
  30         (Rdq): New.
  31         (XMxmmq): New.
  32         (EXdScalarS): New.
  33         (EXymm): New.
  34         (EXEvexHalfBcstXmmq): New.
  35         (EXxmm_mdq): New.
  36         (EXEvexXGscat): New.
  37         (EXEvexXNoBcst): New.
  38         (VPCMP): New.
  39         (EXxEVexR): New.
  40         (EXxEVexS): New.
  41         (XMask): New.
  42         (MaskG): New.
  43         (MaskE): New.
  44         (MaskR): New.
  45         (MaskVex): New.
  46         (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
  47         evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
  48         evex_rounding_mode, evex_sae_mode, mask_mode.
  49         (USE_EVEX_TABLE): New.
  50         (EVEX_TABLE): New.
  51         (EVEX enum): New.
  52         (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
  53         REG_EVEX_0F38C7.
  54         (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
  55         MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
  56         MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
  57         MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
  58         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,  MOD_EVEX_0F38C7_REG_5,
  59         MOD_EVEX_0F38C7_REG_6.
  60         (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
  61         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
  62         PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
  63         PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
  64         PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
  65         PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
  66         PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
  67         PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
  68         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
  69         PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
  70         PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
  71         PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
  72         PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
  73         PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
  74         PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
  75         PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
  76         PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
  77         PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
  78         PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
  79         PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
  80         PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
  81         PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
  82         PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
  83         PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
  84         PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
  85         PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
  86         PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
  87         PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
  88         PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
  89         PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
  90         PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
  91         PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
  92         PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
  93         PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
  94         PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
  95         PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
  96         PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
  97         PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
  98         PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
  99         PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
 100         PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
 101         PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
 102         PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
 103         PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
 104         PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
 105         PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
 106         PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
 107         PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
 108         PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
 109         PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
 110         PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
 111         PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
 112         PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
 113         PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
 114         PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
 115         PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
 116         PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
 117         PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
 118         PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
 119         PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
 120         PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
 121         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
 122         PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
 123         PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
 124         PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
 125         PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
 126         PREFIX_EVEX_0F3A00,  PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
 127         PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
 128         PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
 129         PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
 130         PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
 131         PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
 132         PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
 133         PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
 134         PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
 135         PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
 136         PREFIX_EVEX_0F3A55.
 137         (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
 138         VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
 139         VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
 140         VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
 141         VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
 142         VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
 143         VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
 144         VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
 145         VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
 146         VEX_W_0F3A32_P_2_LEN_0.
 147         (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
 148         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
 149         EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
 150         EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
 151         EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
 152         EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 153         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
 154         EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
 155         EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 156         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
 157         EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 158         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
 159         EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
 160         EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
 161         EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
 162         EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
 163         EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
 164         EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
 165         EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
 166         EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
 167         EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
 168         EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
 169         EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
 170         EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
 171         EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
 172         EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
 173         EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
 174         EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
 175         EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
 176         EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
 177         EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
 178         EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
 179         EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
 180         EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
 181         EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
 182         EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
 183         EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
 184         EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
 185         EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
 186         EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
 187         EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
 188         EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
 189         EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
 190         EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
 191         EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
 192         EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
 193         EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
 194         EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
 195         EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
 196         EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
 197         EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
 198         EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
 199         EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
 200         EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
 201         (struct vex): Add fields evex, r, v, mask_register_specifier,
 202         zeroing, ll, b.
 203         (intel_names_xmm): Add upper 16 registers.
 204         (att_names_xmm): Ditto.
 205         (intel_names_ymm): Ditto.
 206         (att_names_ymm): Ditto.
 207         (names_zmm): New.
 208         (intel_names_zmm): Ditto.
 209         (att_names_zmm): Ditto.
 210         (names_mask): Ditto.
 211         (intel_names_mask): Ditto.
 212         (att_names_mask): Ditto.
 213         (names_rounding): Ditto.
 214         (names_broadcast): Ditto.
 215         (x86_64_table): Add escape to evex-table.
 216         (reg_table): Include reg_table evex-entries from
 217         i386-dis-evex.h.  Fix prefetchwt1 instruction.
 218         (prefix_table): Add entries for new instructions.
 219         (vex_table): Ditto.
 220         (vex_len_table): Ditto.
 221         (vex_w_table): Ditto.
 222         (mod_table): Ditto.
 223         (get_valid_dis386): Properly handle new instructions.
 224         (print_insn): Handle zmm and mask registers, print mask operand.
 225         (intel_operand_size): Support EVEX, new modes and sizes.
 226         (OP_E_register): Handle new modes.
 227         (OP_E_memory): Ditto.
 228         (OP_G): Ditto.
 229         (OP_XMM): Ditto.
 230         (OP_EX): Ditto.
 231         (OP_VEX): Ditto.
 232         * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
 233         CPU_ANY_AVX_FLAGS.  Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
 234         CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 235         (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
 236         CpuAVX512PF and CpuVREX.
 237         (operand_type_init): Add OPERAND_TYPE_REGZMM,
 238         OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
 239         (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
 240         StaticRounding, SAE, Disp8MemShift, NoDefMask.
 241         (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
 242         * i386-init.h: Regenerate.
 243         * i386-opc.h (CpuAVX512F): New.
 244         (CpuAVX512CD): New.
 245         (CpuAVX512ER): New.
 246         (CpuAVX512PF): New.
 247         (CpuVREX): New.
 248         (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
 249         cpuavx512pf and cpuvrex fields.
 250         (VecSIB): Add VecSIB512.
 251         (EVex): New.
 252         (Masking): New.
 253         (VecESize): New.
 254         (Broadcast): New.
 255         (StaticRounding): New.
 256         (SAE): New.
 257         (Disp8MemShift): New.
 258         (NoDefMask): New.
 259         (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
 260         staticrounding, sae, disp8memshift and nodefmask.
 261         (RegZMM): New.
 262         (Zmmword): Ditto.
 263         (Vec_Disp8): Ditto.
 264         (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
 265         fields.
 266         (RegVRex): New.
 267         * i386-opc.tbl: Add AVX512 instructions.
 268         * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
 269         registers, mask registers.
 270         * i386-tbl.h: Regenerate.
 271
 272 2013-07-25  Aaro Koskinen  <aaro.koskinen@iki.fi>
 273
 274         PR gas/15220
 275         * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
 276         Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
 277
 278 2013-07-25  Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 279
 280         * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
 281         PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
 282         PREFIX_0F3ACC.
 283         (prefix_table): Updated.
 284         (three_byte_table): Likewise.
 285         * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
 286         (cpu_flags): Add CpuSHA.
 287         (i386_cpu_flags): Add cpusha.
 288         * i386-init.h: Regenerate.
 289         * i386-opc.h (CpuSHA): New.
 290         (CpuUnused): Restored.
 291         (i386_cpu_flags): Add cpusha.
 292         * i386-opc.tbl: Add SHA instructions.
 293         * i386-tbl.h: Regenerate.
 294
 295 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
 296             Kirill Yukhin  <kirill.yukhin@intel.com>
 297             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 298
 299         * i386-dis.c (BND_Fixup): New.
 300         (Ebnd): New.
 301         (Ev_bnd): New.
 302         (Gbnd): New.
 303         (BND): New.
 304         (v_bnd_mode): New.
 305         (bnd_mode): New.
 306         (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
 307         MOD_0F1B_PREFIX_1.
 308         (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
 309         (dis tables): Replace XX with BND for near branch and call
 310         instructions.
 311         (prefix_table): Add new entries.
 312         (mod_table): Likewise.
 313         (names_bnd): New.
 314         (intel_names_bnd): New.
 315         (att_names_bnd): New.
 316         (BND_PREFIX): New.
 317         (prefix_name): Handle BND_PREFIX.
 318         (print_insn): Initialize names_bnd.
 319         (intel_operand_size): Handle new modes.
 320         (OP_E_register): Likewise.
 321         (OP_E_memory): Likewise.
 322         (OP_G): Likewise.
 323         * i386-gen.c (cpu_flag_init): Add CpuMPX.
 324         (cpu_flags): Add CpuMPX.
 325         (operand_type_init): Add RegBND.
 326         (opcode_modifiers): Add BNDPrefixOk.
 327         (operand_types): Add RegBND.
 328         * i386-init.h: Regenerate.
 329         * i386-opc.h (CpuMPX): New.
 330         (CpuUnused): Comment out.
 331         (i386_cpu_flags): Add cpumpx.
 332         (BNDPrefixOk): New.
 333         (i386_opcode_modifier): Add bndprefixok.
 334         (RegBND): New.
 335         (i386_operand_type): Add regbnd.
 336         * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
 337         Add MPX instructions and bnd prefix.
 338         * i386-reg.tbl: Add bnd0-bnd3 registers.
 339         * i386-tbl.h: Regenerate.
 340
 341 2013-07-17  Richard Sandiford  <rdsandiford@googlemail.com>
 342
 343         * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
 344         ATTRIBUTE_UNUSED.
 345
 346 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 347
 348         * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
 349         special rules.
 350         * Makefile.in: Regenerate.
 351         * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
 352         all fields.  Reformat.
 353
 354 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 355
 356         * mips16-opc.c: Include mips-formats.h.
 357         (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
 358         static arrays.
 359         (decode_mips16_operand): New function.
 360         * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
 361         (print_insn_arg): Handle OP_ENTRY_EXIT list.
 362         Abort for OP_SAVE_RESTORE_LIST.
 363         (print_mips16_insn_arg): Change interface.  Use mips_operand
 364         structures.  Delete GET_OP_S.  Move GET_OP definition to...
 365         (print_insn_mips16): ...here.  Call init_print_arg_state.
 366         Update the call to print_mips16_insn_arg.
 367
 368 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 369
 370         * mips-formats.h: New file.
 371         * mips-opc.c: Include mips-formats.h.
 372         (reg_0_map): New static array.
 373         (decode_mips_operand): New function.
 374         * micromips-opc.c: Remove <stdio.h> include.  Include mips-formats.h.
 375         (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
 376         (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
 377         (int_c_map): New static arrays.
 378         (decode_micromips_operand): New function.
 379         * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
 380         (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
 381         (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
 382         (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
 383         (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
 384         (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
 385         (micromips_imm_b_map, micromips_imm_c_map): Delete.
 386         (print_reg): New function.
 387         (mips_print_arg_state): New structure.
 388         (init_print_arg_state, print_insn_arg): New functions.
 389         (print_insn_args): Change interface and use mips_operand structures.
 390         Delete GET_OP_S.  Move GET_OP definition to...
 391         (print_insn_mips): ...here.  Update the call to print_insn_args.
 392         (print_insn_micromips): Use print_insn_args.
 393
 394 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 395
 396         * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
 397         in macros.
 398
 399 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 400
 401         * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
 402         ADDA.S, MULA.S and SUBA.S.
 403
 404 2013-07-08  H.J. Lu  <hongjiu.lu@intel.com>
 405
 406         PR gas/13572
 407         * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
 408         * i386-tbl.h: Regenerated.
 409
 410 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 411
 412         * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros.  Move LD
 413         and SD A(B) macros up.
 414         * micromips-opc.c (micromips_opcodes): Likewise.
 415
 416 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 417
 418         * mips16-opc.c: Add entries for argumentless "entry" and "exit"
 419         instructions.
 420
 421 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 422
 423         * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
 424         MDMX-like instructions.
 425         * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
 426         printing "Q" operands for INSN_5400 instructions.
 427
 428 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 429
 430         * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
 431         "+S" for "cins".
 432         * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
 433         Combine cases.
 434
 435 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 436
 437         * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
 438         "jalx".
 439         * mips16-opc.c (mips16_opcodes): Likewise.
 440         * micromips-opc.c (micromips_opcodes): Likewise.
 441         * mips-dis.c (print_insn_args, print_mips16_insn_arg)
 442         (print_insn_mips16): Handle "+i".
 443         (print_insn_micromips): Likewise.  Conditionally preserve the
 444         ISA bit for "a" but not for "+i".
 445
 446 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 447
 448         * micromips-opc.c (WR_mhi): Rename to..
 449         (WR_mh): ...this.
 450         (micromips_opcodes): Update "movep" entry accordingly.  Replace
 451         "mh,mi" with "mh".
 452         * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
 453         (micromips_to_32_reg_h_map1): ...this.
 454         (micromips_to_32_reg_i_map): Rename to...
 455         (micromips_to_32_reg_h_map2): ...this.
 456         (print_micromips_insn): Remove "mi" case.  Print both registers
 457         in the pair for "mh".
 458
 459 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 460
 461         * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
 462         * micromips-opc.c (micromips_opcodes): Likewise.
 463         * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
 464         and "+T" handling.  Check for a "0" suffix when deciding whether to
 465         use coprocessor 0 names.  In that case, also check for ",H" selectors.
 466
 467 2013-07-05  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 468
 469         * s390-opc.c (J12_12, J24_24): New macros.
 470         (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
 471         (MASK_MII_UPI): Rename to MASK_MII_UPP.
 472         * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
 473
 474 2013-07-04  Alan Modra  <amodra@gmail.com>
 475
 476         * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
 477
 478 2013-06-26  Nick Clifton  <nickc@redhat.com>
 479
 480         * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
 481         field when checking for type 2 nop.
 482         * rx-decode.c: Regenerate.
 483
 484 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
 485
 486         * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
 487         and "movep" macros.
 488
 489 2013-06-24  Maciej W. Rozycki  <macro@codesourcery.com>
 490
 491         * mips-dis.c (is_mips16_plt_tail): New function.
 492         (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
 493         word.
 494         (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
 495
 496 2013-06-21  DJ Delorie  <dj@redhat.com>
 497
 498         * msp430-decode.opc: New.
 499         * msp430-decode.c: New/generated.
 500         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
 501         (MAINTAINER_CLEANFILES): Likewise.
 502         Add rule to build msp430-decode.c frommsp430decode.opc
 503         using the opc2c program.
 504         * Makefile.in: Regenerate.
 505         * configure.in: Add msp430-decode.lo to msp430 architecture files.
 506         * configure: Regenerate.
 507
 508 2013-06-20  Yufeng Zhang  <yufeng.zhang@arm.com>
 509
 510         * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
 511         (SYMTAB_AVAILABLE): Removed.
 512         (#include "elf/aarch64.h): Ditto.
 513
 514 2013-06-17  Catherine Moore  <clm@codesourcery.com>
 515             Maciej W. Rozycki  <macro@codesourcery.com>
 516             Chao-Ying Fu  <fu@mips.com>
 517
 518         * micromips-opc.c (EVA): Define.
 519         (TLBINV): Define.
 520         (micromips_opcodes): Add EVA opcodes.
 521         * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
 522         (print_insn_args): Handle EVA offsets.
 523         (print_insn_micromips): Likewise.
 524         * mips-opc.c (EVA): Define.
 525         (TLBINV): Define.
 526         (mips_builtin_opcodes): Add EVA opcodes.
 527
 528 2013-06-17  Alan Modra  <amodra@gmail.com>
 529
 530         * Makefile.am (mips-opc.lo): Add rules to create automatic
 531         dependency files.  Pass archdefs.
 532         (micromips-opc.lo, mips16-opc.lo): Likewise.
 533         * Makefile.in: Regenerate.
 534
 535 2013-06-14  DJ Delorie  <dj@redhat.com>
 536
 537         * rx-decode.opc (rx_decode_opcode): Bit operations on
 538         registers are 32-bit operations, not 8-bit operations.
 539         * rx-decode.c: Regenerate.
 540
 541 2013-06-13  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 542
 543         * micromips-opc.c (IVIRT): New define.
 544         (IVIRT64): New define.
 545         (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 546         tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
 547
 548         * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
 549         dmtgc0 to print cp0 names.
 550
 551 2013-06-09  Sandra Loosemore  <sandra@codesourcery.com>
 552
 553         * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
 554         argument.
 555
 556 2013-06-08  Catherine Moore  <clm@codesourcery.com>
 557             Richard Sandiford  <rdsandiford@googlemail.com>
 558
 559         * micromips-opc.c (D32, D33, MC): Update definitions.
 560         (micromips_opcodes):  Initialize ase field.
 561         * mips-dis.c (mips_arch_choice): Add ase field.
 562         (mips_arch_choices): Initialize ase field.
 563         (set_default_mips_dis_options): Declare and setup mips_ase.
 564         * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
 565         MT32, MC): Update definitions.
 566         (mips_builtin_opcodes): Initialize ase field.
 567
 568 2013-05-24  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 569
 570         * s390-opc.txt (flogr): Require a register pair destination.
 571
 572 2013-05-23  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 573
 574         * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
 575         instruction format.
 576
 577 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 578
 579         * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
 580
 581 2013-05-20  Peter Bergner <bergner@vnet.ibm.com>
 582
 583         * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
 584         * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
 585         XLS_MASK, PPCVSX2): New defines.
 586         (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
 587         fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
 588         mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
 589         mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
 590         mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
 591         vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
 592         vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
 593         vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
 594         vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
 595         vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
 596         vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
 597         vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
 598         vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
 599         vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
 600         xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
 601         xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
 602         xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
 603         xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
 604         <lxvx, stxvx>: New extended mnemonics.
 605
 606 2013-05-17  Alan Modra  <amodra@gmail.com>
 607
 608         * ia64-raw.tbl: Replace non-ASCII char.
 609         * ia64-waw.tbl: Likewise.
 610         * ia64-asmtab.c: Regenerate.
 611
 612 2013-05-15  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 613
 614         * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
 615         * i386-init.h: Regenerated.
 616
 617 2013-05-13  Yufeng Zhang  <yufeng.zhang@arm.com>
 618
 619         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
 620         * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
 621         check from [0, 255] to [-128, 255].
 622
 623 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 624
 625         * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
 626         Add INSN_VIRT and INSN_VIRT64 to mips64r2.
 627         (parse_mips_dis_option): Handle the virt option.
 628         (print_insn_args): Handle "+J".
 629         (print_mips_disassembler_options): Print out message about virt64.
 630         * mips-opc.c (IVIRT): New define.
 631         (IVIRT64): New define.
 632         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 633         tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
 634         Move rfe to the bottom as it conflicts with tlbgp.
 635
 636 2013-05-09  Alan Modra  <amodra@gmail.com>
 637
 638         * ppc-opc.c (extract_vlesi): Properly sign extend.
 639         (extract_vlensi): Likewise.  Comment reason for setting invalid.
 640
 641 2013-05-02  Nick Clifton  <nickc@redhat.com>
 642
 643         * msp430-dis.c: Add support for MSP430X instructions.
 644
 645 2013-04-24  Sandra Loosemore  <sandra@codesourcery.com>
 646
 647         * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
 648         to "eccinj".
 649
 650 2013-04-17  Wei-chen Wang  <cole945@gmail.com>
 651
 652         PR binutils/15369
 653         * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
 654         of CGEN_CPU_ENDIAN.
 655         (hash_insns_list): Likewise.
 656
 657 2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>
 658
 659         * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
 660         warning workaround.
 661
 662 2013-04-08  Jan Beulich <jbeulich@suse.com>
 663
 664         * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
 665         * i386-tbl.h: Re-generate.
 666
 667 2013-04-06  David S. Miller  <davem@davemloft.net>
 668
 669         * sparc-dis.c (compare_opcodes): When encountering multiple aliases
 670         of an opcode, prefer the one with F_PREFERRED set.
 671         * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
 672         lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
 673         ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
 674         mark existing mnenomics as aliases.  Add "cc" suffix to edge
 675         instructions generating condition codes, mark existing mnenomics
 676         as aliases.  Add "fp" prefix to VIS compare instructions, mark
 677         existing mnenomics as aliases.
 678
 679 2013-04-03  Nick Clifton  <nickc@redhat.com>
 680
 681         * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
 682         destination address by subtracting the operand from the current
 683         address.
 684         * v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
 685         a positive value in the insn.
 686         (extract_u16_loop): Do not negate the returned value.
 687         (D16_LOOP): Add V850_INVERSE_PCREL flag.
 688
 689         (ceilf.sw): Remove duplicate entry.
 690         (cvtf.hs): New entry.
 691         (cvtf.sh): Likewise.
 692         (fmaf.s): Likewise.
 693         (fmsf.s): Likewise.
 694         (fnmaf.s): Likewise.
 695         (fnmsf.s): Likewise.
 696         (maddf.s): Restrict to E3V5 architectures.
 697         (msubf.s): Likewise.
 698         (nmaddf.s): Likewise.
 699         (nmsubf.s): Likewise.
 700
 701 2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>
 702
 703         * i386-dis.c (get_sib): Add the sizeflag argument.  Properly
 704         check address mode.
 705         (print_insn): Pass sizeflag to get_sib.
 706
 707 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 708
 709         PR binutils/15068
 710         * tic6x-dis.c: Add support for displaying 16-bit insns.
 711
 712 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 713
 714         PR gas/15095
 715         * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
 716         individual msb and lsb halves in src1 & src2 fields.  Discard the
 717         src1 (lsb) value and only use src2 (msb), discarding bit 0, to
 718         follow what Ti SDK does in that case as any value in the src1
 719         field yields the same output with SDK disassembler.
 720
 721 2013-03-12  Michael Eager <eager@eagercon.com>
 722
 723         * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
 724
 725 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 726
 727         * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
 728
 729 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 730
 731         * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
 732
 733 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 734
 735         * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
 736
 737 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 738
 739         * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
 740         (thumb32_opcodes): Likewise.
 741         (print_insn_thumb32): Handle 'S' control char.
 742
 743 2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
 744
 745         * lm32-desc.c: Regenerate.
 746
 747 2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 748
 749         * i386-reg.tbl (riz): Add RegRex64.
 750         * i386-tbl.h: Regenerated.
 751
 752 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 753
 754         * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
 755         (aarch64_feature_crc): New static.
 756         (CRC): New macro.
 757         (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
 758         crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
 759         * aarch64-asm-2.c: Re-generate.
 760         * aarch64-dis-2.c: Ditto.
 761         * aarch64-opc-2.c: Ditto.
 762
 763 2013-02-27  Alan Modra  <amodra@gmail.com>
 764
 765         * rl78-decode.opc (rl78_decode_opcode): Fix typo.
 766         * rl78-decode.c: Regenerate.
 767
 768 2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
 769
 770         * rl78-decode.opc: Fix encoding of DIVWU insn.
 771         * rl78-decode.c: Regenerate.
 772
 773 2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 774
 775         PR gas/15159
 776         * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
 777
 778         * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
 779         (cpu_flags): Add CpuSMAP.
 780
 781         * i386-opc.h (CpuSMAP): New.
 782         (i386_cpu_flags): Add cpusmap.
 783
 784         * i386-opc.tbl: Add clac and stac.
 785
 786         * i386-init.h: Regenerated.
 787         * i386-tbl.h: Likewise.
 788
 789 2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
 790
 791         * metag-dis.c: Initialize outf->bytes_per_chunk to 4
 792         which also makes the disassembler output be in little
 793         endian like it should be.
 794
 795 2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
 796
 797         * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
 798         fields to NULL.
 799         (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
 800
 801 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
 802
 803         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
 804         section disassembled.
 805
 806 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 807
 808         * arm-dis.c: Update strht pattern.
 809
 810 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
 811
 812         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
 813         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
 814         trunc.w.s macro for EE.
 815
 816 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
 817             Andrew Jenner <andrew@codesourcery.com>
 818
 819         Based on patches from Altera Corporation.
 820
 821         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
 822         nios2-opc.c.
 823         * Makefile.in: Regenerated.
 824         * configure.in: Add case for bfd_nios2_arch.
 825         * configure: Regenerated.
 826         * disassemble.c (ARCH_nios2): Define.
 827         (disassembler): Add case for bfd_arch_nios2.
 828         * nios2-dis.c: New file.
 829         * nios2-opc.c: New file.
 830
 831 2013-02-04  Alan Modra  <amodra@gmail.com>
 832
 833         * po/POTFILES.in: Regenerate.
 834         * rl78-decode.c: Regenerate.
 835         * rx-decode.c: Regenerate.
 836
 837 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
 838
 839         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
 840         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
 841         * aarch64-asm.c (convert_xtl_to_shll): New function.
 842         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 843         calling convert_xtl_to_shll.
 844         * aarch64-dis.c (convert_shll_to_xtl): New function.
 845         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 846         calling convert_shll_to_xtl.
 847         * aarch64-gen.c: Update copyright year.
 848         * aarch64-asm-2.c: Re-generate.
 849         * aarch64-dis-2.c: Re-generate.
 850         * aarch64-opc-2.c: Re-generate.
 851
 852 2013-01-24  Nick Clifton  <nickc@redhat.com>
 853
 854         * v850-dis.c: Add support for e3v5 architecture.
 855         * v850-opc.c: Likewise.
 856
 857 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 858
 859         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
 860         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
 861         * aarch64-opc.c (operand_general_constraint_met_p): For
 862         AARCH64_MOD_LSL, move the range check on the shift amount before the
 863         alignment check; change to call set_sft_amount_out_of_range_error
 864         instead of set_imm_out_of_range_error.
 865         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
 866         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
 867         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
 868         SIMD_IMM_SFT.
 869
 870 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
 871
 872         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
 873
 874         * i386-init.h: Regenerated.
 875         * i386-tbl.h: Likewise.
 876
 877 2013-01-15  Nick Clifton  <nickc@redhat.com>
 878
 879         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
 880         values.
 881         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
 882
 883 2013-01-14  Will Newton <will.newton@imgtec.com>
 884
 885         * metag-dis.c (REG_WIDTH): Increase to 64.
 886
 887 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
 888
 889         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
 890         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
 891         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
 892         (SH6): Update.
 893         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
 894         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
 895         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
 896         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
 897
 898 2013-01-10  Will Newton <will.newton@imgtec.com>
 899
 900         * Makefile.am: Add Meta.
 901         * configure.in: Add Meta.
 902         * disassemble.c: Add Meta support.
 903         * metag-dis.c: New file.
 904         * Makefile.in: Regenerate.
 905         * configure: Regenerate.
 906
 907 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 908
 909         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
 910         (match_opcode): Rename to cr16_match_opcode.
 911
 912 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
 913
 914         * mips-dis.c: Add names for CP0 registers of r5900.
 915         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
 916         instructions sq and lq.
 917         Add support for MIPS r5900 CPU.
 918         Add support for 128 bit MMI (Multimedia Instructions).
 919         Add support for EE instructions (Emotion Engine).
 920         Disable unsupported floating point instructions (64 bit and
 921         undefined compare operations).
 922         Enable instructions of MIPS ISA IV which are supported by r5900.
 923         Disable 64 bit co processor instructions.
 924         Disable 64 bit multiplication and division instructions.
 925         Disable instructions for co-processor 2 and 3, because these are
 926         not supported (preparation for later VU0 support (Vector Unit)).
 927         Disable cvt.w.s because this behaves like trunc.w.s and the
 928         correct execution can't be ensured on r5900.
 929         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
 930         will confuse less developers and compilers.
 931
 932 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 933
 934         * aarch64-opc.c (aarch64_print_operand): Change to print
 935         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
 936         in comment.
 937         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
 938         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
 939         OP_MOV_IMM_WIDE.
 940
 941 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 942
 943         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
 944         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
 945
 946 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
 947
 948         * i386-gen.c (process_copyright): Update copyright year to 2013.
 949
 950 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 951
 952         * cr16-dis.c (match_opcode,make_instruction): Remove static
 953         declaration.
 954         (dwordU,wordU): Moved typedefs to opcode/cr16.h
 955         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
 956
 957 For older changes see ChangeLog-2012
 958 \f
 959 Copyright (C) 2013 Free Software Foundation, Inc.
 960
 961 Copying and distribution of this file, with or without modification,
 962 are permitted in any medium without royalty provided the copyright
 963 notice and this notice are preserved.
 964
 965 Local Variables:
 966 mode: change-log
 967 left-margin: 8
 968 fill-column: 74
 969 version-control: never
 970 End: