1 2015-10-27 Vinay Kumar <vinay.g@kpit.com>
4 * rl78-decode.opc: Add 's' print operator to instructions that
5 access system registers.
6 * rl78-decode.c: Regenerate.
7 * rl78-dis.c (print_insn_rl78_common): Decode all system
10 2015-10-27 Vinay Kumar <vinay.g@kpit.com>
13 * rl78-decode.opc: Add 'a' print operator to mov instructions
14 using stack pointer plus index addressing.
15 * rl78-decode.c: Regenerate.
17 2015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
19 * s390-opc.c: Fix comment.
20 * s390-opc.txt: Change instruction type for troo, trot, trto, and
21 trtt to RRF_U0RER since the second parameter does not need to be a
24 2015-10-08 Nick Clifton <nickc@redhat.com>
26 * arc-dis.c (print_insn_arc): Initiallise insn array.
28 2015-10-07 Yao Qi <yao.qi@linaro.org>
30 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
31 'name' rather than 'template'.
32 * aarch64-opc.c (aarch64_print_operand): Likewise.
34 2015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
36 * arc-dis.c: Revamped file for ARC support
37 * arc-dis.h: Likewise.
38 * arc-ext.c: Likewise.
39 * arc-ext.h: Likewise.
40 * arc-opc.c: Likewise.
41 * arc-fxi.h: New file.
42 * arc-regs.h: Likewise.
43 * arc-tbl.h: Likewise.
45 2015-10-02 Yao Qi <yao.qi@linaro.org>
47 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
48 argument insn type to aarch64_insn. Rename to ...
49 (aarch64_decode_insn): ... it.
50 (print_insn_aarch64_word): Caller updated.
52 2015-10-02 Yao Qi <yao.qi@linaro.org>
54 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
55 (print_insn_aarch64_word): Caller updated.
57 2015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
59 * s390-mkopc.c (main): Parse htm and vx flag.
60 * s390-opc.txt: Mark instructions from the hardware transactional
61 memory and vector facilities with the "htm"/"vx" flag.
63 2015-09-28 Nick Clifton <nickc@redhat.com>
65 * po/de.po: Updated German translation.
67 2015-09-28 Tom Rix <tom@bumblecow.com>
69 * ppc-opc.c (PPC500): Mark some opcodes as invalid
71 2015-09-23 Nick Clifton <nickc@redhat.com>
73 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
75 * tic30-dis.c (print_branch): Likewise.
76 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
77 value before left shifting.
78 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
79 * hppa-dis.c (print_insn_hppa): Likewise.
80 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
82 * msp430-dis.c (msp430_singleoperand): Likewise.
83 (msp430_doubleoperand): Likewise.
84 (print_insn_msp430): Likewise.
85 * nds32-asm.c (parse_operand): Likewise.
86 * sh-opc.h (MASK): Likewise.
87 * v850-dis.c (get_operand_value): Likewise.
89 2015-09-22 Nick Clifton <nickc@redhat.com>
91 * rx-decode.opc (bwl): Use RX_Bad_Size.
93 (ubwl): Likewise. Rename to ubw.
94 (uBWL): Rename to uBW.
95 Replace all references to uBWL with uBW.
96 * rx-decode.c: Regenerate.
97 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
98 (opsize_names): Likewise.
99 (print_insn_rx): Detect and report RX_Bad_Size.
101 2015-09-22 Anton Blanchard <anton@samba.org>
103 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
105 2015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
107 * sparc-dis.c (print_insn_sparc): Handle the privileged register
110 2015-08-24 Jan Stancek <jstancek@redhat.com>
112 * i386-dis.c (print_insn): Fix decoding of three byte operands.
114 2015-08-21 Alexander Fomin <alexander.fomin@intel.com>
117 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
118 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
119 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
120 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
121 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
122 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
123 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
124 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
125 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
126 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
127 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
128 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
129 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
130 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
131 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
132 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
133 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
134 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
135 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
136 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
137 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
138 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
139 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
140 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
141 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
142 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
143 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
144 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
145 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
146 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
147 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
148 (vex_w_table): Replace terminals with MOD_TABLE entries for
149 most of mask instructions.
151 2015-08-17 Alan Modra <amodra@gmail.com>
153 * cgen.sh: Trim trailing space from cgen output.
154 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
155 (print_dis_table): Likewise.
156 * opc2c.c (dump_lines): Likewise.
157 (orig_filename): Warning fix.
158 * ia64-asmtab.c: Regenerate.
160 2015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
162 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
163 and higher with ARM instruction set will now mark the 26-bit
164 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
165 (arm_opcodes): Fix for unpredictable nop being recognized as a
168 2015-08-12 Simon Dardis <simon.dardis@imgtec.com>
170 * micromips-opc.c (micromips_opcodes): Re-order table so that move
171 based on 'or' is first.
172 * mips-opc.c (mips_builtin_opcodes): Ditto.
174 2015-08-11 Nick Clifton <nickc@redhat.com>
177 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
180 2015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
182 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
184 2015-08-07 Amit Pawar <Amit.Pawar@amd.com>
186 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
187 * i386-init.h: Regenerated.
189 2015-07-30 H.J. Lu <hongjiu.lu@intel.com>
192 * i386-dis.c (MOD_0FC3): New.
193 (PREFIX_0FC3): Renamed to ...
194 (PREFIX_MOD_0_0FC3): This.
195 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
196 (prefix_table): Replace Ma with Ev on movntiS.
197 (mod_table): Add MOD_0FC3.
199 2015-07-27 H.J. Lu <hongjiu.lu@intel.com>
201 * configure: Regenerated.
203 2015-07-23 Alan Modra <amodra@gmail.com>
206 * i386-dis.c (get64): Avoid signed integer overflow.
208 2015-07-22 Alexander Fomin <alexander.fomin@intel.com>
211 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
212 "EXEvexHalfBcstXmmq" for the second operand.
213 (EVEX_W_0F79_P_2): Likewise.
214 (EVEX_W_0F7A_P_2): Likewise.
215 (EVEX_W_0F7B_P_2): Likewise.
217 2015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
219 * arm-dis.c (print_insn_coprocessor): Added support for quarter
220 float bitfield format.
221 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
222 quarter float bitfield format.
224 2015-07-14 H.J. Lu <hongjiu.lu@intel.com>
226 * configure: Regenerated.
228 2015-07-03 Alan Modra <amodra@gmail.com>
230 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
231 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
232 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
234 2015-07-01 Sandra Loosemore <sandra@codesourcery.com>
235 Cesar Philippidis <cesar@codesourcery.com>
237 * nios2-dis.c (nios2_extract_opcode): New.
238 (nios2_disassembler_state): New.
239 (nios2_find_opcode_hash): Use mach parameter to select correct
241 (nios2_print_insn_arg): Extend to support new R2 argument letters
243 (print_insn_nios2): Check for 16-bit instruction at end of memory.
244 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
245 (NIOS2_NUM_OPCODES): Rename to...
246 (NIOS2_NUM_R1_OPCODES): This.
247 (nios2_r2_opcodes): New.
248 (NIOS2_NUM_R2_OPCODES): New.
249 (nios2_num_r2_opcodes): New.
250 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
251 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
252 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
253 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
254 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
256 2015-06-30 Amit Pawar <Amit.Pawar@amd.com>
258 * i386-dis.c (OP_Mwaitx): New.
259 (rm_table): Add monitorx/mwaitx.
260 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
261 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
262 (operand_type_init): Add CpuMWAITX.
263 * i386-opc.h (CpuMWAITX): New.
264 (i386_cpu_flags): Add cpumwaitx.
265 * i386-opc.tbl: Add monitorx and mwaitx.
266 * i386-init.h: Regenerated.
267 * i386-tbl.h: Likewise.
269 2015-06-22 Peter Bergner <bergner@vnet.ibm.com>
271 * ppc-opc.c (insert_ls): Test for invalid LS operands.
272 (insert_esync): New function.
273 (LS, WC): Use insert_ls.
274 (ESYNC): Use insert_esync.
276 2015-06-22 Nick Clifton <nickc@redhat.com>
278 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
279 requested region lies beyond it.
280 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
281 looking for 32-bit insns.
282 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
284 * sh-dis.c (print_insn_sh): Likewise.
285 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
286 blocks of instructions.
287 * vax-dis.c (print_insn_vax): Check that the requested address
288 does not clash with the stop_vma.
290 2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
292 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
293 * ppc-opc.c (FXM4): Add non-zero optional value.
296 (insert_fxm): Handle new default operand value.
297 (extract_fxm): Likewise.
298 (insert_tbr): Likewise.
299 (extract_tbr): Likewise.
301 2015-06-16 Matthew Wahab <matthew.wahab@arm.com>
303 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
305 2015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
307 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
309 2015-06-12 Peter Bergner <bergner@vnet.ibm.com>
311 * ppc-opc.c: Add comment accidentally removed by old commit.
314 2015-06-04 Peter Bergner <bergner@vnet.ibm.com>
316 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
318 2015-06-04 Nick Clifton <nickc@redhat.com>
321 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
323 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
325 * arm-dis.c (arm_opcodes): Add "setpan".
326 (thumb_opcodes): Add "setpan".
328 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
330 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
333 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
335 * aarch64-tbl.h (aarch64_feature_rdma): New.
337 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
338 * aarch64-asm-2.c: Regenerate.
339 * aarch64-dis-2.c: Regenerate.
340 * aarch64-opc-2.c: Regenerate.
342 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
344 * aarch64-tbl.h (aarch64_feature_lor): New.
346 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
348 * aarch64-asm-2.c: Regenerate.
349 * aarch64-dis-2.c: Regenerate.
350 * aarch64-opc-2.c: Regenerate.
352 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
354 * aarch64-opc.c (F_ARCHEXT): New.
355 (aarch64_sys_regs): Add "pan".
356 (aarch64_sys_reg_supported_p): New.
357 (aarch64_pstatefields): Add "pan".
358 (aarch64_pstatefield_supported_p): New.
360 2015-06-01 Jan Beulich <jbeulich@suse.com>
362 * i386-tbl.h: Regenerate.
364 2015-06-01 Jan Beulich <jbeulich@suse.com>
366 * i386-dis.c (print_insn): Swap rounding mode specifier and
367 general purpose register in Intel mode.
369 2015-06-01 Jan Beulich <jbeulich@suse.com>
371 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
372 * i386-tbl.h: Regenerate.
374 2015-05-18 H.J. Lu <hongjiu.lu@intel.com>
376 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
377 * i386-init.h: Regenerated.
379 2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
382 * i386-dis.c: Add comments for '@'.
383 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
384 (enum x86_64_isa): New.
386 (print_i386_disassembler_options): Add amd64 and intel64.
387 (print_insn): Handle amd64 and intel64.
389 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
390 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
391 * i386-opc.h (AMD64): New.
392 (CpuIntel64): Likewise.
393 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
394 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
395 Mark direct call/jmp without Disp16|Disp32 as Intel64.
396 * i386-init.h: Regenerated.
397 * i386-tbl.h: Likewise.
399 2015-05-14 Peter Bergner <bergner@vnet.ibm.com>
401 * ppc-opc.c (IH) New define.
402 (powerpc_opcodes) <wait>: Do not enable for POWER7.
403 <tlbie>: Add RS operand for POWER7.
404 <slbia>: Add IH operand for POWER6.
406 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
408 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
411 * i386-tbl.h: Regenerated.
413 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
415 * configure.ac: Support bfd_iamcu_arch.
416 * disassemble.c (disassembler): Support bfd_iamcu_arch.
417 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
418 CPU_IAMCU_COMPAT_FLAGS.
419 (cpu_flags): Add CpuIAMCU.
420 * i386-opc.h (CpuIAMCU): New.
421 (i386_cpu_flags): Add cpuiamcu.
422 * configure: Regenerated.
423 * i386-init.h: Likewise.
424 * i386-tbl.h: Likewise.
426 2015-05-08 H.J. Lu <hongjiu.lu@intel.com>
429 * i386-dis.c (X86_64_E8): New.
430 (X86_64_E9): Likewise.
431 Update comments on 'T', 'U', 'V'. Add comments for '^'.
432 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
433 (x86_64_table): Add X86_64_E8 and X86_64_E9.
434 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
436 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
439 2015-04-30 DJ Delorie <dj@redhat.com>
441 * disassemble.c (disassembler): Choose suitable disassembler based
443 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
444 it to decode mul/div insns.
445 * rl78-decode.c: Regenerate.
446 * rl78-dis.c (print_insn_rl78): Rename to...
447 (print_insn_rl78_common): ...this, take ISA parameter.
448 (print_insn_rl78): New.
449 (print_insn_rl78_g10): New.
450 (print_insn_rl78_g13): New.
451 (print_insn_rl78_g14): New.
452 (rl78_get_disassembler): New.
454 2015-04-29 Nick Clifton <nickc@redhat.com>
456 * po/fr.po: Updated French translation.
458 2015-04-27 Peter Bergner <bergner@vnet.ibm.com>
460 * ppc-opc.c (DCBT_EO): New define.
461 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
465 <waitrsv>: Do not enable for POWER7 and later.
466 <waitimpl>: Likewise.
467 <dcbt>: Default to the two operand form of the instruction for all
468 "old" cpus. For "new" cpus, use the operand ordering that matches
469 whether the cpu is server or embedded.
472 2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
474 * s390-opc.c: New instruction type VV0UU2.
475 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
478 2015-04-23 Jan Beulich <jbeulich@suse.com>
480 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
481 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
482 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
483 (vfpclasspd, vfpclassps): Add %XZ.
485 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
487 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
488 (PREFIX_UD_REPZ): Likewise.
489 (PREFIX_UD_REPNZ): Likewise.
490 (PREFIX_UD_DATA): Likewise.
491 (PREFIX_UD_ADDR): Likewise.
492 (PREFIX_UD_LOCK): Likewise.
494 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
496 * i386-dis.c (prefix_requirement): Removed.
497 (print_insn): Don't set prefix_requirement. Check
498 dp->prefix_requirement instead of prefix_requirement.
500 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
503 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
504 (PREFIX_MOD_0_0FC7_REG_6): This.
505 (PREFIX_MOD_3_0FC7_REG_6): New.
506 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
507 (prefix_table): Replace PREFIX_0FC7_REG_6 with
508 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
509 PREFIX_MOD_3_0FC7_REG_7.
510 (mod_table): Replace PREFIX_0FC7_REG_6 with
511 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
512 PREFIX_MOD_3_0FC7_REG_7.
514 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
516 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
517 (PREFIX_MANDATORY_REPNZ): Likewise.
518 (PREFIX_MANDATORY_DATA): Likewise.
519 (PREFIX_MANDATORY_ADDR): Likewise.
520 (PREFIX_MANDATORY_LOCK): Likewise.
521 (PREFIX_MANDATORY): Likewise.
522 (PREFIX_UD_SHIFT): Set to 8
523 (PREFIX_UD_REPZ): Updated.
524 (PREFIX_UD_REPNZ): Likewise.
525 (PREFIX_UD_DATA): Likewise.
526 (PREFIX_UD_ADDR): Likewise.
527 (PREFIX_UD_LOCK): Likewise.
528 (PREFIX_IGNORED_SHIFT): New.
529 (PREFIX_IGNORED_REPZ): Likewise.
530 (PREFIX_IGNORED_REPNZ): Likewise.
531 (PREFIX_IGNORED_DATA): Likewise.
532 (PREFIX_IGNORED_ADDR): Likewise.
533 (PREFIX_IGNORED_LOCK): Likewise.
534 (PREFIX_OPCODE): Likewise.
535 (PREFIX_IGNORED): Likewise.
536 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
537 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
538 (three_byte_table): Likewise.
539 (mod_table): Likewise.
540 (mandatory_prefix): Renamed to ...
541 (prefix_requirement): This.
542 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
543 Update PREFIX_90 entry.
544 (get_valid_dis386): Check prefix_requirement to see if a prefix
546 (print_insn): Replace mandatory_prefix with prefix_requirement.
548 2015-04-15 Renlin Li <renlin.li@arm.com>
550 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
551 use it for ssat and ssat16.
552 (print_insn_thumb32): Add handle case for 'D' control code.
554 2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
555 H.J. Lu <hongjiu.lu@intel.com>
557 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
558 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
559 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
560 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
561 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
562 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
563 Fill prefix_requirement field.
564 (struct dis386): Add prefix_requirement field.
565 (dis386): Fill prefix_requirement field.
566 (dis386_twobyte): Ditto.
567 (twobyte_has_mandatory_prefix_: Remove.
568 (reg_table): Fill prefix_requirement field.
569 (prefix_table): Ditto.
570 (x86_64_table): Ditto.
571 (three_byte_table): Ditto.
574 (vex_len_table): Ditto.
575 (vex_w_table): Ditto.
578 (print_insn): Use prefix_requirement.
579 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
580 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
583 2015-03-30 Mike Frysinger <vapier@gentoo.org>
585 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
587 2015-03-29 H.J. Lu <hongjiu.lu@intel.com>
589 * Makefile.in: Regenerated.
591 2015-03-25 Anton Blanchard <anton@samba.org>
593 * ppc-dis.c (disassemble_init_powerpc): Only initialise
594 powerpc_opcd_indices and vle_opcd_indices once.
596 2015-03-25 Anton Blanchard <anton@samba.org>
598 * ppc-opc.c (powerpc_opcodes): Add slbfee.
600 2015-03-24 Terry Guo <terry.guo@arm.com>
602 * arm-dis.c (opcode32): Updated to use new arm feature struct.
603 (opcode16): Likewise.
604 (coprocessor_opcodes): Replace bit with feature struct.
605 (neon_opcodes): Likewise.
606 (arm_opcodes): Likewise.
607 (thumb_opcodes): Likewise.
608 (thumb32_opcodes): Likewise.
609 (print_insn_coprocessor): Likewise.
610 (print_insn_arm): Likewise.
611 (select_arm_features): Follow new feature struct.
613 2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
615 * i386-dis.c (rm_table): Add clzero.
616 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
617 Add CPU_CLZERO_FLAGS.
618 (cpu_flags): Add CpuCLZERO.
619 * i386-opc.h: Add CpuCLZERO.
620 * i386-opc.tbl: Add clzero.
621 * i386-init.h: Re-generated.
622 * i386-tbl.h: Re-generated.
624 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
626 * mips-opc.c (decode_mips_operand): Fix constraint issues
627 with u and y operands.
629 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
631 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
633 2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
635 * s390-opc.c: Add new IBM z13 instructions.
636 * s390-opc.txt: Likewise.
638 2015-03-10 Renlin Li <renlin.li@arm.com>
640 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
641 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
643 * aarch64-asm-2.c: Regenerate.
644 * aarch64-dis-2.c: Likewise.
645 * aarch64-opc-2.c: Likewise.
647 2015-03-03 Jiong Wang <jiong.wang@arm.com>
649 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
651 2015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
653 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
655 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
656 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
658 2015-02-23 Vinay <Vinay.G@kpit.com>
660 * rl78-decode.opc (MOV): Added space between two operands for
661 'mov' instruction in index addressing mode.
662 * rl78-decode.c: Regenerate.
664 2015-02-19 Pedro Alves <palves@redhat.com>
666 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
668 2015-02-10 Pedro Alves <palves@redhat.com>
669 Tom Tromey <tromey@redhat.com>
671 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
672 microblaze_and, microblaze_xor.
673 * microblaze-opc.h (opcodes): Adjust.
675 2015-01-28 James Bowman <james.bowman@ftdichip.com>
677 * Makefile.am: Add FT32 files.
678 * configure.ac: Handle FT32.
679 * disassemble.c (disassembler): Call print_insn_ft32.
680 * ft32-dis.c: New file.
681 * ft32-opc.c: New file.
682 * Makefile.in: Regenerate.
683 * configure: Regenerate.
684 * po/POTFILES.in: Regenerate.
686 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
688 * nds32-asm.c (keyword_sr): Add new system registers.
690 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
692 * s390-dis.c (s390_extract_operand): Support vector register
694 (s390_print_insn_with_opcode): Support new operands types and add
695 new handling of optional operands.
696 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
697 and include opcode/s390.h instead.
698 (struct op_struct): New field `flags'.
699 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
700 (dumpTable): Dump flags.
701 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
703 * s390-opc.c: Add new operands types, instruction formats, and
705 (s390_opformats): Add new formats for .insn.
706 * s390-opc.txt: Add new instructions.
708 2015-01-01 Alan Modra <amodra@gmail.com>
710 Update year range in copyright notice of all files.
712 For older changes see ChangeLog-2014
714 Copyright (C) 2015 Free Software Foundation, Inc.
716 Copying and distribution of this file, with or without modification,
717 are permitted in any medium without royalty provided the copyright
718 notice and this notice are preserved.
724 version-control: never