1 2018-09-13 Jan Beulich <jbeulich@suse.com>
3 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
4 * i386-tbl.h: Re-generate.
6 2018-09-13 Jan Beulich <jbeulich@suse.com>
8 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
10 * i386-tbl.h: Re-generate.
12 2018-09-13 Jan Beulich <jbeulich@suse.com>
14 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
16 * i386-tbl.h: Re-generate.
18 2018-09-13 Jan Beulich <jbeulich@suse.com>
20 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
22 * i386-tbl.h: Re-generate.
24 2018-09-13 Jan Beulich <jbeulich@suse.com>
26 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
27 * i386-tbl.h: Re-generate.
29 2018-09-13 Jan Beulich <jbeulich@suse.com>
31 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
32 * i386-tbl.h: Re-generate.
34 2018-09-13 Jan Beulich <jbeulich@suse.com>
36 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
37 * i386-tbl.h: Re-generate.
39 2018-09-13 Jan Beulich <jbeulich@suse.com>
41 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
42 (vpbroadcastw, rdpid): Drop NoRex64.
43 * i386-tbl.h: Re-generate.
45 2018-09-13 Jan Beulich <jbeulich@suse.com>
47 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
48 store templates, adding D.
49 * i386-tbl.h: Re-generate.
51 2018-09-13 Jan Beulich <jbeulich@suse.com>
53 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
54 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
55 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
56 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
57 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
58 Fold load and store templates where possible, adding D. Drop
59 IgnoreSize where it was pointlessly present. Drop redundant
61 * i386-tbl.h: Re-generate.
63 2018-09-13 Jan Beulich <jbeulich@suse.com>
65 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
66 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
67 (intel_operand_size): Handle v_bndmk_mode.
68 (OP_E_memory): Likewise. Produce (bad) when also riprel.
70 2018-09-08 John Darrington <john@darrington.wattle.id.au>
72 * disassemble.c (ARCH_s12z): Define if ARCH_all.
74 2018-08-31 Kito Cheng <kito@andestech.com>
76 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
77 compressed floating point instructions.
79 2018-08-30 Kito Cheng <kito@andestech.com>
81 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
82 riscv_opcode.xlen_requirement.
83 * riscv-opc.c (riscv_opcodes): Update for struct change.
85 2018-08-29 Martin Aberg <maberg@gaisler.com>
87 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
88 psr (PWRPSR) instruction.
90 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
92 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
94 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
96 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
98 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
100 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
101 loongson3a as an alias of gs464 for compatibility.
102 * mips-opc.c (mips_opcodes): Change Comments.
104 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
106 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
108 (print_mips_disassembler_options): Document -M loongson-ext.
109 * mips-opc.c (LEXT2): New macro.
110 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
112 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
114 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
116 (parse_mips_ase_option): Handle -M loongson-ext option.
117 (print_mips_disassembler_options): Document -M loongson-ext.
118 * mips-opc.c (IL3A): Delete.
119 * mips-opc.c (LEXT): New macro.
120 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
123 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
125 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
127 (parse_mips_ase_option): Handle -M loongson-cam option.
128 (print_mips_disassembler_options): Document -M loongson-cam.
129 * mips-opc.c (LCAM): New macro.
130 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
133 2018-08-21 Alan Modra <amodra@gmail.com>
135 * ppc-dis.c (operand_value_powerpc): Init "invalid".
136 (skip_optional_operands): Count optional operands, and update
137 ppc_optional_operand_value call.
138 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
139 (extract_vlensi): Likewise.
140 (extract_fxm): Return default value for missing optional operand.
141 (extract_ls, extract_raq, extract_tbr): Likewise.
142 (insert_sxl, extract_sxl): New functions.
143 (insert_esync, extract_esync): Remove Power9 handling and simplify.
144 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
145 flag and extra entry.
146 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
149 2018-08-20 Alan Modra <amodra@gmail.com>
151 * sh-opc.h (MASK): Simplify.
153 2018-08-18 John Darrington <john@darrington.wattle.id.au>
155 * s12z-dis.c (bm_decode): Deal with cases where the mode is
156 BM_RESERVED0 or BM_RESERVED1
157 (bm_rel_decode, bm_n_bytes): Ditto.
159 2018-08-18 John Darrington <john@darrington.wattle.id.au>
163 2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
165 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
166 address with the addr32 prefix and without base nor index
169 2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
171 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
172 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
173 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
174 (cpu_flags): Add CpuCMOV and CpuFXSR.
175 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
176 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
177 * i386-init.h: Regenerated.
178 * i386-tbl.h: Likewise.
180 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
182 * arc-regs.h: Update auxiliary registers.
184 2018-08-06 Jan Beulich <jbeulich@suse.com>
186 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
187 (RegIP, RegIZ): Define.
188 * i386-reg.tbl: Adjust comments.
189 (rip): Use Qword instead of BaseIndex. Use RegIP.
190 (eip): Use Dword instead of BaseIndex. Use RegIP.
191 (riz): Add Qword. Use RegIZ.
192 (eiz): Add Dword. Use RegIZ.
193 * i386-tbl.h: Re-generate.
195 2018-08-03 Jan Beulich <jbeulich@suse.com>
197 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
198 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
199 vpmovzxdq, vpmovzxwd): Remove NoRex64.
200 * i386-tbl.h: Re-generate.
202 2018-08-03 Jan Beulich <jbeulich@suse.com>
204 * i386-gen.c (operand_types): Remove Mem field.
205 * i386-opc.h (union i386_operand_type): Remove mem field.
206 * i386-init.h, i386-tbl.h: Re-generate.
208 2018-08-01 Alan Modra <amodra@gmail.com>
210 * po/POTFILES.in: Regenerate.
212 2018-07-31 Nick Clifton <nickc@redhat.com>
214 * po/sv.po: Updated Swedish translation.
216 2018-07-31 Jan Beulich <jbeulich@suse.com>
218 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
219 * i386-init.h, i386-tbl.h: Re-generate.
221 2018-07-31 Jan Beulich <jbeulich@suse.com>
223 * i386-opc.h (ZEROING_MASKING) Rename to ...
224 (DYNAMIC_MASKING): ... this. Adjust comment.
225 * i386-opc.tbl (MaskingMorZ): Define.
226 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
227 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
228 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
229 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
230 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
231 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
232 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
233 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
234 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
236 2018-07-31 Jan Beulich <jbeulich@suse.com>
238 * i386-opc.tbl: Use element rather than vector size for AVX512*
239 scatter/gather insns.
240 * i386-tbl.h: Re-generate.
242 2018-07-31 Jan Beulich <jbeulich@suse.com>
244 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
245 (cpu_flags): Drop CpuVREX.
246 * i386-opc.h (CpuVREX): Delete.
247 (union i386_cpu_flags): Remove cpuvrex.
248 * i386-init.h, i386-tbl.h: Re-generate.
250 2018-07-30 Jim Wilson <jimw@sifive.com>
252 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
254 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
256 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
258 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
259 * Makefile.in: Regenerated.
260 * configure.ac: Add C-SKY.
261 * configure: Regenerated.
262 * csky-dis.c: New file.
263 * csky-opc.h: New file.
264 * disassemble.c (ARCH_csky): Define.
265 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
266 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
268 2018-07-27 Alan Modra <amodra@gmail.com>
270 * ppc-opc.c (insert_sprbat): Correct function parameter and
272 (extract_sprbat): Likewise, variable too.
274 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
275 Alan Modra <amodra@gmail.com>
277 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
278 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
279 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
280 support disjointed BAT.
281 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
282 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
283 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
285 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
286 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
288 * i386-gen.c (adjust_broadcast_modifier): New function.
289 (process_i386_opcode_modifier): Add an argument for operands.
290 Adjust the Broadcast value based on operands.
291 (output_i386_opcode): Pass operand_types to
292 process_i386_opcode_modifier.
293 (process_i386_opcodes): Pass NULL as operands to
294 process_i386_opcode_modifier.
295 * i386-opc.h (BYTE_BROADCAST): New.
296 (WORD_BROADCAST): Likewise.
297 (DWORD_BROADCAST): Likewise.
298 (QWORD_BROADCAST): Likewise.
299 (i386_opcode_modifier): Expand broadcast to 3 bits.
300 * i386-tbl.h: Regenerated.
302 2018-07-24 Alan Modra <amodra@gmail.com>
305 * or1k-desc.h: Regenerate.
307 2018-07-24 Jan Beulich <jbeulich@suse.com>
309 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
310 vcvtusi2ss, and vcvtusi2sd.
311 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
312 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
313 * i386-tbl.h: Re-generate.
315 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
317 * arc-opc.c (extract_w6): Fix extending the sign.
319 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
321 * arc-tbl.h (vewt): Allow it for ARC EM family.
323 2018-07-23 Alan Modra <amodra@gmail.com>
326 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
327 opcode variants for mtspr/mfspr encodings.
329 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
330 Maciej W. Rozycki <macro@mips.com>
332 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
333 loongson3a descriptors.
334 (parse_mips_ase_option): Handle -M loongson-mmi option.
335 (print_mips_disassembler_options): Document -M loongson-mmi.
336 * mips-opc.c (LMMI): New macro.
337 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
340 2018-07-19 Jan Beulich <jbeulich@suse.com>
342 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
343 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
344 IgnoreSize and [XYZ]MMword where applicable.
345 * i386-tbl.h: Re-generate.
347 2018-07-19 Jan Beulich <jbeulich@suse.com>
349 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
350 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
351 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
352 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
353 * i386-tbl.h: Re-generate.
355 2018-07-19 Jan Beulich <jbeulich@suse.com>
357 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
358 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
359 VPCLMULQDQ templates into their respective AVX512VL counterparts
360 where possible, using Disp8ShiftVL and CheckRegSize instead of
361 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
362 * i386-tbl.h: Re-generate.
364 2018-07-19 Jan Beulich <jbeulich@suse.com>
366 * i386-opc.tbl: Fold AVX512DQ templates into their respective
367 AVX512VL counterparts where possible, using Disp8ShiftVL and
368 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
369 IgnoreSize) as appropriate.
370 * i386-tbl.h: Re-generate.
372 2018-07-19 Jan Beulich <jbeulich@suse.com>
374 * i386-opc.tbl: Fold AVX512BW templates into their respective
375 AVX512VL counterparts where possible, using Disp8ShiftVL and
376 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
377 IgnoreSize) as appropriate.
378 * i386-tbl.h: Re-generate.
380 2018-07-19 Jan Beulich <jbeulich@suse.com>
382 * i386-opc.tbl: Fold AVX512CD templates into their respective
383 AVX512VL counterparts where possible, using Disp8ShiftVL and
384 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
385 IgnoreSize) as appropriate.
386 * i386-tbl.h: Re-generate.
388 2018-07-19 Jan Beulich <jbeulich@suse.com>
390 * i386-opc.h (DISP8_SHIFT_VL): New.
391 * i386-opc.tbl (Disp8ShiftVL): Define.
392 (various): Fold AVX512VL templates into their respective
393 AVX512F counterparts where possible, using Disp8ShiftVL and
394 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
395 IgnoreSize) as appropriate.
396 * i386-tbl.h: Re-generate.
398 2018-07-19 Jan Beulich <jbeulich@suse.com>
400 * Makefile.am: Change dependencies and rule for
401 $(srcdir)/i386-init.h.
402 * Makefile.in: Re-generate.
403 * i386-gen.c (process_i386_opcodes): New local variable
404 "marker". Drop opening of input file. Recognize marker and line
406 * i386-opc.tbl (OPCODE_I386_H): Define.
407 (i386-opc.h): Include it.
410 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
413 * i386-opc.h (Byte): Update comments.
422 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
424 * i386-tbl.h: Regenerated.
426 2018-07-12 Sudakshina Das <sudi.das@arm.com>
428 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
429 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
430 * aarch64-asm-2.c: Regenerate.
431 * aarch64-dis-2.c: Regenerate.
432 * aarch64-opc-2.c: Regenerate.
434 2018-07-12 Tamar Christina <tamar.christina@arm.com>
437 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
438 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
439 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
440 sqdmulh, sqrdmulh): Use Em16.
442 2018-07-11 Sudakshina Das <sudi.das@arm.com>
444 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
445 csdb together with them.
446 (thumb32_opcodes): Likewise.
448 2018-07-11 Jan Beulich <jbeulich@suse.com>
450 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
451 requiring 32-bit registers as operands 2 and 3. Improve
453 (mwait, mwaitx): Fold templates. Improve comments.
454 OPERAND_TYPE_INOUTPORTREG.
455 * i386-tbl.h: Re-generate.
457 2018-07-11 Jan Beulich <jbeulich@suse.com>
459 * i386-gen.c (operand_type_init): Remove
460 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
461 OPERAND_TYPE_INOUTPORTREG.
462 * i386-init.h: Re-generate.
464 2018-07-11 Jan Beulich <jbeulich@suse.com>
466 * i386-opc.tbl (wrssd, wrussd): Add Dword.
467 (wrssq, wrussq): Add Qword.
468 * i386-tbl.h: Re-generate.
470 2018-07-11 Jan Beulich <jbeulich@suse.com>
472 * i386-opc.h: Rename OTMax to OTNum.
473 (OTNumOfUints): Adjust calculation.
474 (OTUnused): Directly alias to OTNum.
476 2018-07-09 Maciej W. Rozycki <macro@mips.com>
478 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
480 (lea_reg_xys): Likewise.
481 (print_insn_loop_primitive): Rename `reg' local variable to
484 2018-07-06 Tamar Christina <tamar.christina@arm.com>
487 * aarch64-tbl.h (ldarh): Fix disassembly mask.
489 2018-07-06 Tamar Christina <tamar.christina@arm.com>
492 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
493 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
495 2018-07-02 Maciej W. Rozycki <macro@mips.com>
498 * mips-dis.c (mips_option_arg_t): New enumeration.
499 (mips_options): New variable.
500 (disassembler_options_mips): New function.
501 (print_mips_disassembler_options): Reimplement in terms of
502 `disassembler_options_mips'.
503 * arm-dis.c (disassembler_options_arm): Adapt to using the
504 `disasm_options_and_args_t' structure.
505 * ppc-dis.c (disassembler_options_powerpc): Likewise.
506 * s390-dis.c (disassembler_options_s390): Likewise.
508 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
510 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
512 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
513 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
514 * testsuite/ld-arm/tls-longplt.d: Likewise.
516 2018-06-29 Tamar Christina <tamar.christina@arm.com>
519 * aarch64-asm-2.c: Regenerate.
520 * aarch64-dis-2.c: Likewise.
521 * aarch64-opc-2.c: Likewise.
522 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
523 * aarch64-opc.c (operand_general_constraint_met_p,
524 aarch64_print_operand): Likewise.
525 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
526 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
528 (AARCH64_OPERANDS): Add Em2.
530 2018-06-26 Nick Clifton <nickc@redhat.com>
532 * po/uk.po: Updated Ukranian translation.
533 * po/de.po: Updated German translation.
534 * po/pt_BR.po: Updated Brazilian Portuguese translation.
536 2018-06-26 Nick Clifton <nickc@redhat.com>
538 * nfp-dis.c: Fix spelling mistake.
540 2018-06-24 Nick Clifton <nickc@redhat.com>
542 * configure: Regenerate.
543 * po/opcodes.pot: Regenerate.
545 2018-06-24 Nick Clifton <nickc@redhat.com>
549 2018-06-19 Tamar Christina <tamar.christina@arm.com>
551 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
552 * aarch64-asm-2.c: Regenerate.
553 * aarch64-dis-2.c: Likewise.
555 2018-06-21 Maciej W. Rozycki <macro@mips.com>
557 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
558 `-M ginv' option description.
560 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
563 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
566 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
568 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
569 * configure.ac: Remove AC_PREREQ.
570 * Makefile.in: Re-generate.
571 * aclocal.m4: Re-generate.
572 * configure: Re-generate.
574 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
576 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
577 mips64r6 descriptors.
578 (parse_mips_ase_option): Handle -Mginv option.
579 (print_mips_disassembler_options): Document -Mginv.
580 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
582 (mips_opcodes): Define ginvi and ginvt.
584 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
585 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
587 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
588 * mips-opc.c (CRC, CRC64): New macros.
589 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
590 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
593 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
596 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
597 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
599 2018-06-06 Alan Modra <amodra@gmail.com>
601 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
602 setjmp. Move init for some other vars later too.
604 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
606 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
607 (dis_private): Add new fields for property section tracking.
608 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
609 (xtensa_instruction_fits): New functions.
610 (fetch_data): Bump minimal fetch size to 4.
611 (print_insn_xtensa): Make struct dis_private static.
612 Load and prepare property table on section change.
613 Don't disassemble literals. Don't disassemble instructions that
614 cross property table boundaries.
616 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
618 * configure: Regenerated.
620 2018-06-01 Jan Beulich <jbeulich@suse.com>
622 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
623 * i386-tbl.h: Re-generate.
625 2018-06-01 Jan Beulich <jbeulich@suse.com>
627 * i386-opc.tbl (sldt, str): Add NoRex64.
628 * i386-tbl.h: Re-generate.
630 2018-06-01 Jan Beulich <jbeulich@suse.com>
632 * i386-opc.tbl (invpcid): Add Oword.
633 * i386-tbl.h: Re-generate.
635 2018-06-01 Alan Modra <amodra@gmail.com>
637 * sysdep.h (_bfd_error_handler): Don't declare.
638 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
639 * rl78-decode.opc: Likewise.
640 * msp430-decode.c: Regenerate.
641 * rl78-decode.c: Regenerate.
643 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
645 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
646 * i386-init.h : Regenerated.
648 2018-05-25 Alan Modra <amodra@gmail.com>
650 * Makefile.in: Regenerate.
651 * po/POTFILES.in: Regenerate.
653 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
655 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
656 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
657 (insert_bab, extract_bab, insert_btab, extract_btab,
658 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
659 (BAT, BBA VBA RBS XB6S): Delete macros.
660 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
661 (BB, BD, RBX, XC6): Update for new macros.
662 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
663 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
664 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
665 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
667 2018-05-18 John Darrington <john@darrington.wattle.id.au>
669 * Makefile.am: Add support for s12z architecture.
670 * configure.ac: Likewise.
671 * disassemble.c: Likewise.
672 * disassemble.h: Likewise.
673 * Makefile.in: Regenerate.
674 * configure: Regenerate.
675 * s12z-dis.c: New file.
678 2018-05-18 Alan Modra <amodra@gmail.com>
680 * nfp-dis.c: Don't #include libbfd.h.
681 (init_nfp3200_priv): Use bfd_get_section_contents.
682 (nit_nfp6000_mecsr_sec): Likewise.
684 2018-05-17 Nick Clifton <nickc@redhat.com>
686 * po/zh_CN.po: Updated simplified Chinese translation.
688 2018-05-16 Tamar Christina <tamar.christina@arm.com>
691 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
692 * aarch64-dis-2.c: Regenerate.
694 2018-05-15 Tamar Christina <tamar.christina@arm.com>
697 * aarch64-asm.c (opintl.h): Include.
698 (aarch64_ins_sysreg): Enforce read/write constraints.
699 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
700 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
701 (F_REG_READ, F_REG_WRITE): New.
702 * aarch64-opc.c (aarch64_print_operand): Generate notes for
704 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
705 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
706 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
707 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
708 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
709 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
710 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
711 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
712 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
713 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
714 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
715 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
716 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
717 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
718 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
719 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
720 msr (F_SYS_WRITE), mrs (F_SYS_READ).
722 2018-05-15 Tamar Christina <tamar.christina@arm.com>
725 * aarch64-dis.c (no_notes: New.
726 (parse_aarch64_dis_option): Support notes.
727 (aarch64_decode_insn, print_operands): Likewise.
728 (print_aarch64_disassembler_options): Document notes.
729 * aarch64-opc.c (aarch64_print_operand): Support notes.
731 2018-05-15 Tamar Christina <tamar.christina@arm.com>
734 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
735 and take error struct.
736 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
737 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
738 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
739 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
740 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
741 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
742 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
743 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
744 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
745 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
746 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
747 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
748 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
749 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
750 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
751 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
752 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
753 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
754 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
755 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
756 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
757 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
758 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
759 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
760 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
761 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
762 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
763 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
764 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
765 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
766 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
767 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
768 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
769 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
770 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
771 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
772 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
773 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
774 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
775 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
776 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
777 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
778 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
779 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
780 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
781 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
782 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
783 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
784 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
785 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
786 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
787 (determine_disassembling_preference, aarch64_decode_insn,
788 print_insn_aarch64_word, print_insn_data): Take errors struct.
789 (print_insn_aarch64): Use errors.
790 * aarch64-asm-2.c: Regenerate.
791 * aarch64-dis-2.c: Regenerate.
792 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
793 boolean in aarch64_insert_operan.
794 (print_operand_extractor): Likewise.
795 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
797 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
799 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
801 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
803 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
805 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
807 * cr16-opc.c (cr16_instruction): Comment typo fix.
808 * hppa-dis.c (print_insn_hppa): Likewise.
810 2018-05-08 Jim Wilson <jimw@sifive.com>
812 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
813 (match_c_slli64, match_srxi_as_c_srxi): New.
814 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
815 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
816 <c.slli, c.srli, c.srai>: Use match_s_slli.
817 <c.slli64, c.srli64, c.srai64>: New.
819 2018-05-08 Alan Modra <amodra@gmail.com>
821 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
822 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
823 partition opcode space for index lookup.
825 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
827 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
828 <insn_length>: ...with this. Update usage.
829 Remove duplicate call to *info->memory_error_func.
831 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
832 H.J. Lu <hongjiu.lu@intel.com>
834 * i386-dis.c (Gva): New.
835 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
836 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
837 (prefix_table): New instructions (see prefix above).
838 (mod_table): New instructions (see prefix above).
839 (OP_G): Handle va_mode.
840 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
842 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
843 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
844 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
845 * i386-opc.tbl: Add movidir{i,64b}.
846 * i386-init.h: Regenerated.
847 * i386-tbl.h: Likewise.
849 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
851 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
853 * i386-opc.h (AddrPrefixOp0): Renamed to ...
854 (AddrPrefixOpReg): This.
855 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
856 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
858 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
860 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
861 (vle_num_opcodes): Likewise.
862 (spe2_num_opcodes): Likewise.
863 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
865 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
866 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
869 2018-05-01 Tamar Christina <tamar.christina@arm.com>
871 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
873 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
875 Makefile.am: Added nfp-dis.c.
876 configure.ac: Added bfd_nfp_arch.
877 disassemble.h: Added print_insn_nfp prototype.
878 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
879 nfp-dis.c: New, for NFP support.
880 po/POTFILES.in: Added nfp-dis.c to the list.
881 Makefile.in: Regenerate.
882 configure: Regenerate.
884 2018-04-26 Jan Beulich <jbeulich@suse.com>
886 * i386-opc.tbl: Fold various non-memory operand AVX512VL
887 templates into their base ones.
888 * i386-tlb.h: Re-generate.
890 2018-04-26 Jan Beulich <jbeulich@suse.com>
892 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
893 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
894 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
895 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
896 * i386-init.h: Re-generate.
898 2018-04-26 Jan Beulich <jbeulich@suse.com>
900 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
901 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
902 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
903 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
905 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
907 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
909 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
910 cpuregzmm, and cpuregmask.
911 * i386-init.h: Re-generate.
912 * i386-tbl.h: Re-generate.
914 2018-04-26 Jan Beulich <jbeulich@suse.com>
916 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
917 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
918 * i386-init.h: Re-generate.
920 2018-04-26 Jan Beulich <jbeulich@suse.com>
922 * i386-gen.c (VexImmExt): Delete.
923 * i386-opc.h (VexImmExt, veximmext): Delete.
924 * i386-opc.tbl: Drop all VexImmExt uses.
925 * i386-tlb.h: Re-generate.
927 2018-04-25 Jan Beulich <jbeulich@suse.com>
929 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
931 * i386-tlb.h: Re-generate.
933 2018-04-25 Tamar Christina <tamar.christina@arm.com>
935 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
937 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
939 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
941 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
942 (cpu_flags): Add CpuCLDEMOTE.
943 * i386-init.h: Regenerate.
944 * i386-opc.h (enum): Add CpuCLDEMOTE,
945 (i386_cpu_flags): Add cpucldemote.
946 * i386-opc.tbl: Add cldemote.
947 * i386-tbl.h: Regenerate.
949 2018-04-16 Alan Modra <amodra@gmail.com>
951 * Makefile.am: Remove sh5 and sh64 support.
952 * configure.ac: Likewise.
953 * disassemble.c: Likewise.
954 * disassemble.h: Likewise.
955 * sh-dis.c: Likewise.
956 * sh64-dis.c: Delete.
957 * sh64-opc.c: Delete.
958 * sh64-opc.h: Delete.
959 * Makefile.in: Regenerate.
960 * configure: Regenerate.
961 * po/POTFILES.in: Regenerate.
963 2018-04-16 Alan Modra <amodra@gmail.com>
965 * Makefile.am: Remove w65 support.
966 * configure.ac: Likewise.
967 * disassemble.c: Likewise.
968 * disassemble.h: Likewise.
971 * Makefile.in: Regenerate.
972 * configure: Regenerate.
973 * po/POTFILES.in: Regenerate.
975 2018-04-16 Alan Modra <amodra@gmail.com>
977 * configure.ac: Remove we32k support.
978 * configure: Regenerate.
980 2018-04-16 Alan Modra <amodra@gmail.com>
982 * Makefile.am: Remove m88k support.
983 * configure.ac: Likewise.
984 * disassemble.c: Likewise.
985 * disassemble.h: Likewise.
986 * m88k-dis.c: Delete.
987 * Makefile.in: Regenerate.
988 * configure: Regenerate.
989 * po/POTFILES.in: Regenerate.
991 2018-04-16 Alan Modra <amodra@gmail.com>
993 * Makefile.am: Remove i370 support.
994 * configure.ac: Likewise.
995 * disassemble.c: Likewise.
996 * disassemble.h: Likewise.
997 * i370-dis.c: Delete.
998 * i370-opc.c: Delete.
999 * Makefile.in: Regenerate.
1000 * configure: Regenerate.
1001 * po/POTFILES.in: Regenerate.
1003 2018-04-16 Alan Modra <amodra@gmail.com>
1005 * Makefile.am: Remove h8500 support.
1006 * configure.ac: Likewise.
1007 * disassemble.c: Likewise.
1008 * disassemble.h: Likewise.
1009 * h8500-dis.c: Delete.
1010 * h8500-opc.h: Delete.
1011 * Makefile.in: Regenerate.
1012 * configure: Regenerate.
1013 * po/POTFILES.in: Regenerate.
1015 2018-04-16 Alan Modra <amodra@gmail.com>
1017 * configure.ac: Remove tahoe support.
1018 * configure: Regenerate.
1020 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1022 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1024 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1026 * i386-tbl.h: Regenerated.
1028 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1030 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1031 PREFIX_MOD_1_0FAE_REG_6.
1033 (OP_E_register): Use va_mode.
1034 * i386-dis-evex.h (prefix_table):
1035 New instructions (see prefixes above).
1036 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1037 (cpu_flags): Likewise.
1038 * i386-opc.h (enum): Likewise.
1039 (i386_cpu_flags): Likewise.
1040 * i386-opc.tbl: Add umonitor, umwait, tpause.
1041 * i386-init.h: Regenerate.
1042 * i386-tbl.h: Likewise.
1044 2018-04-11 Alan Modra <amodra@gmail.com>
1046 * opcodes/i860-dis.c: Delete.
1047 * opcodes/i960-dis.c: Delete.
1048 * Makefile.am: Remove i860 and i960 support.
1049 * configure.ac: Likewise.
1050 * disassemble.c: Likewise.
1051 * disassemble.h: Likewise.
1052 * Makefile.in: Regenerate.
1053 * configure: Regenerate.
1054 * po/POTFILES.in: Regenerate.
1056 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1059 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1061 (print_insn): Clear vex instead of vex.evex.
1063 2018-04-04 Nick Clifton <nickc@redhat.com>
1065 * po/es.po: Updated Spanish translation.
1067 2018-03-28 Jan Beulich <jbeulich@suse.com>
1069 * i386-gen.c (opcode_modifiers): Delete VecESize.
1070 * i386-opc.h (VecESize): Delete.
1071 (struct i386_opcode_modifier): Delete vecesize.
1072 * i386-opc.tbl: Drop VecESize.
1073 * i386-tlb.h: Re-generate.
1075 2018-03-28 Jan Beulich <jbeulich@suse.com>
1077 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1078 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1079 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1080 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1081 * i386-tlb.h: Re-generate.
1083 2018-03-28 Jan Beulich <jbeulich@suse.com>
1085 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1087 * i386-tlb.h: Re-generate.
1089 2018-03-28 Jan Beulich <jbeulich@suse.com>
1091 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1092 (vex_len_table): Drop Y for vcvt*2si.
1093 (putop): Replace plain 'Y' handling by abort().
1095 2018-03-28 Nick Clifton <nickc@redhat.com>
1098 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1099 instructions with only a base address register.
1100 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1101 handle AARHC64_OPND_SVE_ADDR_R.
1102 (aarch64_print_operand): Likewise.
1103 * aarch64-asm-2.c: Regenerate.
1104 * aarch64_dis-2.c: Regenerate.
1105 * aarch64-opc-2.c: Regenerate.
1107 2018-03-22 Jan Beulich <jbeulich@suse.com>
1109 * i386-opc.tbl: Drop VecESize from register only insn forms and
1110 memory forms not allowing broadcast.
1111 * i386-tlb.h: Re-generate.
1113 2018-03-22 Jan Beulich <jbeulich@suse.com>
1115 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1116 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1117 sha256*): Drop Disp<N>.
1119 2018-03-22 Jan Beulich <jbeulich@suse.com>
1121 * i386-dis.c (EbndS, bnd_swap_mode): New.
1122 (prefix_table): Use EbndS.
1123 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1124 * i386-opc.tbl (bndmov): Move misplaced Load.
1125 * i386-tlb.h: Re-generate.
1127 2018-03-22 Jan Beulich <jbeulich@suse.com>
1129 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1130 templates allowing memory operands and folded ones for register
1132 * i386-tlb.h: Re-generate.
1134 2018-03-22 Jan Beulich <jbeulich@suse.com>
1136 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1137 256-bit templates. Drop redundant leftover Disp<N>.
1138 * i386-tlb.h: Re-generate.
1140 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
1142 * riscv-opc.c (riscv_insn_types): New.
1144 2018-03-13 Nick Clifton <nickc@redhat.com>
1146 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1148 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1150 * i386-opc.tbl: Add Optimize to clr.
1151 * i386-tbl.h: Regenerated.
1153 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1155 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1156 * i386-opc.h (OldGcc): Removed.
1157 (i386_opcode_modifier): Remove oldgcc.
1158 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1159 instructions for old (<= 2.8.1) versions of gcc.
1160 * i386-tbl.h: Regenerated.
1162 2018-03-08 Jan Beulich <jbeulich@suse.com>
1164 * i386-opc.h (EVEXDYN): New.
1165 * i386-opc.tbl: Fold various AVX512VL templates.
1166 * i386-tlb.h: Re-generate.
1168 2018-03-08 Jan Beulich <jbeulich@suse.com>
1170 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1171 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1172 vpexpandd, vpexpandq): Fold AFX512VF templates.
1173 * i386-tlb.h: Re-generate.
1175 2018-03-08 Jan Beulich <jbeulich@suse.com>
1177 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1178 Fold 128- and 256-bit VEX-encoded templates.
1179 * i386-tlb.h: Re-generate.
1181 2018-03-08 Jan Beulich <jbeulich@suse.com>
1183 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1184 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1185 vpexpandd, vpexpandq): Fold AVX512F templates.
1186 * i386-tlb.h: Re-generate.
1188 2018-03-08 Jan Beulich <jbeulich@suse.com>
1190 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1191 64-bit templates. Drop Disp<N>.
1192 * i386-tlb.h: Re-generate.
1194 2018-03-08 Jan Beulich <jbeulich@suse.com>
1196 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1197 and 256-bit templates.
1198 * i386-tlb.h: Re-generate.
1200 2018-03-08 Jan Beulich <jbeulich@suse.com>
1202 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1203 * i386-tlb.h: Re-generate.
1205 2018-03-08 Jan Beulich <jbeulich@suse.com>
1207 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1209 * i386-tlb.h: Re-generate.
1211 2018-03-08 Jan Beulich <jbeulich@suse.com>
1213 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1214 * i386-tlb.h: Re-generate.
1216 2018-03-08 Jan Beulich <jbeulich@suse.com>
1218 * i386-gen.c (opcode_modifiers): Delete FloatD.
1219 * i386-opc.h (FloatD): Delete.
1220 (struct i386_opcode_modifier): Delete floatd.
1221 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1223 * i386-tlb.h: Re-generate.
1225 2018-03-08 Jan Beulich <jbeulich@suse.com>
1227 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1229 2018-03-08 Jan Beulich <jbeulich@suse.com>
1231 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1232 * i386-tlb.h: Re-generate.
1234 2018-03-08 Jan Beulich <jbeulich@suse.com>
1236 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1238 * i386-tlb.h: Re-generate.
1240 2018-03-07 Alan Modra <amodra@gmail.com>
1242 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1244 * disassemble.h (print_insn_rs6000): Delete.
1245 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1246 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1247 (print_insn_rs6000): Delete.
1249 2018-03-03 Alan Modra <amodra@gmail.com>
1251 * sysdep.h (opcodes_error_handler): Define.
1252 (_bfd_error_handler): Declare.
1253 * Makefile.am: Remove stray #.
1254 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1256 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1257 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1258 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1259 opcodes_error_handler to print errors. Standardize error messages.
1260 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1261 and include opintl.h.
1262 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1263 * i386-gen.c: Standardize error messages.
1264 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1265 * Makefile.in: Regenerate.
1266 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1267 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1268 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1269 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1270 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1271 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1272 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1273 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1274 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1275 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1276 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1277 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1278 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1280 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1282 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1283 vpsub[bwdq] instructions.
1284 * i386-tbl.h: Regenerated.
1286 2018-03-01 Alan Modra <amodra@gmail.com>
1288 * configure.ac (ALL_LINGUAS): Sort.
1289 * configure: Regenerate.
1291 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1293 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1294 macro by assignements.
1296 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1299 * i386-gen.c (opcode_modifiers): Add Optimize.
1300 * i386-opc.h (Optimize): New enum.
1301 (i386_opcode_modifier): Add optimize.
1302 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1303 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1304 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1305 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1306 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1308 * i386-tbl.h: Regenerated.
1310 2018-02-26 Alan Modra <amodra@gmail.com>
1312 * crx-dis.c (getregliststring): Allocate a large enough buffer
1313 to silence false positive gcc8 warning.
1315 2018-02-22 Shea Levy <shea@shealevy.com>
1317 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1319 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1321 * i386-opc.tbl: Add {rex},
1322 * i386-tbl.h: Regenerated.
1324 2018-02-20 Maciej W. Rozycki <macro@mips.com>
1326 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1327 (mips16_opcodes): Replace `M' with `m' for "restore".
1329 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1331 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1333 2018-02-13 Maciej W. Rozycki <macro@mips.com>
1335 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1336 variable to `function_index'.
1338 2018-02-13 Nick Clifton <nickc@redhat.com>
1341 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1342 about truncation of printing.
1344 2018-02-12 Henry Wong <henry@stuffedcow.net>
1346 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1348 2018-02-05 Nick Clifton <nickc@redhat.com>
1350 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1352 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1354 * i386-dis.c (enum): Add pconfig.
1355 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1356 (cpu_flags): Add CpuPCONFIG.
1357 * i386-opc.h (enum): Add CpuPCONFIG.
1358 (i386_cpu_flags): Add cpupconfig.
1359 * i386-opc.tbl: Add PCONFIG instruction.
1360 * i386-init.h: Regenerate.
1361 * i386-tbl.h: Likewise.
1363 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1365 * i386-dis.c (enum): Add PREFIX_0F09.
1366 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1367 (cpu_flags): Add CpuWBNOINVD.
1368 * i386-opc.h (enum): Add CpuWBNOINVD.
1369 (i386_cpu_flags): Add cpuwbnoinvd.
1370 * i386-opc.tbl: Add WBNOINVD instruction.
1371 * i386-init.h: Regenerate.
1372 * i386-tbl.h: Likewise.
1374 2018-01-17 Jim Wilson <jimw@sifive.com>
1376 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1378 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1380 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1381 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1382 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1383 (cpu_flags): Add CpuIBT, CpuSHSTK.
1384 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1385 (i386_cpu_flags): Add cpuibt, cpushstk.
1386 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1387 * i386-init.h: Regenerate.
1388 * i386-tbl.h: Likewise.
1390 2018-01-16 Nick Clifton <nickc@redhat.com>
1392 * po/pt_BR.po: Updated Brazilian Portugese translation.
1393 * po/de.po: Updated German translation.
1395 2018-01-15 Jim Wilson <jimw@sifive.com>
1397 * riscv-opc.c (match_c_nop): New.
1398 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1400 2018-01-15 Nick Clifton <nickc@redhat.com>
1402 * po/uk.po: Updated Ukranian translation.
1404 2018-01-13 Nick Clifton <nickc@redhat.com>
1406 * po/opcodes.pot: Regenerated.
1408 2018-01-13 Nick Clifton <nickc@redhat.com>
1410 * configure: Regenerate.
1412 2018-01-13 Nick Clifton <nickc@redhat.com>
1414 2.30 branch created.
1416 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1418 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1419 * i386-tbl.h: Regenerate.
1421 2018-01-10 Jan Beulich <jbeulich@suse.com>
1423 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1424 * i386-tbl.h: Re-generate.
1426 2018-01-10 Jan Beulich <jbeulich@suse.com>
1428 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1429 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1430 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1431 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1432 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1433 Disp8MemShift of AVX512VL forms.
1434 * i386-tbl.h: Re-generate.
1436 2018-01-09 Jim Wilson <jimw@sifive.com>
1438 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1439 then the hi_addr value is zero.
1441 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1443 * arm-dis.c (arm_opcodes): Add csdb.
1444 (thumb32_opcodes): Add csdb.
1446 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1448 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1449 * aarch64-asm-2.c: Regenerate.
1450 * aarch64-dis-2.c: Regenerate.
1451 * aarch64-opc-2.c: Regenerate.
1453 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1456 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1457 Remove AVX512 vmovd with 64-bit operands.
1458 * i386-tbl.h: Regenerated.
1460 2018-01-05 Jim Wilson <jimw@sifive.com>
1462 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1465 2018-01-03 Alan Modra <amodra@gmail.com>
1467 Update year range in copyright notice of all files.
1469 2018-01-02 Jan Beulich <jbeulich@suse.com>
1471 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1472 and OPERAND_TYPE_REGZMM entries.
1474 For older changes see ChangeLog-2017
1476 Copyright (C) 2018 Free Software Foundation, Inc.
1478 Copying and distribution of this file, with or without modification,
1479 are permitted in any medium without royalty provided the copyright
1480 notice and this notice are preserved.
1486 version-control: never