opcodes/ChangeLog

   1 2018-09-17  Kito Cheng  <kito@andestech.com>
   2
   3         * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
   4
   5 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
   6
   7         PR gas/23670
   8         * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
   9         EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
  10         (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
  11         (EVEX_LEN_0F7E_P_1): Likewise.
  12         (EVEX_LEN_0F7E_P_2): Likewise.
  13         (EVEX_LEN_0FD6_P_2): Likewise.
  14         * i386-dis.c (USE_EVEX_LEN_TABLE): New.
  15         (EVEX_LEN_TABLE): Likewise.
  16         (EVEX_LEN_0F6E_P_2): New enum.
  17         (EVEX_LEN_0F7E_P_1): Likewise.
  18         (EVEX_LEN_0F7E_P_2): Likewise.
  19         (EVEX_LEN_0FD6_P_2): Likewise.
  20         (evex_len_table): New.
  21         (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
  22         * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
  23         * i386-tbl.h: Regenerated.
  24
  25 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
  26
  27         PR gas/23665
  28         * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
  29         VEX_LEN_0F7E_P_2 entries.
  30         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
  31         * i386-tbl.h: Regenerated.
  32
  33 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
  34
  35         * i386-dis.c (VZERO_Fixup): Removed.
  36         (VZERO): Likewise.
  37         (VEX_LEN_0F10_P_1): Likewise.
  38         (VEX_LEN_0F10_P_3): Likewise.
  39         (VEX_LEN_0F11_P_1): Likewise.
  40         (VEX_LEN_0F11_P_3): Likewise.
  41         (VEX_LEN_0F2E_P_0): Likewise.
  42         (VEX_LEN_0F2E_P_2): Likewise.
  43         (VEX_LEN_0F2F_P_0): Likewise.
  44         (VEX_LEN_0F2F_P_2): Likewise.
  45         (VEX_LEN_0F51_P_1): Likewise.
  46         (VEX_LEN_0F51_P_3): Likewise.
  47         (VEX_LEN_0F52_P_1): Likewise.
  48         (VEX_LEN_0F53_P_1): Likewise.
  49         (VEX_LEN_0F58_P_1): Likewise.
  50         (VEX_LEN_0F58_P_3): Likewise.
  51         (VEX_LEN_0F59_P_1): Likewise.
  52         (VEX_LEN_0F59_P_3): Likewise.
  53         (VEX_LEN_0F5A_P_1): Likewise.
  54         (VEX_LEN_0F5A_P_3): Likewise.
  55         (VEX_LEN_0F5C_P_1): Likewise.
  56         (VEX_LEN_0F5C_P_3): Likewise.
  57         (VEX_LEN_0F5D_P_1): Likewise.
  58         (VEX_LEN_0F5D_P_3): Likewise.
  59         (VEX_LEN_0F5E_P_1): Likewise.
  60         (VEX_LEN_0F5E_P_3): Likewise.
  61         (VEX_LEN_0F5F_P_1): Likewise.
  62         (VEX_LEN_0F5F_P_3): Likewise.
  63         (VEX_LEN_0FC2_P_1): Likewise.
  64         (VEX_LEN_0FC2_P_3): Likewise.
  65         (VEX_LEN_0F3A0A_P_2): Likewise.
  66         (VEX_LEN_0F3A0B_P_2): Likewise.
  67         (VEX_W_0F10_P_0): Likewise.
  68         (VEX_W_0F10_P_1): Likewise.
  69         (VEX_W_0F10_P_2): Likewise.
  70         (VEX_W_0F10_P_3): Likewise.
  71         (VEX_W_0F11_P_0): Likewise.
  72         (VEX_W_0F11_P_1): Likewise.
  73         (VEX_W_0F11_P_2): Likewise.
  74         (VEX_W_0F11_P_3): Likewise.
  75         (VEX_W_0F12_P_0_M_0): Likewise.
  76         (VEX_W_0F12_P_0_M_1): Likewise.
  77         (VEX_W_0F12_P_1): Likewise.
  78         (VEX_W_0F12_P_2): Likewise.
  79         (VEX_W_0F12_P_3): Likewise.
  80         (VEX_W_0F13_M_0): Likewise.
  81         (VEX_W_0F14): Likewise.
  82         (VEX_W_0F15): Likewise.
  83         (VEX_W_0F16_P_0_M_0): Likewise.
  84         (VEX_W_0F16_P_0_M_1): Likewise.
  85         (VEX_W_0F16_P_1): Likewise.
  86         (VEX_W_0F16_P_2): Likewise.
  87         (VEX_W_0F17_M_0): Likewise.
  88         (VEX_W_0F28): Likewise.
  89         (VEX_W_0F29): Likewise.
  90         (VEX_W_0F2B_M_0): Likewise.
  91         (VEX_W_0F2E_P_0): Likewise.
  92         (VEX_W_0F2E_P_2): Likewise.
  93         (VEX_W_0F2F_P_0): Likewise.
  94         (VEX_W_0F2F_P_2): Likewise.
  95         (VEX_W_0F50_M_0): Likewise.
  96         (VEX_W_0F51_P_0): Likewise.
  97         (VEX_W_0F51_P_1): Likewise.
  98         (VEX_W_0F51_P_2): Likewise.
  99         (VEX_W_0F51_P_3): Likewise.
 100         (VEX_W_0F52_P_0): Likewise.
 101         (VEX_W_0F52_P_1): Likewise.
 102         (VEX_W_0F53_P_0): Likewise.
 103         (VEX_W_0F53_P_1): Likewise.
 104         (VEX_W_0F58_P_0): Likewise.
 105         (VEX_W_0F58_P_1): Likewise.
 106         (VEX_W_0F58_P_2): Likewise.
 107         (VEX_W_0F58_P_3): Likewise.
 108         (VEX_W_0F59_P_0): Likewise.
 109         (VEX_W_0F59_P_1): Likewise.
 110         (VEX_W_0F59_P_2): Likewise.
 111         (VEX_W_0F59_P_3): Likewise.
 112         (VEX_W_0F5A_P_0): Likewise.
 113         (VEX_W_0F5A_P_1): Likewise.
 114         (VEX_W_0F5A_P_3): Likewise.
 115         (VEX_W_0F5B_P_0): Likewise.
 116         (VEX_W_0F5B_P_1): Likewise.
 117         (VEX_W_0F5B_P_2): Likewise.
 118         (VEX_W_0F5C_P_0): Likewise.
 119         (VEX_W_0F5C_P_1): Likewise.
 120         (VEX_W_0F5C_P_2): Likewise.
 121         (VEX_W_0F5C_P_3): Likewise.
 122         (VEX_W_0F5D_P_0): Likewise.
 123         (VEX_W_0F5D_P_1): Likewise.
 124         (VEX_W_0F5D_P_2): Likewise.
 125         (VEX_W_0F5D_P_3): Likewise.
 126         (VEX_W_0F5E_P_0): Likewise.
 127         (VEX_W_0F5E_P_1): Likewise.
 128         (VEX_W_0F5E_P_2): Likewise.
 129         (VEX_W_0F5E_P_3): Likewise.
 130         (VEX_W_0F5F_P_0): Likewise.
 131         (VEX_W_0F5F_P_1): Likewise.
 132         (VEX_W_0F5F_P_2): Likewise.
 133         (VEX_W_0F5F_P_3): Likewise.
 134         (VEX_W_0F60_P_2): Likewise.
 135         (VEX_W_0F61_P_2): Likewise.
 136         (VEX_W_0F62_P_2): Likewise.
 137         (VEX_W_0F63_P_2): Likewise.
 138         (VEX_W_0F64_P_2): Likewise.
 139         (VEX_W_0F65_P_2): Likewise.
 140         (VEX_W_0F66_P_2): Likewise.
 141         (VEX_W_0F67_P_2): Likewise.
 142         (VEX_W_0F68_P_2): Likewise.
 143         (VEX_W_0F69_P_2): Likewise.
 144         (VEX_W_0F6A_P_2): Likewise.
 145         (VEX_W_0F6B_P_2): Likewise.
 146         (VEX_W_0F6C_P_2): Likewise.
 147         (VEX_W_0F6D_P_2): Likewise.
 148         (VEX_W_0F6F_P_1): Likewise.
 149         (VEX_W_0F6F_P_2): Likewise.
 150         (VEX_W_0F70_P_1): Likewise.
 151         (VEX_W_0F70_P_2): Likewise.
 152         (VEX_W_0F70_P_3): Likewise.
 153         (VEX_W_0F71_R_2_P_2): Likewise.
 154         (VEX_W_0F71_R_4_P_2): Likewise.
 155         (VEX_W_0F71_R_6_P_2): Likewise.
 156         (VEX_W_0F72_R_2_P_2): Likewise.
 157         (VEX_W_0F72_R_4_P_2): Likewise.
 158         (VEX_W_0F72_R_6_P_2): Likewise.
 159         (VEX_W_0F73_R_2_P_2): Likewise.
 160         (VEX_W_0F73_R_3_P_2): Likewise.
 161         (VEX_W_0F73_R_6_P_2): Likewise.
 162         (VEX_W_0F73_R_7_P_2): Likewise.
 163         (VEX_W_0F74_P_2): Likewise.
 164         (VEX_W_0F75_P_2): Likewise.
 165         (VEX_W_0F76_P_2): Likewise.
 166         (VEX_W_0F77_P_0): Likewise.
 167         (VEX_W_0F7C_P_2): Likewise.
 168         (VEX_W_0F7C_P_3): Likewise.
 169         (VEX_W_0F7D_P_2): Likewise.
 170         (VEX_W_0F7D_P_3): Likewise.
 171         (VEX_W_0F7E_P_1): Likewise.
 172         (VEX_W_0F7F_P_1): Likewise.
 173         (VEX_W_0F7F_P_2): Likewise.
 174         (VEX_W_0FAE_R_2_M_0): Likewise.
 175         (VEX_W_0FAE_R_3_M_0): Likewise.
 176         (VEX_W_0FC2_P_0): Likewise.
 177         (VEX_W_0FC2_P_1): Likewise.
 178         (VEX_W_0FC2_P_2): Likewise.
 179         (VEX_W_0FC2_P_3): Likewise.
 180         (VEX_W_0FD0_P_2): Likewise.
 181         (VEX_W_0FD0_P_3): Likewise.
 182         (VEX_W_0FD1_P_2): Likewise.
 183         (VEX_W_0FD2_P_2): Likewise.
 184         (VEX_W_0FD3_P_2): Likewise.
 185         (VEX_W_0FD4_P_2): Likewise.
 186         (VEX_W_0FD5_P_2): Likewise.
 187         (VEX_W_0FD6_P_2): Likewise.
 188         (VEX_W_0FD7_P_2_M_1): Likewise.
 189         (VEX_W_0FD8_P_2): Likewise.
 190         (VEX_W_0FD9_P_2): Likewise.
 191         (VEX_W_0FDA_P_2): Likewise.
 192         (VEX_W_0FDB_P_2): Likewise.
 193         (VEX_W_0FDC_P_2): Likewise.
 194         (VEX_W_0FDD_P_2): Likewise.
 195         (VEX_W_0FDE_P_2): Likewise.
 196         (VEX_W_0FDF_P_2): Likewise.
 197         (VEX_W_0FE0_P_2): Likewise.
 198         (VEX_W_0FE1_P_2): Likewise.
 199         (VEX_W_0FE2_P_2): Likewise.
 200         (VEX_W_0FE3_P_2): Likewise.
 201         (VEX_W_0FE4_P_2): Likewise.
 202         (VEX_W_0FE5_P_2): Likewise.
 203         (VEX_W_0FE6_P_1): Likewise.
 204         (VEX_W_0FE6_P_2): Likewise.
 205         (VEX_W_0FE6_P_3): Likewise.
 206         (VEX_W_0FE7_P_2_M_0): Likewise.
 207         (VEX_W_0FE8_P_2): Likewise.
 208         (VEX_W_0FE9_P_2): Likewise.
 209         (VEX_W_0FEA_P_2): Likewise.
 210         (VEX_W_0FEB_P_2): Likewise.
 211         (VEX_W_0FEC_P_2): Likewise.
 212         (VEX_W_0FED_P_2): Likewise.
 213         (VEX_W_0FEE_P_2): Likewise.
 214         (VEX_W_0FEF_P_2): Likewise.
 215         (VEX_W_0FF0_P_3_M_0): Likewise.
 216         (VEX_W_0FF1_P_2): Likewise.
 217         (VEX_W_0FF2_P_2): Likewise.
 218         (VEX_W_0FF3_P_2): Likewise.
 219         (VEX_W_0FF4_P_2): Likewise.
 220         (VEX_W_0FF5_P_2): Likewise.
 221         (VEX_W_0FF6_P_2): Likewise.
 222         (VEX_W_0FF7_P_2): Likewise.
 223         (VEX_W_0FF8_P_2): Likewise.
 224         (VEX_W_0FF9_P_2): Likewise.
 225         (VEX_W_0FFA_P_2): Likewise.
 226         (VEX_W_0FFB_P_2): Likewise.
 227         (VEX_W_0FFC_P_2): Likewise.
 228         (VEX_W_0FFD_P_2): Likewise.
 229         (VEX_W_0FFE_P_2): Likewise.
 230         (VEX_W_0F3800_P_2): Likewise.
 231         (VEX_W_0F3801_P_2): Likewise.
 232         (VEX_W_0F3802_P_2): Likewise.
 233         (VEX_W_0F3803_P_2): Likewise.
 234         (VEX_W_0F3804_P_2): Likewise.
 235         (VEX_W_0F3805_P_2): Likewise.
 236         (VEX_W_0F3806_P_2): Likewise.
 237         (VEX_W_0F3807_P_2): Likewise.
 238         (VEX_W_0F3808_P_2): Likewise.
 239         (VEX_W_0F3809_P_2): Likewise.
 240         (VEX_W_0F380A_P_2): Likewise.
 241         (VEX_W_0F380B_P_2): Likewise.
 242         (VEX_W_0F3817_P_2): Likewise.
 243         (VEX_W_0F381C_P_2): Likewise.
 244         (VEX_W_0F381D_P_2): Likewise.
 245         (VEX_W_0F381E_P_2): Likewise.
 246         (VEX_W_0F3820_P_2): Likewise.
 247         (VEX_W_0F3821_P_2): Likewise.
 248         (VEX_W_0F3822_P_2): Likewise.
 249         (VEX_W_0F3823_P_2): Likewise.
 250         (VEX_W_0F3824_P_2): Likewise.
 251         (VEX_W_0F3825_P_2): Likewise.
 252         (VEX_W_0F3828_P_2): Likewise.
 253         (VEX_W_0F3829_P_2): Likewise.
 254         (VEX_W_0F382A_P_2_M_0): Likewise.
 255         (VEX_W_0F382B_P_2): Likewise.
 256         (VEX_W_0F3830_P_2): Likewise.
 257         (VEX_W_0F3831_P_2): Likewise.
 258         (VEX_W_0F3832_P_2): Likewise.
 259         (VEX_W_0F3833_P_2): Likewise.
 260         (VEX_W_0F3834_P_2): Likewise.
 261         (VEX_W_0F3835_P_2): Likewise.
 262         (VEX_W_0F3837_P_2): Likewise.
 263         (VEX_W_0F3838_P_2): Likewise.
 264         (VEX_W_0F3839_P_2): Likewise.
 265         (VEX_W_0F383A_P_2): Likewise.
 266         (VEX_W_0F383B_P_2): Likewise.
 267         (VEX_W_0F383C_P_2): Likewise.
 268         (VEX_W_0F383D_P_2): Likewise.
 269         (VEX_W_0F383E_P_2): Likewise.
 270         (VEX_W_0F383F_P_2): Likewise.
 271         (VEX_W_0F3840_P_2): Likewise.
 272         (VEX_W_0F3841_P_2): Likewise.
 273         (VEX_W_0F38DB_P_2): Likewise.
 274         (VEX_W_0F3A08_P_2): Likewise.
 275         (VEX_W_0F3A09_P_2): Likewise.
 276         (VEX_W_0F3A0A_P_2): Likewise.
 277         (VEX_W_0F3A0B_P_2): Likewise.
 278         (VEX_W_0F3A0C_P_2): Likewise.
 279         (VEX_W_0F3A0D_P_2): Likewise.
 280         (VEX_W_0F3A0E_P_2): Likewise.
 281         (VEX_W_0F3A0F_P_2): Likewise.
 282         (VEX_W_0F3A21_P_2): Likewise.
 283         (VEX_W_0F3A40_P_2): Likewise.
 284         (VEX_W_0F3A41_P_2): Likewise.
 285         (VEX_W_0F3A42_P_2): Likewise.
 286         (VEX_W_0F3A62_P_2): Likewise.
 287         (VEX_W_0F3A63_P_2): Likewise.
 288         (VEX_W_0F3ADF_P_2): Likewise.
 289         (VEX_LEN_0F77_P_0): New.
 290         (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
 291         PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
 292         PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
 293         PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
 294         PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
 295         PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
 296         PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
 297         PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
 298         PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
 299         PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
 300         PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
 301         PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
 302         PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
 303         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
 304         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
 305         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
 306         PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
 307         PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
 308         PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
 309         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
 310         PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
 311         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
 312         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
 313         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
 314         PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
 315         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
 316         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
 317         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
 318         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
 319         PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
 320         PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
 321         PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
 322         PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
 323         PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
 324         PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
 325         PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
 326         PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
 327         PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
 328         PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
 329         PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
 330         PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
 331         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
 332         PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
 333         PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
 334         PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
 335         PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
 336         PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
 337         PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
 338         PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
 339         (vex_table): Update VEX 0F28 and 0F29 entries.
 340         (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
 341         VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
 342         VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
 343         VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
 344         VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
 345         VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
 346         VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
 347         VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
 348         VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
 349         VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
 350         VEX_LEN_0F3A0B_P_2 entries.
 351         (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
 352         VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
 353         VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
 354         VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
 355         VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
 356         VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
 357         VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
 358         VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
 359         VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
 360         VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
 361         VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
 362         VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
 363         VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
 364         VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
 365         VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
 366         VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
 367         VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
 368         VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
 369         VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
 370         VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
 371         VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
 372         VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
 373         VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
 374         VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
 375         VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
 376         VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
 377         VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
 378         VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
 379         VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
 380         VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
 381         VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
 382         VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
 383         VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
 384         VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
 385         VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
 386         VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
 387         VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
 388         VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
 389         VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
 390         VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
 391         VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
 392         VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
 393         VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
 394         VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
 395         VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
 396         VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
 397         VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
 398         VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
 399         VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
 400         VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
 401         VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
 402         VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
 403         VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
 404         VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
 405         VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
 406         VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
 407         VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
 408         VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
 409         VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
 410         VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
 411         VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
 412         VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
 413         VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
 414         VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
 415         VEX_W_0F3ADF_P_2 entries.
 416         (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
 417         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
 418         MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
 419
 420 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 421
 422         * i386-opc.tbl (VexWIG): New.
 423         Replace VexW=3 with VexWIG.
 424
 425 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 426
 427         * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
 428         * i386-tbl.h: Regenerated.
 429
 430 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 431
 432         PR gas/23665
 433         * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
 434         VEX_LEN_0FD6_P_2 entries.
 435         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
 436         * i386-tbl.h: Regenerated.
 437
 438 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 439
 440         PR gas/23642
 441         * i386-opc.h (VEXWIG): New.
 442         * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
 443         * i386-tbl.h: Regenerated.
 444
 445 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 446
 447         PR binutils/23655
 448         * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
 449         vcvtsi2sd%LQ and vcvtusi2sd%LQ.
 450         * i386-dis.c (EXxEVexR64): New.
 451         (evex_rounding_64_mode): Likewise.
 452         (OP_Rounding): Handle evex_rounding_64_mode.
 453
 454 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 455
 456         PR binutils/23655
 457         * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
 458         vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
 459         * i386-dis.c (Edqa): New.
 460         (dqa_mode): Likewise.
 461         (intel_operand_size): Handle dqa_mode as m_mode.
 462         (OP_E_register): Handle dqa_mode as dq_mode.
 463         (OP_E_memory): Set shift for dqa_mode based on address_mode.
 464
 465 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 466
 467         * i386-dis.c (OP_E_memory): Reformat.
 468
 469 2018-09-14  Jan Beulich  <jbeulich@suse.com>
 470
 471         * i386-opc.tbl (crc32): Fold byte and word forms.
 472         * i386-tbl.h: Re-generate.
 473
 474 2018-09-13  H.J. Lu  <hongjiu.lu@intel.com>
 475
 476         * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
 477         pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
 478         Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
 479         vpinsrq.  Remove VexW=1 from WIG VEX movq and vmovq.
 480         * i386-tbl.h: Regenerated.
 481
 482 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 483
 484         * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
 485         meaningless.
 486         (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
 487         xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
 488         rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
 489         * i386-tbl.h: Re-generate.
 490
 491 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 492
 493         * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
 494         AVX512_4VNNIW insns.
 495         * i386-tbl.h: Re-generate.
 496
 497 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 498
 499         * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
 500         meaningless.
 501         * i386-tbl.h: Re-generate.
 502
 503 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 504
 505         * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
 506         meaningless.
 507         * i386-tbl.h: Re-generate.
 508
 509 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 510
 511         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
 512         meaningless.
 513         * i386-tbl.h: Re-generate.
 514
 515 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 516
 517         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
 518         meaningless.
 519         * i386-tbl.h: Re-generate.
 520
 521 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 522
 523         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
 524         meaningless.
 525         * i386-tbl.h: Re-generate.
 526
 527 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 528
 529         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
 530         * i386-tbl.h: Re-generate.
 531
 532 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 533
 534         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
 535         * i386-tbl.h: Re-generate.
 536
 537 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 538
 539         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
 540         meaningless.
 541         * i386-tbl.h: Re-generate.
 542
 543 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 544
 545         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
 546         meaningless.
 547         * i386-tbl.h: Re-generate.
 548
 549 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 550
 551         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
 552         * i386-tbl.h: Re-generate.
 553
 554 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 555
 556         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
 557         * i386-tbl.h: Re-generate.
 558
 559 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 560
 561         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
 562         * i386-tbl.h: Re-generate.
 563
 564 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 565
 566         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
 567         meaningless.
 568         * i386-tbl.h: Re-generate.
 569
 570 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 571
 572         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
 573         meaningless.
 574         * i386-tbl.h: Re-generate.
 575
 576 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 577
 578         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
 579         meaningless.
 580         * i386-tbl.h: Re-generate.
 581
 582 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 583
 584         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
 585         * i386-tbl.h: Re-generate.
 586
 587 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 588
 589         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
 590         * i386-tbl.h: Re-generate.
 591
 592 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 593
 594         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
 595         * i386-tbl.h: Re-generate.
 596
 597 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 598
 599         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
 600         (vpbroadcastw, rdpid): Drop NoRex64.
 601         * i386-tbl.h: Re-generate.
 602
 603 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 604
 605         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
 606         store templates, adding D.
 607         * i386-tbl.h: Re-generate.
 608
 609 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 610
 611         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
 612         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
 613         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
 614         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
 615         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
 616         Fold load and store templates where possible, adding D. Drop
 617         IgnoreSize where it was pointlessly present. Drop redundant
 618         *word.
 619         * i386-tbl.h: Re-generate.
 620
 621 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 622
 623         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
 624         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
 625         (intel_operand_size): Handle v_bndmk_mode.
 626         (OP_E_memory): Likewise. Produce (bad) when also riprel.
 627
 628 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
 629
 630         * disassemble.c (ARCH_s12z): Define if ARCH_all.
 631
 632 2018-08-31  Kito Cheng  <kito@andestech.com>
 633
 634         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
 635         compressed floating point instructions.
 636
 637 2018-08-30  Kito Cheng  <kito@andestech.com>
 638
 639         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
 640         riscv_opcode.xlen_requirement.
 641         * riscv-opc.c (riscv_opcodes): Update for struct change.
 642
 643 2018-08-29  Martin Aberg  <maberg@gaisler.com>
 644
 645         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
 646         psr (PWRPSR) instruction.
 647
 648 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 649
 650         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
 651
 652 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 653
 654         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
 655
 656 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 657
 658         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
 659         loongson3a as an alias of gs464 for compatibility.
 660         * mips-opc.c (mips_opcodes): Change Comments.
 661
 662 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 663
 664         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
 665         option.
 666         (print_mips_disassembler_options): Document -M loongson-ext.
 667         * mips-opc.c (LEXT2): New macro.
 668         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
 669
 670 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 671
 672          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
 673          descriptors.
 674          (parse_mips_ase_option): Handle -M loongson-ext option.
 675          (print_mips_disassembler_options): Document -M loongson-ext.
 676          * mips-opc.c (IL3A): Delete.
 677          * mips-opc.c (LEXT): New macro.
 678          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
 679          instructions.
 680
 681 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 682
 683         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
 684         descriptors.
 685         (parse_mips_ase_option): Handle -M loongson-cam option.
 686         (print_mips_disassembler_options): Document -M loongson-cam.
 687         * mips-opc.c (LCAM): New macro.
 688         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
 689         instructions.
 690
 691 2018-08-21  Alan Modra  <amodra@gmail.com>
 692
 693         * ppc-dis.c (operand_value_powerpc): Init "invalid".
 694         (skip_optional_operands): Count optional operands, and update
 695         ppc_optional_operand_value call.
 696         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
 697         (extract_vlensi): Likewise.
 698         (extract_fxm): Return default value for missing optional operand.
 699         (extract_ls, extract_raq, extract_tbr): Likewise.
 700         (insert_sxl, extract_sxl): New functions.
 701         (insert_esync, extract_esync): Remove Power9 handling and simplify.
 702         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
 703         flag and extra entry.
 704         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
 705         extract_sxl.
 706
 707 2018-08-20  Alan Modra  <amodra@gmail.com>
 708
 709         * sh-opc.h (MASK): Simplify.
 710
 711 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 712
 713         * s12z-dis.c (bm_decode): Deal with cases where the mode is
 714         BM_RESERVED0 or BM_RESERVED1
 715         (bm_rel_decode, bm_n_bytes): Ditto.
 716
 717 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 718
 719         * s12z.h: Delete.
 720
 721 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
 722
 723         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
 724         address with the addr32 prefix and without base nor index
 725         registers.
 726
 727 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
 728
 729         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
 730         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
 731         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
 732         (cpu_flags): Add CpuCMOV and CpuFXSR.
 733         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
 734         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
 735         * i386-init.h: Regenerated.
 736         * i386-tbl.h: Likewise.
 737
 738 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
 739
 740         * arc-regs.h: Update auxiliary registers.
 741
 742 2018-08-06  Jan Beulich  <jbeulich@suse.com>
 743
 744         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
 745         (RegIP, RegIZ): Define.
 746         * i386-reg.tbl: Adjust comments.
 747         (rip): Use Qword instead of BaseIndex. Use RegIP.
 748         (eip): Use Dword instead of BaseIndex. Use RegIP.
 749         (riz): Add Qword. Use RegIZ.
 750         (eiz): Add Dword. Use RegIZ.
 751         * i386-tbl.h: Re-generate.
 752
 753 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 754
 755         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
 756         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
 757         vpmovzxdq, vpmovzxwd): Remove NoRex64.
 758         * i386-tbl.h: Re-generate.
 759
 760 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 761
 762         * i386-gen.c (operand_types): Remove Mem field.
 763         * i386-opc.h (union i386_operand_type): Remove mem field.
 764         * i386-init.h, i386-tbl.h: Re-generate.
 765
 766 2018-08-01  Alan Modra  <amodra@gmail.com>
 767
 768         * po/POTFILES.in: Regenerate.
 769
 770 2018-07-31  Nick Clifton  <nickc@redhat.com>
 771
 772         * po/sv.po: Updated Swedish translation.
 773
 774 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 775
 776         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
 777         * i386-init.h, i386-tbl.h: Re-generate.
 778
 779 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 780
 781         * i386-opc.h (ZEROING_MASKING) Rename to ...
 782         (DYNAMIC_MASKING): ... this. Adjust comment.
 783         * i386-opc.tbl (MaskingMorZ): Define.
 784         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
 785         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
 786         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
 787         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
 788         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
 789         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
 790         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
 791         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
 792         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
 793
 794 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 795
 796         * i386-opc.tbl: Use element rather than vector size for AVX512*
 797         scatter/gather insns.
 798         * i386-tbl.h: Re-generate.
 799
 800 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 801
 802         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
 803         (cpu_flags): Drop CpuVREX.
 804         * i386-opc.h (CpuVREX): Delete.
 805         (union i386_cpu_flags): Remove cpuvrex.
 806         * i386-init.h, i386-tbl.h: Re-generate.
 807
 808 2018-07-30  Jim Wilson  <jimw@sifive.com>
 809
 810         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
 811         fields.
 812         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
 813
 814 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
 815
 816         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
 817         * Makefile.in: Regenerated.
 818         * configure.ac: Add C-SKY.
 819         * configure: Regenerated.
 820         * csky-dis.c: New file.
 821         * csky-opc.h: New file.
 822         * disassemble.c (ARCH_csky): Define.
 823         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
 824         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
 825
 826 2018-07-27  Alan Modra  <amodra@gmail.com>
 827
 828         * ppc-opc.c (insert_sprbat): Correct function parameter and
 829         return type.
 830         (extract_sprbat): Likewise, variable too.
 831
 832 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
 833             Alan Modra  <amodra@gmail.com>
 834
 835         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
 836         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
 837         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
 838         support disjointed BAT.
 839         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
 840         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
 841         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
 842
 843 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
 844             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 845
 846         * i386-gen.c (adjust_broadcast_modifier): New function.
 847         (process_i386_opcode_modifier): Add an argument for operands.
 848         Adjust the Broadcast value based on operands.
 849         (output_i386_opcode): Pass operand_types to
 850         process_i386_opcode_modifier.
 851         (process_i386_opcodes): Pass NULL as operands to
 852         process_i386_opcode_modifier.
 853         * i386-opc.h (BYTE_BROADCAST): New.
 854         (WORD_BROADCAST): Likewise.
 855         (DWORD_BROADCAST): Likewise.
 856         (QWORD_BROADCAST): Likewise.
 857         (i386_opcode_modifier): Expand broadcast to 3 bits.
 858         * i386-tbl.h: Regenerated.
 859
 860 2018-07-24  Alan Modra  <amodra@gmail.com>
 861
 862         PR 23430
 863         * or1k-desc.h: Regenerate.
 864
 865 2018-07-24  Jan Beulich  <jbeulich@suse.com>
 866
 867         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
 868         vcvtusi2ss, and vcvtusi2sd.
 869         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
 870         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
 871         * i386-tbl.h: Re-generate.
 872
 873 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 874
 875         * arc-opc.c (extract_w6): Fix extending the sign.
 876
 877 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 878
 879         * arc-tbl.h (vewt): Allow it for ARC EM family.
 880
 881 2018-07-23  Alan Modra  <amodra@gmail.com>
 882
 883         PR 23419
 884         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
 885         opcode variants for mtspr/mfspr encodings.
 886
 887 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 888             Maciej W. Rozycki  <macro@mips.com>
 889
 890         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
 891         loongson3a descriptors.
 892         (parse_mips_ase_option): Handle -M loongson-mmi option.
 893         (print_mips_disassembler_options): Document -M loongson-mmi.
 894         * mips-opc.c (LMMI): New macro.
 895         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
 896         instructions.
 897
 898 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 899
 900         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 901         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
 902         IgnoreSize and [XYZ]MMword where applicable.
 903         * i386-tbl.h: Re-generate.
 904
 905 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 906
 907         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
 908         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
 909         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
 910         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
 911         * i386-tbl.h: Re-generate.
 912
 913 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 914
 915         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
 916         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
 917         VPCLMULQDQ templates into their respective AVX512VL counterparts
 918         where possible, using Disp8ShiftVL and CheckRegSize instead of
 919         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
 920         * i386-tbl.h: Re-generate.
 921
 922 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 923
 924         * i386-opc.tbl: Fold AVX512DQ templates into their respective
 925         AVX512VL counterparts where possible, using Disp8ShiftVL and
 926         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 927         IgnoreSize) as appropriate.
 928         * i386-tbl.h: Re-generate.
 929
 930 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 931
 932         * i386-opc.tbl: Fold AVX512BW templates into their respective
 933         AVX512VL counterparts where possible, using Disp8ShiftVL and
 934         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 935         IgnoreSize) as appropriate.
 936         * i386-tbl.h: Re-generate.
 937
 938 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 939
 940         * i386-opc.tbl: Fold AVX512CD templates into their respective
 941         AVX512VL counterparts where possible, using Disp8ShiftVL and
 942         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 943         IgnoreSize) as appropriate.
 944         * i386-tbl.h: Re-generate.
 945
 946 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 947
 948         * i386-opc.h (DISP8_SHIFT_VL): New.
 949         * i386-opc.tbl (Disp8ShiftVL):  Define.
 950         (various): Fold AVX512VL templates into their respective
 951         AVX512F counterparts where possible, using Disp8ShiftVL and
 952         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 953         IgnoreSize) as appropriate.
 954         * i386-tbl.h: Re-generate.
 955
 956 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 957
 958         * Makefile.am: Change dependencies and rule for
 959         $(srcdir)/i386-init.h.
 960         * Makefile.in: Re-generate.
 961         * i386-gen.c (process_i386_opcodes): New local variable
 962         "marker". Drop opening of input file. Recognize marker and line
 963         number directives.
 964         * i386-opc.tbl (OPCODE_I386_H): Define.
 965         (i386-opc.h): Include it.
 966         (None): Undefine.
 967
 968 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 969
 970         PR gas/23418
 971         * i386-opc.h (Byte): Update comments.
 972         (Word): Likewise.
 973         (Dword): Likewise.
 974         (Fword): Likewise.
 975         (Qword): Likewise.
 976         (Tbyte): Likewise.
 977         (Xmmword): Likewise.
 978         (Ymmword): Likewise.
 979         (Zmmword): Likewise.
 980         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 981         vcvttps2uqq.
 982         * i386-tbl.h: Regenerated.
 983
 984 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 985
 986         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 987         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 988         * aarch64-asm-2.c: Regenerate.
 989         * aarch64-dis-2.c: Regenerate.
 990         * aarch64-opc-2.c: Regenerate.
 991
 992 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 993
 994         PR binutils/23192
 995         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 996         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 997         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 998         sqdmulh, sqrdmulh): Use Em16.
 999
1000 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
1001
1002         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1003         csdb together with them.
1004         (thumb32_opcodes): Likewise.
1005
1006 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1007
1008         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1009         requiring 32-bit registers as operands 2 and 3. Improve
1010         comments.
1011         (mwait, mwaitx): Fold templates. Improve comments.
1012         OPERAND_TYPE_INOUTPORTREG.
1013         * i386-tbl.h: Re-generate.
1014
1015 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1016
1017         * i386-gen.c (operand_type_init): Remove
1018         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1019         OPERAND_TYPE_INOUTPORTREG.
1020         * i386-init.h: Re-generate.
1021
1022 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1023
1024         * i386-opc.tbl (wrssd, wrussd): Add Dword.
1025         (wrssq, wrussq): Add Qword.
1026         * i386-tbl.h: Re-generate.
1027
1028 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1029
1030         * i386-opc.h: Rename OTMax to OTNum.
1031         (OTNumOfUints): Adjust calculation.
1032         (OTUnused): Directly alias to OTNum.
1033
1034 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
1035
1036         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1037         `reg_xys'.
1038         (lea_reg_xys): Likewise.
1039         (print_insn_loop_primitive): Rename `reg' local variable to
1040         `reg_dxy'.
1041
1042 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1043
1044         PR binutils/23242
1045         * aarch64-tbl.h (ldarh): Fix disassembly mask.
1046
1047 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1048
1049         PR binutils/23369
1050         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1051         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1052
1053 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
1054
1055         PR tdep/8282
1056         * mips-dis.c (mips_option_arg_t): New enumeration.
1057         (mips_options): New variable.
1058         (disassembler_options_mips): New function.
1059         (print_mips_disassembler_options): Reimplement in terms of
1060         `disassembler_options_mips'.
1061         * arm-dis.c (disassembler_options_arm): Adapt to using the
1062         `disasm_options_and_args_t' structure.
1063         * ppc-dis.c (disassembler_options_powerpc): Likewise.
1064         * s390-dis.c (disassembler_options_s390): Likewise.
1065
1066 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1067
1068         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1069         expected result.
1070         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1071         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1072         * testsuite/ld-arm/tls-longplt.d: Likewise.
1073
1074 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
1075
1076         PR binutils/23192
1077         * aarch64-asm-2.c: Regenerate.
1078         * aarch64-dis-2.c: Likewise.
1079         * aarch64-opc-2.c: Likewise.
1080         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1081         * aarch64-opc.c (operand_general_constraint_met_p,
1082         aarch64_print_operand): Likewise.
1083         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1084         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1085         fmlal2, fmlsl2.
1086         (AARCH64_OPERANDS): Add Em2.
1087
1088 2018-06-26  Nick Clifton  <nickc@redhat.com>
1089
1090         * po/uk.po: Updated Ukranian translation.
1091         * po/de.po: Updated German translation.
1092         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1093
1094 2018-06-26  Nick Clifton  <nickc@redhat.com>
1095
1096         * nfp-dis.c: Fix spelling mistake.
1097
1098 2018-06-24  Nick Clifton  <nickc@redhat.com>
1099
1100         * configure: Regenerate.
1101         * po/opcodes.pot: Regenerate.
1102
1103 2018-06-24  Nick Clifton  <nickc@redhat.com>
1104
1105         2.31 branch created.
1106
1107 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
1108
1109         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1110         * aarch64-asm-2.c: Regenerate.
1111         * aarch64-dis-2.c: Likewise.
1112
1113 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
1114
1115         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1116         `-M ginv' option description.
1117
1118 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
1119
1120         PR gas/23305
1121         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1122         la and lla.
1123
1124 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
1125
1126         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1127         * configure.ac: Remove AC_PREREQ.
1128         * Makefile.in: Re-generate.
1129         * aclocal.m4: Re-generate.
1130         * configure: Re-generate.
1131
1132 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1133
1134         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1135         mips64r6 descriptors.
1136         (parse_mips_ase_option): Handle -Mginv option.
1137         (print_mips_disassembler_options): Document -Mginv.
1138         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1139         (GINV): New macro.
1140         (mips_opcodes): Define ginvi and ginvt.
1141
1142 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
1143             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1144
1145         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1146         * mips-opc.c (CRC, CRC64): New macros.
1147         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1148         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
1149         crc32cd for CRC64.
1150
1151 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
1152
1153         PR 20319
1154         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1155         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1156
1157 2018-06-06  Alan Modra  <amodra@gmail.com>
1158
1159         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1160         setjmp.  Move init for some other vars later too.
1161
1162 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
1163
1164         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1165         (dis_private): Add new fields for property section tracking.
1166         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1167         (xtensa_instruction_fits): New functions.
1168         (fetch_data): Bump minimal fetch size to 4.
1169         (print_insn_xtensa): Make struct dis_private static.
1170         Load and prepare property table on section change.
1171         Don't disassemble literals. Don't disassemble instructions that
1172         cross property table boundaries.
1173
1174 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
1175
1176         * configure: Regenerated.
1177
1178 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1179
1180         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1181         * i386-tbl.h: Re-generate.
1182
1183 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1184
1185         * i386-opc.tbl (sldt, str): Add NoRex64.
1186         * i386-tbl.h: Re-generate.
1187
1188 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1189
1190         * i386-opc.tbl (invpcid): Add Oword.
1191         * i386-tbl.h: Re-generate.
1192
1193 2018-06-01  Alan Modra  <amodra@gmail.com>
1194
1195         * sysdep.h (_bfd_error_handler): Don't declare.
1196         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
1197         * rl78-decode.opc: Likewise.
1198         * msp430-decode.c: Regenerate.
1199         * rl78-decode.c: Regenerate.
1200
1201 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
1202
1203         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1204         * i386-init.h : Regenerated.
1205
1206 2018-05-25  Alan Modra  <amodra@gmail.com>
1207
1208         * Makefile.in: Regenerate.
1209         * po/POTFILES.in: Regenerate.
1210
1211 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
1212
1213         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1214         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1215         (insert_bab, extract_bab, insert_btab, extract_btab,
1216         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1217         (BAT, BBA VBA RBS XB6S): Delete macros.
1218         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1219         (BB, BD, RBX, XC6): Update for new macros.
1220         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1221         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1222         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1223         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1224
1225 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
1226
1227         * Makefile.am: Add support for s12z architecture.
1228         * configure.ac: Likewise.
1229         * disassemble.c: Likewise.
1230         * disassemble.h: Likewise.
1231         * Makefile.in: Regenerate.
1232         * configure: Regenerate.
1233         * s12z-dis.c: New file.
1234         * s12z.h: New file.
1235
1236 2018-05-18  Alan Modra  <amodra@gmail.com>
1237
1238         * nfp-dis.c: Don't #include libbfd.h.
1239         (init_nfp3200_priv): Use bfd_get_section_contents.
1240         (nit_nfp6000_mecsr_sec): Likewise.
1241
1242 2018-05-17  Nick Clifton  <nickc@redhat.com>
1243
1244         * po/zh_CN.po: Updated simplified Chinese translation.
1245
1246 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
1247
1248         PR binutils/23109
1249         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1250         * aarch64-dis-2.c: Regenerate.
1251
1252 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1253
1254         PR binutils/21446
1255         * aarch64-asm.c (opintl.h): Include.
1256         (aarch64_ins_sysreg): Enforce read/write constraints.
1257         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1258         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1259         (F_REG_READ, F_REG_WRITE): New.
1260         * aarch64-opc.c (aarch64_print_operand): Generate notes for
1261         AARCH64_OPND_SYSREG.
1262         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1263         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1264         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1265         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1266         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1267         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1268         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1269         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1270         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1271         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1272         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1273         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1274         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1275         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1276         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1277         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1278         msr (F_SYS_WRITE), mrs (F_SYS_READ).
1279
1280 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1281
1282         PR binutils/21446
1283         * aarch64-dis.c (no_notes: New.
1284         (parse_aarch64_dis_option): Support notes.
1285         (aarch64_decode_insn, print_operands): Likewise.
1286         (print_aarch64_disassembler_options): Document notes.
1287         * aarch64-opc.c (aarch64_print_operand): Support notes.
1288
1289 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1290
1291         PR binutils/21446
1292         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1293         and take error struct.
1294         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1295         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1296         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1297         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1298         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1299         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1300         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1301         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1302         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1303         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1304         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1305         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1306         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1307         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1308         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1309         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1310         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1311         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1312         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1313         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1314         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1315         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1316         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1317         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1318         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1319         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1320         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1321         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1322         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1323         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1324         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1325         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1326         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1327         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1328         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1329         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1330         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1331         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1332         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1333         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1334         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1335         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1336         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1337         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1338         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1339         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1340         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1341         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1342         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1343         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1344         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1345         (determine_disassembling_preference, aarch64_decode_insn,
1346         print_insn_aarch64_word, print_insn_data): Take errors struct.
1347         (print_insn_aarch64): Use errors.
1348         * aarch64-asm-2.c: Regenerate.
1349         * aarch64-dis-2.c: Regenerate.
1350         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1351         boolean in aarch64_insert_operan.
1352         (print_operand_extractor): Likewise.
1353         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1354
1355 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
1356
1357         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1358
1359 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
1360
1361         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1362
1363 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
1364
1365         * cr16-opc.c (cr16_instruction): Comment typo fix.
1366         * hppa-dis.c (print_insn_hppa): Likewise.
1367
1368 2018-05-08  Jim Wilson  <jimw@sifive.com>
1369
1370         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1371         (match_c_slli64, match_srxi_as_c_srxi): New.
1372         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1373         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1374         <c.slli, c.srli, c.srai>: Use match_s_slli.
1375         <c.slli64, c.srli64, c.srai64>: New.
1376
1377 2018-05-08  Alan Modra  <amodra@gmail.com>
1378
1379         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1380         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1381         partition opcode space for index lookup.
1382
1383 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1384
1385         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1386         <insn_length>: ...with this.  Update usage.
1387         Remove duplicate call to *info->memory_error_func.
1388
1389 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1390             H.J. Lu  <hongjiu.lu@intel.com>
1391
1392         * i386-dis.c (Gva): New.
1393         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1394         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1395         (prefix_table): New instructions (see prefix above).
1396         (mod_table): New instructions (see prefix above).
1397         (OP_G): Handle va_mode.
1398         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1399         CPU_MOVDIR64B_FLAGS.
1400         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1401         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1402         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1403         * i386-opc.tbl: Add movidir{i,64b}.
1404         * i386-init.h: Regenerated.
1405         * i386-tbl.h: Likewise.
1406
1407 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
1408
1409         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1410         AddrPrefixOpReg.
1411         * i386-opc.h (AddrPrefixOp0): Renamed to ...
1412         (AddrPrefixOpReg): This.
1413         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1414         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1415
1416 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1417
1418         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1419         (vle_num_opcodes): Likewise.
1420         (spe2_num_opcodes): Likewise.
1421         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1422         initialization loop.
1423         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1424         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
1425         only once.
1426
1427 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
1428
1429         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1430
1431 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
1432
1433         Makefile.am: Added nfp-dis.c.
1434         configure.ac: Added bfd_nfp_arch.
1435         disassemble.h: Added print_insn_nfp prototype.
1436         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1437         nfp-dis.c: New, for NFP support.
1438         po/POTFILES.in: Added nfp-dis.c to the list.
1439         Makefile.in: Regenerate.
1440         configure: Regenerate.
1441
1442 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1443
1444         * i386-opc.tbl: Fold various non-memory operand AVX512VL
1445         templates into their base ones.
1446         * i386-tlb.h: Re-generate.
1447
1448 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1449
1450         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1451         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1452         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1453         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1454         * i386-init.h: Re-generate.
1455
1456 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1457
1458         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1459         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1460         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1461         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1462         comment.
1463         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1464         and CpuRegMask.
1465         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1466         CpuRegMask: Delete.
1467         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1468         cpuregzmm, and cpuregmask.
1469         * i386-init.h: Re-generate.
1470         * i386-tbl.h: Re-generate.
1471
1472 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1473
1474         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1475         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1476         * i386-init.h: Re-generate.
1477
1478 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1479
1480         * i386-gen.c (VexImmExt): Delete.
1481         * i386-opc.h (VexImmExt, veximmext): Delete.
1482         * i386-opc.tbl: Drop all VexImmExt uses.
1483         * i386-tlb.h: Re-generate.
1484
1485 2018-04-25  Jan Beulich  <jbeulich@suse.com>
1486
1487         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1488         register-only forms.
1489         * i386-tlb.h: Re-generate.
1490
1491 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
1492
1493         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1494
1495 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1496
1497         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1498         PREFIX_0F1C.
1499         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1500         (cpu_flags): Add CpuCLDEMOTE.
1501         * i386-init.h: Regenerate.
1502         * i386-opc.h (enum): Add CpuCLDEMOTE,
1503         (i386_cpu_flags): Add cpucldemote.
1504         * i386-opc.tbl: Add cldemote.
1505         * i386-tbl.h: Regenerate.
1506
1507 2018-04-16  Alan Modra  <amodra@gmail.com>
1508
1509         * Makefile.am: Remove sh5 and sh64 support.
1510         * configure.ac: Likewise.
1511         * disassemble.c: Likewise.
1512         * disassemble.h: Likewise.
1513         * sh-dis.c: Likewise.
1514         * sh64-dis.c: Delete.
1515         * sh64-opc.c: Delete.
1516         * sh64-opc.h: Delete.
1517         * Makefile.in: Regenerate.
1518         * configure: Regenerate.
1519         * po/POTFILES.in: Regenerate.
1520
1521 2018-04-16  Alan Modra  <amodra@gmail.com>
1522
1523         * Makefile.am: Remove w65 support.
1524         * configure.ac: Likewise.
1525         * disassemble.c: Likewise.
1526         * disassemble.h: Likewise.
1527         * w65-dis.c: Delete.
1528         * w65-opc.h: Delete.
1529         * Makefile.in: Regenerate.
1530         * configure: Regenerate.
1531         * po/POTFILES.in: Regenerate.
1532
1533 2018-04-16  Alan Modra  <amodra@gmail.com>
1534
1535         * configure.ac: Remove we32k support.
1536         * configure: Regenerate.
1537
1538 2018-04-16  Alan Modra  <amodra@gmail.com>
1539
1540         * Makefile.am: Remove m88k support.
1541         * configure.ac: Likewise.
1542         * disassemble.c: Likewise.
1543         * disassemble.h: Likewise.
1544         * m88k-dis.c: Delete.
1545         * Makefile.in: Regenerate.
1546         * configure: Regenerate.
1547         * po/POTFILES.in: Regenerate.
1548
1549 2018-04-16  Alan Modra  <amodra@gmail.com>
1550
1551         * Makefile.am: Remove i370 support.
1552         * configure.ac: Likewise.
1553         * disassemble.c: Likewise.
1554         * disassemble.h: Likewise.
1555         * i370-dis.c: Delete.
1556         * i370-opc.c: Delete.
1557         * Makefile.in: Regenerate.
1558         * configure: Regenerate.
1559         * po/POTFILES.in: Regenerate.
1560
1561 2018-04-16  Alan Modra  <amodra@gmail.com>
1562
1563         * Makefile.am: Remove h8500 support.
1564         * configure.ac: Likewise.
1565         * disassemble.c: Likewise.
1566         * disassemble.h: Likewise.
1567         * h8500-dis.c: Delete.
1568         * h8500-opc.h: Delete.
1569         * Makefile.in: Regenerate.
1570         * configure: Regenerate.
1571         * po/POTFILES.in: Regenerate.
1572
1573 2018-04-16  Alan Modra  <amodra@gmail.com>
1574
1575         * configure.ac: Remove tahoe support.
1576         * configure: Regenerate.
1577
1578 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1579
1580         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1581         umwait.
1582         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1583         64-bit mode.
1584         * i386-tbl.h: Regenerated.
1585
1586 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1587
1588         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1589         PREFIX_MOD_1_0FAE_REG_6.
1590         (va_mode): New.
1591         (OP_E_register): Use va_mode.
1592         * i386-dis-evex.h (prefix_table):
1593         New instructions (see prefixes above).
1594         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1595         (cpu_flags): Likewise.
1596         * i386-opc.h (enum): Likewise.
1597         (i386_cpu_flags): Likewise.
1598         * i386-opc.tbl: Add umonitor, umwait, tpause.
1599         * i386-init.h: Regenerate.
1600         * i386-tbl.h: Likewise.
1601
1602 2018-04-11  Alan Modra  <amodra@gmail.com>
1603
1604         * opcodes/i860-dis.c: Delete.
1605         * opcodes/i960-dis.c: Delete.
1606         * Makefile.am: Remove i860 and i960 support.
1607         * configure.ac: Likewise.
1608         * disassemble.c: Likewise.
1609         * disassemble.h: Likewise.
1610         * Makefile.in: Regenerate.
1611         * configure: Regenerate.
1612         * po/POTFILES.in: Regenerate.
1613
1614 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1615
1616         PR binutils/23025
1617         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1618         to 0.
1619         (print_insn): Clear vex instead of vex.evex.
1620
1621 2018-04-04  Nick Clifton  <nickc@redhat.com>
1622
1623         * po/es.po: Updated Spanish translation.
1624
1625 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1626
1627         * i386-gen.c (opcode_modifiers): Delete VecESize.
1628         * i386-opc.h (VecESize): Delete.
1629         (struct i386_opcode_modifier): Delete vecesize.
1630         * i386-opc.tbl: Drop VecESize.
1631         * i386-tlb.h: Re-generate.
1632
1633 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1634
1635         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1636         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1637         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1638         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1639         * i386-tlb.h: Re-generate.
1640
1641 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1642
1643         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1644         Fold AVX512 forms
1645         * i386-tlb.h: Re-generate.
1646
1647 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1648
1649         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1650         (vex_len_table): Drop Y for vcvt*2si.
1651         (putop): Replace plain 'Y' handling by abort().
1652
1653 2018-03-28  Nick Clifton  <nickc@redhat.com>
1654
1655         PR 22988
1656         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1657         instructions with only a base address register.
1658         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1659         handle AARHC64_OPND_SVE_ADDR_R.
1660         (aarch64_print_operand): Likewise.
1661         * aarch64-asm-2.c: Regenerate.
1662         * aarch64_dis-2.c: Regenerate.
1663         * aarch64-opc-2.c: Regenerate.
1664
1665 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1666
1667         * i386-opc.tbl: Drop VecESize from register only insn forms and
1668         memory forms not allowing broadcast.
1669         * i386-tlb.h: Re-generate.
1670
1671 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1672
1673         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1674         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1675         sha256*): Drop Disp<N>.
1676
1677 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1678
1679         * i386-dis.c (EbndS, bnd_swap_mode): New.
1680         (prefix_table): Use EbndS.
1681         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1682         * i386-opc.tbl (bndmov): Move misplaced Load.
1683         * i386-tlb.h: Re-generate.
1684
1685 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1686
1687         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1688         templates allowing memory operands and folded ones for register
1689         only flavors.
1690         * i386-tlb.h: Re-generate.
1691
1692 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1693
1694         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1695         256-bit templates. Drop redundant leftover Disp<N>.
1696         * i386-tlb.h: Re-generate.
1697
1698 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1699
1700         * riscv-opc.c (riscv_insn_types): New.
1701
1702 2018-03-13  Nick Clifton  <nickc@redhat.com>
1703
1704         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1705
1706 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1707
1708         * i386-opc.tbl: Add Optimize to clr.
1709         * i386-tbl.h: Regenerated.
1710
1711 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1712
1713         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1714         * i386-opc.h (OldGcc): Removed.
1715         (i386_opcode_modifier): Remove oldgcc.
1716         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1717         instructions for old (<= 2.8.1) versions of gcc.
1718         * i386-tbl.h: Regenerated.
1719
1720 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1721
1722         * i386-opc.h (EVEXDYN): New.
1723         * i386-opc.tbl: Fold various AVX512VL templates.
1724         * i386-tlb.h: Re-generate.
1725
1726 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1727
1728         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1729         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1730         vpexpandd, vpexpandq): Fold AFX512VF templates.
1731         * i386-tlb.h: Re-generate.
1732
1733 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1734
1735         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1736         Fold 128- and 256-bit VEX-encoded templates.
1737         * i386-tlb.h: Re-generate.
1738
1739 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1740
1741         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1742         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1743         vpexpandd, vpexpandq): Fold AVX512F templates.
1744         * i386-tlb.h: Re-generate.
1745
1746 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1747
1748         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1749         64-bit templates. Drop Disp<N>.
1750         * i386-tlb.h: Re-generate.
1751
1752 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1753
1754         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1755         and 256-bit templates.
1756         * i386-tlb.h: Re-generate.
1757
1758 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1759
1760         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1761         * i386-tlb.h: Re-generate.
1762
1763 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1764
1765         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1766         Drop NoAVX.
1767         * i386-tlb.h: Re-generate.
1768
1769 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1770
1771         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1772         * i386-tlb.h: Re-generate.
1773
1774 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1775
1776         * i386-gen.c (opcode_modifiers): Delete FloatD.
1777         * i386-opc.h (FloatD): Delete.
1778         (struct i386_opcode_modifier): Delete floatd.
1779         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1780         FloatD by D.
1781         * i386-tlb.h: Re-generate.
1782
1783 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1784
1785         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1786
1787 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1788
1789         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1790         * i386-tlb.h: Re-generate.
1791
1792 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1793
1794         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1795         forms.
1796         * i386-tlb.h: Re-generate.
1797
1798 2018-03-07  Alan Modra  <amodra@gmail.com>
1799
1800         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1801         bfd_arch_rs6000.
1802         * disassemble.h (print_insn_rs6000): Delete.
1803         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1804         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1805         (print_insn_rs6000): Delete.
1806
1807 2018-03-03  Alan Modra  <amodra@gmail.com>
1808
1809         * sysdep.h (opcodes_error_handler): Define.
1810         (_bfd_error_handler): Declare.
1811         * Makefile.am: Remove stray #.
1812         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1813         EDIT" comment.
1814         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1815         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1816         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1817         opcodes_error_handler to print errors.  Standardize error messages.
1818         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1819         and include opintl.h.
1820         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1821         * i386-gen.c: Standardize error messages.
1822         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1823         * Makefile.in: Regenerate.
1824         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1825         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1826         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1827         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1828         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1829         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1830         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1831         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1832         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1833         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1834         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1835         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1836         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1837
1838 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1839
1840         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1841         vpsub[bwdq] instructions.
1842         * i386-tbl.h: Regenerated.
1843
1844 2018-03-01  Alan Modra  <amodra@gmail.com>
1845
1846         * configure.ac (ALL_LINGUAS): Sort.
1847         * configure: Regenerate.
1848
1849 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1850
1851         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1852         macro by assignements.
1853
1854 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1855
1856         PR gas/22871
1857         * i386-gen.c (opcode_modifiers): Add Optimize.
1858         * i386-opc.h (Optimize): New enum.
1859         (i386_opcode_modifier): Add optimize.
1860         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1861         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1862         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1863         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1864         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1865         vpxord and vpxorq.
1866         * i386-tbl.h: Regenerated.
1867
1868 2018-02-26  Alan Modra  <amodra@gmail.com>
1869
1870         * crx-dis.c (getregliststring): Allocate a large enough buffer
1871         to silence false positive gcc8 warning.
1872
1873 2018-02-22  Shea Levy <shea@shealevy.com>
1874
1875         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1876
1877 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1878
1879         * i386-opc.tbl: Add {rex},
1880         * i386-tbl.h: Regenerated.
1881
1882 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1883
1884         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1885         (mips16_opcodes): Replace `M' with `m' for "restore".
1886
1887 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1888
1889         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1890
1891 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1892
1893         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1894         variable to `function_index'.
1895
1896 2018-02-13  Nick Clifton  <nickc@redhat.com>
1897
1898         PR 22823
1899         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1900         about truncation of printing.
1901
1902 2018-02-12  Henry Wong <henry@stuffedcow.net>
1903
1904         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1905
1906 2018-02-05  Nick Clifton  <nickc@redhat.com>
1907
1908         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1909
1910 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1911
1912         * i386-dis.c (enum): Add pconfig.
1913         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1914         (cpu_flags): Add CpuPCONFIG.
1915         * i386-opc.h (enum): Add CpuPCONFIG.
1916         (i386_cpu_flags): Add cpupconfig.
1917         * i386-opc.tbl: Add PCONFIG instruction.
1918         * i386-init.h: Regenerate.
1919         * i386-tbl.h: Likewise.
1920
1921 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1922
1923         * i386-dis.c (enum): Add PREFIX_0F09.
1924         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1925         (cpu_flags): Add CpuWBNOINVD.
1926         * i386-opc.h (enum): Add CpuWBNOINVD.
1927         (i386_cpu_flags): Add cpuwbnoinvd.
1928         * i386-opc.tbl: Add WBNOINVD instruction.
1929         * i386-init.h: Regenerate.
1930         * i386-tbl.h: Likewise.
1931
1932 2018-01-17  Jim Wilson  <jimw@sifive.com>
1933
1934         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1935
1936 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1937
1938         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1939         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1940         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1941         (cpu_flags): Add CpuIBT, CpuSHSTK.
1942         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1943         (i386_cpu_flags): Add cpuibt, cpushstk.
1944         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1945         * i386-init.h: Regenerate.
1946         * i386-tbl.h: Likewise.
1947
1948 2018-01-16  Nick Clifton  <nickc@redhat.com>
1949
1950         * po/pt_BR.po: Updated Brazilian Portugese translation.
1951         * po/de.po: Updated German translation.
1952
1953 2018-01-15  Jim Wilson  <jimw@sifive.com>
1954
1955         * riscv-opc.c (match_c_nop): New.
1956         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1957
1958 2018-01-15  Nick Clifton  <nickc@redhat.com>
1959
1960         * po/uk.po: Updated Ukranian translation.
1961
1962 2018-01-13  Nick Clifton  <nickc@redhat.com>
1963
1964         * po/opcodes.pot: Regenerated.
1965
1966 2018-01-13  Nick Clifton  <nickc@redhat.com>
1967
1968         * configure: Regenerate.
1969
1970 2018-01-13  Nick Clifton  <nickc@redhat.com>
1971
1972         2.30 branch created.
1973
1974 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1975
1976         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1977         * i386-tbl.h: Regenerate.
1978
1979 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1980
1981         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1982         * i386-tbl.h: Re-generate.
1983
1984 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1985
1986         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1987         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1988         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1989         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1990         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1991         Disp8MemShift of AVX512VL forms.
1992         * i386-tbl.h: Re-generate.
1993
1994 2018-01-09  Jim Wilson  <jimw@sifive.com>
1995
1996         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1997         then the hi_addr value is zero.
1998
1999 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2000
2001         * arm-dis.c (arm_opcodes): Add csdb.
2002         (thumb32_opcodes): Add csdb.
2003
2004 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2005
2006         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2007         * aarch64-asm-2.c: Regenerate.
2008         * aarch64-dis-2.c: Regenerate.
2009         * aarch64-opc-2.c: Regenerate.
2010
2011 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
2012
2013         PR gas/22681
2014         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2015         Remove AVX512 vmovd with 64-bit operands.
2016         * i386-tbl.h: Regenerated.
2017
2018 2018-01-05  Jim Wilson  <jimw@sifive.com>
2019
2020         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2021         jalr.
2022
2023 2018-01-03  Alan Modra  <amodra@gmail.com>
2024
2025         Update year range in copyright notice of all files.
2026
2027 2018-01-02  Jan Beulich  <jbeulich@suse.com>
2028
2029         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2030         and OPERAND_TYPE_REGZMM entries.
2031
2032 For older changes see ChangeLog-2017
2033 \f
2034 Copyright (C) 2018 Free Software Foundation, Inc.
2035
2036 Copying and distribution of this file, with or without modification,
2037 are permitted in any medium without royalty provided the copyright
2038 notice and this notice are preserved.
2039
2040 Local Variables:
2041 mode: change-log
2042 left-margin: 8
2043 fill-column: 74
2044 version-control: never
2045 End: