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MIPS16: Add ASMACRO instruction support
[binutils-gdb.git] / opcodes / ChangeLog
1 2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
2
3 * mips16-opc.c (decode_mips16_operand): Add `0', `1', `2', `3',
4 `4' and `s' operand codes.
5 (mips16_opcodes): Add "asmacro" entry.
6
7 2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
8
9 * mips-dis.c (print_mips16_insn_arg): Simplify processing of
10 extended operands.
11 * mips16-opc.c (decode_mips16_operand): Switch the extended
12 form of the `<' operand type to LSB position 22.
13
14 2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
15
16 * mips16-opc.c (decode_mips16_operand): Replace `0' and `4'
17 operand codes with `.' and `F' respectively.
18 (mips16_opcodes): Likewise.
19
20 2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
21
22 * mips-dis.c (print_insn_mips16): Disallow EXTEND prefix
23 matching for INSN2_SHORT_ONLY opcode table entries.
24 * mips16-opc.c (SH): New macro.
25 (mips16_opcodes): Set SH in `pinfo2' for non-extensible
26 instruction entries: "nop", "addu", "and", "break", "cmp",
27 "daddu", "ddiv", "ddivu", "div", "divu", "dmult", "dmultu",
28 "drem", "dremu", "dsllv", "dsll", "dsrav", "dsra", "dsrlv",
29 "dsrl", "dsubu", "exit", "entry", "jalr", "jal", "jr", "j",
30 "jalrc", "jrc", "mfhi", "mflo", "move", "mult", "multu", "neg",
31 "not", "or", "rem", "remu", "sllv", "sll", "slt", "sltu",
32 "srav", "sra", "srlv", "srl", "subu", "xor", "sdbbp", "seb",
33 "seh", "sew", "zeb", "zeh", "zew" and "extend".
34
35 2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
36
37 * mips16-opc.c (decode_mips16_operand) <'6'>: Remove extended
38 encoding support.
39
40 2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
41
42 * mips16-opc.c (mips16_opcodes): Set NODS in `pinfo' for
43 "extend".
44
45 2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
46
47 * mips-dis.c (set_default_mips_dis_options): Use
48 HAVE_BFD_MIPS_ELF_GET_ABIFLAGS rather than BFD64 to guard the
49 call to `bfd_mips_elf_get_abiflags'.
50 * configure.ac: Check for `bfd_mips_elf_get_abiflags' in BFD.
51 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add `libbfd.la'.
52 * aclocal.m4: Regenerate.
53 * configure: Regenerate.
54 * config.in: Regenerate.
55 * Makefile.in: Regenerate.
56
57 2016-12-23 Tristan Gingold <gingold@adacore.com>
58
59 * configure: Regenerate.
60
61 2016-12-23 Tristan Gingold <gingold@adacore.com>
62
63 * po/opcodes.pot: Regenerate.
64
65 2016-12-21 Andrew Waterman <andrew@sifive.com>
66
67 * riscv-opc.c (riscv_opcodes): Reorder jal and call entries.
68
69 2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
70
71 * mips-dis.c (mips_arch_choices): Use ISA_MIPS64 rather than
72 ISA_MIPS3 as the `isa' selection in the `bfd_mach_mips16' entry.
73 (print_insn_mips16): Check opcode entries for validity against
74 the ISA level and ASE set selected.
75
76 2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
77
78 * mips-dis.c (print_mips16_insn_arg): Always handle `extend' and
79 `insn' together, with `extend' as the high-order 16 bits.
80 (match_kind): New enum.
81 (print_insn_mips16): Rework for 32-bit instruction matching.
82 Do not dump EXTEND prefixes here.
83 * mips16-opc.c (mips16_opcodes): Move "extend" entry to the end.
84 Recode `match' and `mask' fields as 32-bit in absolute "jal" and
85 "jalx" entries.
86
87 2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
88
89 * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
90 than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu"
91 INSN_MACRO entries.
92
93 2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
94
95 * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
96 than I1 for the SP-relative "sd"/$ra entry (SDRASP minor
97 opcode).
98
99 2016-12-20 Andrew Waterman <andrew@sifive.com>
100
101 * riscv-opc.c (riscv_opcodes): Rename the "*.sc" instructions to
102 "*.aqrl".
103
104 2016-12-20 Andrew Waterman <andrew@sifive.com>
105
106 * riscv-opc.c (riscv_opcodes): Mark the rd* and csr* aliases as
107 INSN_ALIAS.
108
109 2016-12-20 Andrew Waterman <andrew@sifive.com>
110
111 * riscv-opc.c (riscv_opcodes): Change jr and jalr to "o(s)"
112 format.
113
114 2016-12-20 Andrew Waterman <andrew@sifive.com>
115
116 * riscv-dis.c (riscv_disassemble_insn): Default to the ELF's
117 XLEN when none is provided.
118
119 2016-12-20 Andrew Waterman <andrew@sifive.com>
120
121 * riscv-opc.c: Formatting fixes.
122
123 2016-12-20 Alan Modra <amodra@gmail.com>
124
125 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files.
126 * Makefile.in: Regenerate.
127 * po/POTFILES.in: Regenerate.
128
129 2016-12-19 Maciej W. Rozycki <macro@imgtec.com>
130
131 * mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]:
132 Only examine ELF file structures here.
133
134 2016-12-19 Maciej W. Rozycki <macro@imgtec.com>
135
136 * mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call
137 `bfd_mips_elf_get_abiflags' here.
138
139 2016-12-16 Nick Clifton <nickc@redhat.com>
140
141 * arm-dis.c (print_insn_thumb32): Fix compile time warning
142 computing value_in_comment.
143
144 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
145
146 * mips-dis.c (mips_convert_abiflags_ases): New function.
147 (set_default_mips_dis_options): Also infer ASE flags from ELF
148 file structures.
149
150 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
151
152 * mips-dis.c (set_default_mips_dis_options): Reorder ELF file
153 header flag interpretation code.
154
155 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
156
157 * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
158 `pinfo2' with SP-relative "sd" entries.
159
160 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
161
162 * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e
163 compact jumps.
164
165 2016-12-13 Renlin Li <renlin.li@arm.com>
166
167 * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
168 qualifier.
169 (operand_general_constraint_met_p): Remove case for CP_REG.
170 (aarch64_print_operand): Print CRn, CRm operand using imm field.
171 * aarch64-tbl.h (QL_SYS): Use CR qualifier.
172 (QL_SYSL): Likewise.
173 (aarch64_opcode_table): Change CRn, CRm operand class and type.
174 * aarch64-opc-2.c : Regenerate.
175 * aarch64-asm-2.c : Likewise.
176 * aarch64-dis-2.c : Likewise.
177
178 2016-12-12 Yao Qi <yao.qi@linaro.org>
179
180 * rx-dis.c: Include <setjmp.h>
181 (struct private): New.
182 (rx_get_byte): Check return value of read_memory_func, and
183 call memory_error_func and OPCODES_SIGLONGJMP on error.
184 (print_insn_rx): Call OPCODES_SIGSETJMP.
185
186 2016-12-12 Yao Qi <yao.qi@linaro.org>
187
188 * rl78-dis.c: Include <setjmp.h>.
189 (struct private): New.
190 (rl78_get_byte): Check return value of read_memory_func, and
191 call memory_error_func and OPCODES_SIGLONGJMP on error.
192 (print_insn_rl78_common): Call OPCODES_SIGJMP.
193
194 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
195
196 * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
197
198 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
199
200 * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
201 than UINT.
202
203 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
204
205 * mips-dis.c (print_insn_mips16): Use a tab rather than a space
206 to separate `extend' and its uninterpreted argument output.
207 Separate hexadecimal halves of undecoded extended instructions
208 output.
209
210 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
211
212 * mips-dis.c (print_mips16_insn_arg): Remove extraneous
213 indentation space across.
214
215 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
216
217 * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
218 adjustment for PC-relative operations following MIPS16e compact
219 jumps or undefined RR/J(AL)R(C) encodings.
220
221 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
222
223 * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
224 variable to `reglane_index'.
225
226 2016-12-08 Luis Machado <lgustavo@codesourcery.com>
227
228 * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
229
230 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
231
232 * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
233
234 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
235
236 * mips16-opc.c (mips16_opcodes): Update comment naming structure
237 members.
238
239 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
240
241 * mips-dis.c (print_mips_disassembler_options): Reformat output.
242
243 2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
244
245 * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
246 (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
247
248 2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
249
250 * arm-dis.c (coprocessor_opcodes): Add vjcvt.
251
252 2016-12-01 Nick Clifton <nickc@redhat.com>
253
254 PR binutils/20893
255 * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
256 opcode designator.
257
258 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
259
260 * arc-opc.c (insert_ra_chk): New function.
261 (insert_rb_chk): Likewise.
262 (insert_rad): Update text error message.
263 (insert_rcd): Likewise.
264 (insert_rhv2): Likewise.
265 (insert_r0): Likewise.
266 (insert_r1): Likewise.
267 (insert_r2): Likewise.
268 (insert_r3): Likewise.
269 (insert_sp): Likewise.
270 (insert_gp): Likewise.
271 (insert_pcl): Likewise.
272 (insert_blink): Likewise.
273 (insert_ilink1): Likewise.
274 (insert_ilink2): Likewise.
275 (insert_ras): Likewise.
276 (insert_rbs): Likewise.
277 (insert_rcs): Likewise.
278 (insert_simm3s): Likewise.
279 (insert_rrange): Likewise.
280 (insert_fpel): Likewise.
281 (insert_blinkel): Likewise.
282 (insert_pcel): Likewise.
283 (insert_nps_3bit_dst): Likewise.
284 (insert_nps_3bit_dst_short): Likewise.
285 (insert_nps_3bit_src2_short): Likewise.
286 (insert_nps_bitop_size_2b): Likewise.
287 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
288 (RA_CHK): Define.
289 (RB): Adjust.
290 (RB_CHK): Define.
291 (RC): Adjust.
292 * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
293 * arc-tbl.h (div, divu): All instructions are DIVREM class.
294 Change first insn argument to check for LP_COUNT usage.
295 (rem): Likewise.
296 (ld, ldd): All instructions are LOAD class. Change first insn
297 argument to check for LP_COUNT usage.
298 (st, std): All instructions are STORE class.
299 (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
300 Change first insn argument to check for LP_COUNT usage.
301 (mov): All instructions are MOVE class. Change first insn
302 argument to check for LP_COUNT usage.
303
304 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
305
306 * arc-dis.c (is_compatible_p): Remove function.
307 (skip_this_opcode): Don't add any decoding class to decode list.
308 Remove warning.
309 (find_format_from_table): Go through all opcodes, and warn if we
310 use a guessed mnemonic.
311
312 2016-11-28 Ramiro Polla <ramiro@hex-rays.com>
313 Amit Pawar <amit.pawar@amd.com>
314
315 PR binutils/20637
316 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
317 instructions.
318
319 2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
320
321 * configure: Regenerate.
322
323 2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
324
325 * sparc-opc.c (HWS_V8): Definition moved from
326 gas/config/tc-sparc.c.
327 (HWS_V9): Likewise.
328 (HWS_VA): Likewise.
329 (HWS_VB): Likewise.
330 (HWS_VC): Likewise.
331 (HWS_VD): Likewise.
332 (HWS_VE): Likewise.
333 (HWS_VV): Likewise.
334 (HWS_VM): Likewise.
335 (HWS2_VM): Likewise.
336 (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
337 existing entries.
338
339 2016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
340
341 * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
342 instructions.
343
344 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
345
346 * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
347 (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
348 (aarch64_opcode_table): Add fcmla and fcadd.
349 (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
350 * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
351 * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
352 * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
353 * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
354 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
355 * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
356 (operand_general_constraint_met_p): Rotate and index range check.
357 (aarch64_print_operand): Handle rotate operand.
358 * aarch64-asm-2.c: Regenerate.
359 * aarch64-dis-2.c: Likewise.
360 * aarch64-opc-2.c: Likewise.
361
362 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
363
364 * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
365 * aarch64-asm-2.c: Regenerate.
366 * aarch64-dis-2.c: Regenerate.
367 * aarch64-opc-2.c: Regenerate.
368
369 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
370
371 * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
372 (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
373 * aarch64-asm-2.c: Regenerate.
374 * aarch64-dis-2.c: Regenerate.
375 * aarch64-opc-2.c: Regenerate.
376
377 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
378
379 * aarch64-tbl.h (QL_X1NIL): New.
380 (arch64_opcode_table): Add ldraa, ldrab.
381 (AARCH64_OPERANDS): Add "ADDR_SIMM10".
382 * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
383 * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
384 * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
385 * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
386 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
387 * aarch64-opc.c (fields): Add data for FLD_S_simm10.
388 (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
389 (aarch64_print_operand): Likewise.
390 * aarch64-asm-2.c: Regenerate.
391 * aarch64-dis-2.c: Regenerate.
392 * aarch64-opc-2.c: Regenerate.
393
394 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
395
396 * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
397 brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
398 * aarch64-asm-2.c: Regenerate.
399 * aarch64-dis-2.c: Regenerate.
400 * aarch64-opc-2.c: Regenerate.
401
402 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
403
404 * aarch64-tbl.h (arch64_opcode_table): Add pacga.
405 (AARCH64_OPERANDS): Add Rm_SP.
406 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
407 * aarch64-asm-2.c: Regenerate.
408 * aarch64-dis-2.c: Regenerate.
409 * aarch64-opc-2.c: Regenerate.
410
411 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
412
413 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
414 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
415 autdzb, xpaci, xpacd.
416 * aarch64-asm-2.c: Regenerate.
417 * aarch64-dis-2.c: Regenerate.
418 * aarch64-opc-2.c: Regenerate.
419
420 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
421
422 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
423 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
424 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
425 (aarch64_sys_reg_supported_p): Add feature test for new registers.
426
427 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
428
429 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
430 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
431 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
432 autibsp.
433 * aarch64-asm-2.c: Regenerate.
434 * aarch64-dis-2.c: Regenerate.
435
436 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
437
438 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
439
440 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
441
442 PR binutils/20799
443 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
444 * i386-dis.c (EdqwS): Removed.
445 (dqw_swap_mode): Likewise.
446 (intel_operand_size): Don't check dqw_swap_mode.
447 (OP_E_register): Likewise.
448 (OP_E_memory): Likewise.
449 (OP_G): Likewise.
450 (OP_EX): Likewise.
451 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
452 * i386-tbl.h: Regerated.
453
454 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
455
456 * i386-opc.tbl: Merge AVX512F vmovq.
457 * i386-tbl.h: Regerated.
458
459 2016-11-08 H.J. Lu <hongjiu.lu@intel.com>
460
461 PR binutils/20701
462 * i386-dis.c (THREE_BYTE_0F7A): Removed.
463 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
464 (three_byte_table): Remove THREE_BYTE_0F7A.
465
466 2016-11-07 H.J. Lu <hongjiu.lu@intel.com>
467
468 PR binutils/20775
469 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
470 (FGRPd9_4): Replace 1 with 2.
471 (FGRPd9_5): Replace 2 with 3.
472 (FGRPd9_6): Replace 3 with 4.
473 (FGRPd9_7): Replace 4 with 5.
474 (FGRPda_5): Replace 5 with 6.
475 (FGRPdb_4): Replace 6 with 7.
476 (FGRPde_3): Replace 7 with 8.
477 (FGRPdf_4): Replace 8 with 9.
478 (fgrps): Add an entry for Bad_Opcode.
479
480 2016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
481
482 * arc-opc.c (arc_flag_operands): Add F_DI14.
483 (arc_flag_classes): Add C_DI14.
484 * arc-nps400-tbl.h: Add new exc instructions.
485
486 2016-11-03 Graham Markall <graham.markall@embecosm.com>
487
488 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
489 major opcode 0xa.
490 * arc-nps-400-tbl.h: Add dcmac instruction.
491 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
492 (insert_nps_rbdouble_64): Added.
493 (extract_nps_rbdouble_64): Added.
494 (insert_nps_proto_size): Added.
495 (extract_nps_proto_size): Added.
496
497 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
498
499 * arc-dis.c (struct arc_operand_iterator): Remove all fields
500 relating to long instruction processing, add new limm field.
501 (OPCODE): Rename to...
502 (OPCODE_32BIT_INSN): ...this.
503 (OPCODE_AC): Delete.
504 (skip_this_opcode): Handle different instruction lengths, update
505 macro name.
506 (special_flag_p): Update parameter type.
507 (find_format_from_table): Update for more instruction lengths.
508 (find_format_long_instructions): Delete.
509 (find_format): Update for more instruction lengths.
510 (arc_insn_length): Likewise.
511 (extract_operand_value): Update for more instruction lengths.
512 (operand_iterator_next): Remove code relating to long
513 instructions.
514 (arc_opcode_to_insn_type): New function.
515 (print_insn_arc):Update for more instructions lengths.
516 * arc-ext.c (extInstruction_t): Change argument type.
517 * arc-ext.h (extInstruction_t): Change argument type.
518 * arc-fxi.h: Change type unsigned to unsigned long long
519 extensively throughout.
520 * arc-nps400-tbl.h: Add long instructions taken from
521 arc_long_opcodes table in arc-opc.c.
522 * arc-opc.c: Update parameter types on insert/extract handlers.
523 (arc_long_opcodes): Delete.
524 (arc_num_long_opcodes): Delete.
525 (arc_opcode_len): Update for more instruction lengths.
526
527 2016-11-03 Graham Markall <graham.markall@embecosm.com>
528
529 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
530
531 2016-11-03 Graham Markall <graham.markall@embecosm.com>
532
533 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
534 with arc_opcode_len.
535 (find_format_long_instructions): Likewise.
536 * arc-opc.c (arc_opcode_len): New function.
537
538 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
539
540 * arc-nps400-tbl.h: Fix some instruction masks.
541
542 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
543
544 * i386-dis.c (REG_82): Removed.
545 (X86_64_82_REG_0): Likewise.
546 (X86_64_82_REG_1): Likewise.
547 (X86_64_82_REG_2): Likewise.
548 (X86_64_82_REG_3): Likewise.
549 (X86_64_82_REG_4): Likewise.
550 (X86_64_82_REG_5): Likewise.
551 (X86_64_82_REG_6): Likewise.
552 (X86_64_82_REG_7): Likewise.
553 (X86_64_82): New.
554 (dis386): Use X86_64_82 instead of REG_82.
555 (reg_table): Remove REG_82.
556 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
557 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
558 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
559 X86_64_82_REG_7.
560
561 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
562
563 PR binutils/20754
564 * i386-dis.c (REG_82): New.
565 (X86_64_82_REG_0): Likewise.
566 (X86_64_82_REG_1): Likewise.
567 (X86_64_82_REG_2): Likewise.
568 (X86_64_82_REG_3): Likewise.
569 (X86_64_82_REG_4): Likewise.
570 (X86_64_82_REG_5): Likewise.
571 (X86_64_82_REG_6): Likewise.
572 (X86_64_82_REG_7): Likewise.
573 (dis386): Use REG_82.
574 (reg_table): Add REG_82.
575 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
576 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
577 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
578
579 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
580
581 * i386-dis.c (REG_82): Renamed to ...
582 (REG_83): This.
583 (dis386): Updated.
584 (reg_table): Likewise.
585
586 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
587
588 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
589 * i386-dis-evex.h (evex_table): Updated.
590 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
591 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
592 (cpu_flags): Add CpuAVX512_4VNNIW.
593 * i386-opc.h (enum): (AVX512_4VNNIW): New.
594 (i386_cpu_flags): Add cpuavx512_4vnniw.
595 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
596 * i386-init.h: Regenerate.
597 * i386-tbl.h: Ditto.
598
599 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
600
601 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
602 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
603 * i386-dis-evex.h (evex_table): Updated.
604 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
605 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
606 (cpu_flags): Add CpuAVX512_4FMAPS.
607 (opcode_modifiers): Add ImplicitQuadGroup modifier.
608 * i386-opc.h (AVX512_4FMAP): New.
609 (i386_cpu_flags): Add cpuavx512_4fmaps.
610 (ImplicitQuadGroup): New.
611 (i386_opcode_modifier): Add implicitquadgroup.
612 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
613 * i386-init.h: Regenerate.
614 * i386-tbl.h: Ditto.
615
616 2016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
617 Andrew Waterman <andrew@sifive.com>
618
619 Add support for RISC-V architecture.
620 * configure.ac: Add entry for bfd_riscv_arch.
621 * configure: Regenerate.
622 * disassemble.c (disassembler): Add support for riscv.
623 (disassembler_usage): Likewise.
624 * riscv-dis.c: New file.
625 * riscv-opc.c: New file.
626
627 2016-10-21 H.J. Lu <hongjiu.lu@intel.com>
628
629 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
630 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
631 (rm_table): Update the RM_0FAE_REG_7 entry.
632 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
633 (cpu_flags): Remove CpuPCOMMIT.
634 * i386-opc.h (CpuPCOMMIT): Removed.
635 (i386_cpu_flags): Remove cpupcommit.
636 * i386-opc.tbl: Remove pcommit.
637 * i386-init.h: Regenerated.
638 * i386-tbl.h: Likewise.
639
640 2016-10-20 H.J. Lu <hongjiu.lu@intel.com>
641
642 PR binutis/20705
643 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
644 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
645 32-bit mode. Don't check vex.register_specifier in 32-bit
646 mode.
647 (OP_VEX): Check for invalid mask registers.
648
649 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
650
651 PR binutis/20699
652 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
653 sizeflag.
654
655 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
656
657 PR binutis/20704
658 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
659
660 2016-10-18 Maciej W. Rozycki <macro@imgtec.com>
661
662 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
663 local variable to `index_regno'.
664
665 2016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
666
667 * arc-tbl.h: Removed any "inv.+" instructions from the table.
668
669 2016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
670
671 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
672 usage on ISA basis.
673
674 2016-10-11 Jiong Wang <jiong.wang@arm.com>
675
676 PR target/20666
677 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
678
679 2016-10-07 Jiong Wang <jiong.wang@arm.com>
680
681 PR target/20667
682 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
683 available.
684
685 2016-10-07 Alan Modra <amodra@gmail.com>
686
687 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
688
689 2016-10-06 Alan Modra <amodra@gmail.com>
690
691 * aarch64-opc.c: Spell fall through comments consistently.
692 * i386-dis.c: Likewise.
693 * aarch64-dis.c: Add missing fall through comments.
694 * aarch64-opc.c: Likewise.
695 * arc-dis.c: Likewise.
696 * arm-dis.c: Likewise.
697 * i386-dis.c: Likewise.
698 * m68k-dis.c: Likewise.
699 * mep-asm.c: Likewise.
700 * ns32k-dis.c: Likewise.
701 * sh-dis.c: Likewise.
702 * tic4x-dis.c: Likewise.
703 * tic6x-dis.c: Likewise.
704 * vax-dis.c: Likewise.
705
706 2016-10-06 Alan Modra <amodra@gmail.com>
707
708 * arc-ext.c (create_map): Add missing break.
709 * msp430-decode.opc (encode_as): Likewise.
710 * msp430-decode.c: Regenerate.
711
712 2016-10-06 Alan Modra <amodra@gmail.com>
713
714 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
715 * crx-dis.c (print_insn_crx): Likewise.
716
717 2016-09-30 H.J. Lu <hongjiu.lu@intel.com>
718
719 PR binutils/20657
720 * i386-dis.c (putop): Don't assign alt twice.
721
722 2016-09-29 Jiong Wang <jiong.wang@arm.com>
723
724 PR target/20553
725 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
726
727 2016-09-29 Alan Modra <amodra@gmail.com>
728
729 * ppc-opc.c (L): Make compulsory.
730 (LOPT): New, optional form of L.
731 (HTM_R): Define as LOPT.
732 (L0, L1): Delete.
733 (L32OPT): New, optional for 32-bit L.
734 (L2OPT): New, 2-bit L for dcbf.
735 (SVC_LEC): Update.
736 (L2): Define.
737 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
738 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
739 <dcbf>: Use L2OPT.
740 <tlbiel, tlbie>: Use LOPT.
741 <wclr, wclrall>: Use L2.
742
743 2016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
744
745 * Makefile.in: Regenerate.
746 * configure: Likewise.
747
748 2016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
749
750 * arc-ext-tbl.h (EXTINSN2OPF): Define.
751 (EXTINSN2OP): Use EXTINSN2OPF.
752 (bspeekm, bspop, modapp): New extension instructions.
753 * arc-opc.c (F_DNZ_ND): Define.
754 (F_DNZ_D): Likewise.
755 (F_SIZEB1): Changed.
756 (C_DNZ_D): Define.
757 (C_HARD): Changed.
758 * arc-tbl.h (dbnz): New instruction.
759 (prealloc): Allow it for ARC EM.
760 (xbfu): Likewise.
761
762 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
763
764 * aarch64-opc.c (print_immediate_offset_address): Print spaces
765 after commas in addresses.
766 (aarch64_print_operand): Likewise.
767
768 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
769
770 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
771 rather than "should be" or "expected to be" in error messages.
772
773 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
774
775 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
776 (print_mnemonic_name): ...here.
777 (print_comment): New function.
778 (print_aarch64_insn): Call it.
779 * aarch64-opc.c (aarch64_conds): Add SVE names.
780 (aarch64_print_operand): Print alternative condition names in
781 a comment.
782
783 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
784
785 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
786 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
787 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
788 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
789 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
790 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
791 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
792 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
793 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
794 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
795 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
796 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
797 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
798 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
799 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
800 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
801 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
802 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
803 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
804 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
805 (OP_SVE_XWU, OP_SVE_XXU): New macros.
806 (aarch64_feature_sve): New variable.
807 (SVE): New macro.
808 (_SVE_INSN): Likewise.
809 (aarch64_opcode_table): Add SVE instructions.
810 * aarch64-opc.h (extract_fields): Declare.
811 * aarch64-opc-2.c: Regenerate.
812 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
813 * aarch64-asm-2.c: Regenerate.
814 * aarch64-dis.c (extract_fields): Make global.
815 (do_misc_decoding): Handle the new SVE aarch64_ops.
816 * aarch64-dis-2.c: Regenerate.
817
818 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
819
820 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
821 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
822 aarch64_field_kinds.
823 * aarch64-opc.c (fields): Add corresponding entries.
824 * aarch64-asm.c (aarch64_get_variant): New function.
825 (aarch64_encode_variant_using_iclass): Likewise.
826 (aarch64_opcode_encode): Call it.
827 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
828 (aarch64_opcode_decode): Call it.
829
830 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
831
832 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
833 and FP register operands.
834 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
835 (FLD_SVE_Vn): New aarch64_field_kinds.
836 * aarch64-opc.c (fields): Add corresponding entries.
837 (aarch64_print_operand): Handle the new SVE core and FP register
838 operands.
839 * aarch64-opc-2.c: Regenerate.
840 * aarch64-asm-2.c: Likewise.
841 * aarch64-dis-2.c: Likewise.
842
843 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
844
845 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
846 immediate operands.
847 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
848 * aarch64-opc.c (fields): Add corresponding entry.
849 (operand_general_constraint_met_p): Handle the new SVE FP immediate
850 operands.
851 (aarch64_print_operand): Likewise.
852 * aarch64-opc-2.c: Regenerate.
853 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
854 (ins_sve_float_zero_one): New inserters.
855 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
856 (aarch64_ins_sve_float_half_two): Likewise.
857 (aarch64_ins_sve_float_zero_one): Likewise.
858 * aarch64-asm-2.c: Regenerate.
859 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
860 (ext_sve_float_zero_one): New extractors.
861 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
862 (aarch64_ext_sve_float_half_two): Likewise.
863 (aarch64_ext_sve_float_zero_one): Likewise.
864 * aarch64-dis-2.c: Regenerate.
865
866 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
867
868 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
869 integer immediate operands.
870 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
871 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
872 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
873 * aarch64-opc.c (fields): Add corresponding entries.
874 (operand_general_constraint_met_p): Handle the new SVE integer
875 immediate operands.
876 (aarch64_print_operand): Likewise.
877 (aarch64_sve_dupm_mov_immediate_p): New function.
878 * aarch64-opc-2.c: Regenerate.
879 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
880 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
881 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
882 (aarch64_ins_limm): ...here.
883 (aarch64_ins_inv_limm): New function.
884 (aarch64_ins_sve_aimm): Likewise.
885 (aarch64_ins_sve_asimm): Likewise.
886 (aarch64_ins_sve_limm_mov): Likewise.
887 (aarch64_ins_sve_shlimm): Likewise.
888 (aarch64_ins_sve_shrimm): Likewise.
889 * aarch64-asm-2.c: Regenerate.
890 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
891 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
892 * aarch64-dis.c (decode_limm): New function, split out from...
893 (aarch64_ext_limm): ...here.
894 (aarch64_ext_inv_limm): New function.
895 (decode_sve_aimm): Likewise.
896 (aarch64_ext_sve_aimm): Likewise.
897 (aarch64_ext_sve_asimm): Likewise.
898 (aarch64_ext_sve_limm_mov): Likewise.
899 (aarch64_top_bit): Likewise.
900 (aarch64_ext_sve_shlimm): Likewise.
901 (aarch64_ext_sve_shrimm): Likewise.
902 * aarch64-dis-2.c: Regenerate.
903
904 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
905
906 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
907 operands.
908 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
909 the AARCH64_MOD_MUL_VL entry.
910 (value_aligned_p): Cope with non-power-of-two alignments.
911 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
912 (print_immediate_offset_address): Likewise.
913 (aarch64_print_operand): Likewise.
914 * aarch64-opc-2.c: Regenerate.
915 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
916 (ins_sve_addr_ri_s9xvl): New inserters.
917 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
918 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
919 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
920 * aarch64-asm-2.c: Regenerate.
921 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
922 (ext_sve_addr_ri_s9xvl): New extractors.
923 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
924 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
925 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
926 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
927 * aarch64-dis-2.c: Regenerate.
928
929 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
930
931 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
932 address operands.
933 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
934 (FLD_SVE_xs_22): New aarch64_field_kinds.
935 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
936 (get_operand_specific_data): New function.
937 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
938 FLD_SVE_xs_14 and FLD_SVE_xs_22.
939 (operand_general_constraint_met_p): Handle the new SVE address
940 operands.
941 (sve_reg): New array.
942 (get_addr_sve_reg_name): New function.
943 (aarch64_print_operand): Handle the new SVE address operands.
944 * aarch64-opc-2.c: Regenerate.
945 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
946 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
947 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
948 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
949 (aarch64_ins_sve_addr_rr_lsl): Likewise.
950 (aarch64_ins_sve_addr_rz_xtw): Likewise.
951 (aarch64_ins_sve_addr_zi_u5): Likewise.
952 (aarch64_ins_sve_addr_zz): Likewise.
953 (aarch64_ins_sve_addr_zz_lsl): Likewise.
954 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
955 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
956 * aarch64-asm-2.c: Regenerate.
957 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
958 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
959 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
960 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
961 (aarch64_ext_sve_addr_ri_u6): Likewise.
962 (aarch64_ext_sve_addr_rr_lsl): Likewise.
963 (aarch64_ext_sve_addr_rz_xtw): Likewise.
964 (aarch64_ext_sve_addr_zi_u5): Likewise.
965 (aarch64_ext_sve_addr_zz): Likewise.
966 (aarch64_ext_sve_addr_zz_lsl): Likewise.
967 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
968 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
969 * aarch64-dis-2.c: Regenerate.
970
971 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
972
973 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
974 AARCH64_OPND_SVE_PATTERN_SCALED.
975 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
976 * aarch64-opc.c (fields): Add a corresponding entry.
977 (set_multiplier_out_of_range_error): New function.
978 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
979 (operand_general_constraint_met_p): Handle
980 AARCH64_OPND_SVE_PATTERN_SCALED.
981 (print_register_offset_address): Use PRIi64 to print the
982 shift amount.
983 (aarch64_print_operand): Likewise. Handle
984 AARCH64_OPND_SVE_PATTERN_SCALED.
985 * aarch64-opc-2.c: Regenerate.
986 * aarch64-asm.h (ins_sve_scale): New inserter.
987 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
988 * aarch64-asm-2.c: Regenerate.
989 * aarch64-dis.h (ext_sve_scale): New inserter.
990 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
991 * aarch64-dis-2.c: Regenerate.
992
993 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
994
995 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
996 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
997 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
998 (FLD_SVE_prfop): Likewise.
999 * aarch64-opc.c: Include libiberty.h.
1000 (aarch64_sve_pattern_array): New variable.
1001 (aarch64_sve_prfop_array): Likewise.
1002 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
1003 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
1004 AARCH64_OPND_SVE_PRFOP.
1005 * aarch64-asm-2.c: Regenerate.
1006 * aarch64-dis-2.c: Likewise.
1007 * aarch64-opc-2.c: Likewise.
1008
1009 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1010
1011 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
1012 AARCH64_OPND_QLF_P_[ZM].
1013 (aarch64_print_operand): Print /z and /m where appropriate.
1014
1015 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1016
1017 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
1018 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
1019 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
1020 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
1021 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
1022 * aarch64-opc.c (fields): Add corresponding entries here.
1023 (operand_general_constraint_met_p): Check that SVE register lists
1024 have the correct length. Check the ranges of SVE index registers.
1025 Check for cases where p8-p15 are used in 3-bit predicate fields.
1026 (aarch64_print_operand): Handle the new SVE operands.
1027 * aarch64-opc-2.c: Regenerate.
1028 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
1029 * aarch64-asm.c (aarch64_ins_sve_index): New function.
1030 (aarch64_ins_sve_reglist): Likewise.
1031 * aarch64-asm-2.c: Regenerate.
1032 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
1033 * aarch64-dis.c (aarch64_ext_sve_index): New function.
1034 (aarch64_ext_sve_reglist): Likewise.
1035 * aarch64-dis-2.c: Regenerate.
1036
1037 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1038
1039 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
1040 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
1041 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
1042 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
1043 tied operands.
1044
1045 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1046
1047 * aarch64-opc.c (get_offset_int_reg_name): New function.
1048 (print_immediate_offset_address): Likewise.
1049 (print_register_offset_address): Take the base and offset
1050 registers as parameters.
1051 (aarch64_print_operand): Update caller accordingly. Use
1052 print_immediate_offset_address.
1053
1054 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1055
1056 * aarch64-opc.c (BANK): New macro.
1057 (R32, R64): Take a register number as argument
1058 (int_reg): Use BANK.
1059
1060 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1061
1062 * aarch64-opc.c (print_register_list): Add a prefix parameter.
1063 (aarch64_print_operand): Update accordingly.
1064
1065 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1066
1067 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
1068 for FPIMM.
1069 * aarch64-asm.h (ins_fpimm): New inserter.
1070 * aarch64-asm.c (aarch64_ins_fpimm): New function.
1071 * aarch64-asm-2.c: Regenerate.
1072 * aarch64-dis.h (ext_fpimm): New extractor.
1073 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
1074 (aarch64_ext_fpimm): New function.
1075 * aarch64-dis-2.c: Regenerate.
1076
1077 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1078
1079 * aarch64-asm.c: Include libiberty.h.
1080 (insert_fields): New function.
1081 (aarch64_ins_imm): Use it.
1082 * aarch64-dis.c (extract_fields): New function.
1083 (aarch64_ext_imm): Use it.
1084
1085 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1086
1087 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
1088 with an esize parameter.
1089 (operand_general_constraint_met_p): Update accordingly.
1090 Fix misindented code.
1091 * aarch64-asm.c (aarch64_ins_limm): Update call to
1092 aarch64_logical_immediate_p.
1093
1094 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1095
1096 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
1097
1098 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1099
1100 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
1101
1102 2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
1103
1104 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
1105
1106 2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
1107
1108 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
1109 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
1110 xor3>: Delete mnemonics.
1111 <cp_abort>: Rename mnemonic from ...
1112 <cpabort>: ...to this.
1113 <setb>: Change to a X form instruction.
1114 <sync>: Change to 1 operand form.
1115 <copy>: Delete mnemonic.
1116 <copy_first>: Rename mnemonic from ...
1117 <copy>: ...to this.
1118 <paste, paste.>: Delete mnemonics.
1119 <paste_last>: Rename mnemonic from ...
1120 <paste.>: ...to this.
1121
1122 2016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
1123
1124 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
1125
1126 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1127
1128 * s390-mkopc.c (main): Support alternate arch strings.
1129
1130 2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
1131
1132 * s390-opc.txt: Fix kmctr instruction type.
1133
1134 2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
1135
1136 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
1137 * i386-init.h: Regenerated.
1138
1139 2016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
1140
1141 * opcodes/arc-dis.c (print_insn_arc): Changed.
1142
1143 2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
1144
1145 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
1146 camellia_fl.
1147
1148 2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
1149
1150 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
1151 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
1152 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
1153
1154 2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
1155
1156 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
1157 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
1158 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
1159 PREFIX_MOD_3_0FAE_REG_4.
1160 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
1161 PREFIX_MOD_3_0FAE_REG_4.
1162 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
1163 (cpu_flags): Add CpuPTWRITE.
1164 * i386-opc.h (CpuPTWRITE): New.
1165 (i386_cpu_flags): Add cpuptwrite.
1166 * i386-opc.tbl: Add ptwrite instruction.
1167 * i386-init.h: Regenerated.
1168 * i386-tbl.h: Likewise.
1169
1170 2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
1171
1172 * arc-dis.h: Wrap around in extern "C".
1173
1174 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1175
1176 * aarch64-tbl.h (V8_2_INSN): New macro.
1177 (aarch64_opcode_table): Use it.
1178
1179 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1180
1181 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
1182 CORE_INSN, __FP_INSN and SIMD_INSN.
1183
1184 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1185
1186 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
1187 (aarch64_opcode_table): Update uses accordingly.
1188
1189 2016-07-25 Andrew Jenner <andrew@codesourcery.com>
1190 Kwok Cheung Yeung <kcy@codesourcery.com>
1191
1192 opcodes/
1193 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
1194 'e_cmplwi' to 'e_cmpli' instead.
1195 (OPVUPRT, OPVUPRT_MASK): Define.
1196 (powerpc_opcodes): Add E200Z4 insns.
1197 (vle_opcodes): Add context save/restore insns.
1198
1199 2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
1200
1201 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
1202 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
1203 "j".
1204
1205 2016-07-27 Graham Markall <graham.markall@embecosm.com>
1206
1207 * arc-nps400-tbl.h: Change block comments to GNU format.
1208 * arc-dis.c: Add new globals addrtypenames,
1209 addrtypenames_max, and addtypeunknown.
1210 (get_addrtype): New function.
1211 (print_insn_arc): Print colons and address types when
1212 required.
1213 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1214 define insert and extract functions for all address types.
1215 (arc_operands): Add operands for colon and all address
1216 types.
1217 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1218 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1219 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1220 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1221 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1222 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1223
1224 2016-07-21 H.J. Lu <hongjiu.lu@intel.com>
1225
1226 * configure: Regenerated.
1227
1228 2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
1229
1230 * arc-dis.c (skipclass): New structure.
1231 (decodelist): New variable.
1232 (is_compatible_p): New function.
1233 (new_element): Likewise.
1234 (skip_class_p): Likewise.
1235 (find_format_from_table): Use skip_class_p function.
1236 (find_format): Decode first the extension instructions.
1237 (print_insn_arc): Select either ARCEM or ARCHS based on elf
1238 e_flags.
1239 (parse_option): New function.
1240 (parse_disassembler_options): Likewise.
1241 (print_arc_disassembler_options): Likewise.
1242 (print_insn_arc): Use parse_disassembler_options function. Proper
1243 select ARCv2 cpu variant.
1244 * disassemble.c (disassembler_usage): Add ARC disassembler
1245 options.
1246
1247 2016-07-13 Maciej W. Rozycki <macro@imgtec.com>
1248
1249 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1250 annotation from the "nal" entry and reorder it beyond "bltzal".
1251
1252 2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
1253
1254 * sparc-opc.c (ldtxa): New macro.
1255 (sparc_opcodes): Use the macro defined above to add entries for
1256 the LDTXA instructions.
1257 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1258 instruction.
1259
1260 2016-07-07 James Bowman <james.bowman@ftdichip.com>
1261
1262 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1263 and "jmpc".
1264
1265 2016-07-01 Jan Beulich <jbeulich@suse.com>
1266
1267 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1268 (movzb): Adjust to cover all permitted suffixes.
1269 (movzw): New.
1270 * i386-tbl.h: Re-generate.
1271
1272 2016-07-01 Jan Beulich <jbeulich@suse.com>
1273
1274 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1275 (lgdt): Remove Tbyte from non-64-bit variant.
1276 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1277 xsaves64, xsavec64): Remove Disp16.
1278 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1279 Remove Disp32S from non-64-bit variants. Remove Disp16 from
1280 64-bit variants.
1281 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1282 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1283 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1284 64-bit variants.
1285 * i386-tbl.h: Re-generate.
1286
1287 2016-07-01 Jan Beulich <jbeulich@suse.com>
1288
1289 * i386-opc.tbl (xlat): Remove RepPrefixOk.
1290 * i386-tbl.h: Re-generate.
1291
1292 2016-06-30 Yao Qi <yao.qi@linaro.org>
1293
1294 * arm-dis.c (print_insn): Fix typo in comment.
1295
1296 2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
1297
1298 * aarch64-opc.c (operand_general_constraint_met_p): Check the
1299 range of ldst_elemlist operands.
1300 (print_register_list): Use PRIi64 to print the index.
1301 (aarch64_print_operand): Likewise.
1302
1303 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1304
1305 * mcore-opc.h: Remove sentinal.
1306 * mcore-dis.c (print_insn_mcore): Adjust.
1307
1308 2016-06-23 Graham Markall <graham.markall@embecosm.com>
1309
1310 * arc-opc.c: Correct description of availability of NPS400
1311 features.
1312
1313 2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
1314
1315 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1316 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1317 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1318 xor3>: New mnemonics.
1319 <setb>: Change to a VX form instruction.
1320 (insert_sh6): Add support for rldixor.
1321 (extract_sh6): Likewise.
1322
1323 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1324
1325 * arc-ext.h: Wrap in extern C.
1326
1327 2016-06-21 Graham Markall <graham.markall@embecosm.com>
1328
1329 * arc-dis.c (arc_insn_length): Add comment on instruction length.
1330 Use same method for determining instruction length on ARC700 and
1331 NPS-400.
1332 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1333 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1334 with the NPS400 subclass.
1335 * arc-opc.c: Likewise.
1336
1337 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1338
1339 * sparc-opc.c (rdasr): New macro.
1340 (wrasr): Likewise.
1341 (rdpr): Likewise.
1342 (wrpr): Likewise.
1343 (rdhpr): Likewise.
1344 (wrhpr): Likewise.
1345 (sparc_opcodes): Use the macros above to fix and expand the
1346 definition of read/write instructions from/to
1347 asr/privileged/hyperprivileged instructions.
1348 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1349 %hva_mask_nz. Prefer softint_set and softint_clear over
1350 set_softint and clear_softint.
1351 (print_insn_sparc): Support %ver in Rd.
1352
1353 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1354
1355 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1356 architecture according to the hardware capabilities they require.
1357
1358 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1359
1360 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1361 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1362 bfd_mach_sparc_v9{c,d,e,v,m}.
1363 * sparc-opc.c (MASK_V9C): Define.
1364 (MASK_V9D): Likewise.
1365 (MASK_V9E): Likewise.
1366 (MASK_V9V): Likewise.
1367 (MASK_V9M): Likewise.
1368 (v6): Add MASK_V9{C,D,E,V,M}.
1369 (v6notlet): Likewise.
1370 (v7): Likewise.
1371 (v8): Likewise.
1372 (v9): Likewise.
1373 (v9andleon): Likewise.
1374 (v9a): Likewise.
1375 (v9b): Likewise.
1376 (v9c): Define.
1377 (v9d): Likewise.
1378 (v9e): Likewise.
1379 (v9v): Likewise.
1380 (v9m): Likewise.
1381 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1382
1383 2016-06-15 Nick Clifton <nickc@redhat.com>
1384
1385 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1386 constants to match expected behaviour.
1387 (nds32_parse_opcode): Likewise. Also for whitespace.
1388
1389 2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
1390
1391 * arc-opc.c (extract_rhv1): Extract value from insn.
1392
1393 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1394
1395 * arc-nps400-tbl.h: Add ldbit instruction.
1396 * arc-opc.c: Add flag classes required for ldbit.
1397
1398 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1399
1400 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1401 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1402 support the above instructions.
1403
1404 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1405
1406 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1407 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1408 csma, cbba, zncv, and hofs.
1409 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1410 support the above instructions.
1411
1412 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1413
1414 * arc-nps400-tbl.h: Add andab and orab instructions.
1415
1416 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1417
1418 * arc-nps400-tbl.h: Add addl-like instructions.
1419
1420 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1421
1422 * arc-nps400-tbl.h: Add mxb and imxb instructions.
1423
1424 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1425
1426 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1427 instructions.
1428
1429 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1430
1431 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1432 variable.
1433 (init_disasm): Handle new command line option "insnlength".
1434 (print_s390_disassembler_options): Mention new option in help
1435 output.
1436 (print_insn_s390): Use the encoded insn length when dumping
1437 unknown instructions.
1438
1439 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1440
1441 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1442 to the address and set as symbol address for LDS/ STS immediate operands.
1443
1444 2016-06-07 Alan Modra <amodra@gmail.com>
1445
1446 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1447 cpu for "vle" to e500.
1448 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1449 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1450 (PPCNONE): Delete, substitute throughout.
1451 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1452 except for major opcode 4 and 31.
1453 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1454
1455 2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1456
1457 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1458 ARM_EXT_RAS in relevant entries.
1459
1460 2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1461
1462 PR binutils/20196
1463 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1464 opcodes for E6500.
1465
1466 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1467
1468 PR binutis/18386
1469 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1470 (indir_v_mode): New.
1471 Add comments for '&'.
1472 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1473 (putop): Handle '&'.
1474 (intel_operand_size): Handle indir_v_mode.
1475 (OP_E_register): Likewise.
1476 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1477 64-bit indirect call/jmp for AMD64.
1478 * i386-tbl.h: Regenerated
1479
1480 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1481
1482 * arc-dis.c (struct arc_operand_iterator): New structure.
1483 (find_format_from_table): All the old content from find_format,
1484 with some minor adjustments, and parameter renaming.
1485 (find_format_long_instructions): New function.
1486 (find_format): Rewritten.
1487 (arc_insn_length): Add LSB parameter.
1488 (extract_operand_value): New function.
1489 (operand_iterator_next): New function.
1490 (print_insn_arc): Use new functions to find opcode, and iterator
1491 over operands.
1492 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1493 (extract_nps_3bit_dst_short): New function.
1494 (insert_nps_3bit_src2_short): New function.
1495 (extract_nps_3bit_src2_short): New function.
1496 (insert_nps_bitop1_size): New function.
1497 (extract_nps_bitop1_size): New function.
1498 (insert_nps_bitop2_size): New function.
1499 (extract_nps_bitop2_size): New function.
1500 (insert_nps_bitop_mod4_msb): New function.
1501 (extract_nps_bitop_mod4_msb): New function.
1502 (insert_nps_bitop_mod4_lsb): New function.
1503 (extract_nps_bitop_mod4_lsb): New function.
1504 (insert_nps_bitop_dst_pos3_pos4): New function.
1505 (extract_nps_bitop_dst_pos3_pos4): New function.
1506 (insert_nps_bitop_ins_ext): New function.
1507 (extract_nps_bitop_ins_ext): New function.
1508 (arc_operands): Add new operands.
1509 (arc_long_opcodes): New global array.
1510 (arc_num_long_opcodes): New global.
1511 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1512
1513 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1514
1515 * nds32-asm.h: Add extern "C".
1516 * sh-opc.h: Likewise.
1517
1518 2016-06-01 Graham Markall <graham.markall@embecosm.com>
1519
1520 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1521 0,b,limm to the rflt instruction.
1522
1523 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1524
1525 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1526 constant.
1527
1528 2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1529
1530 PR gas/20145
1531 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1532 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1533 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1534 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1535 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1536 * i386-init.h: Regenerated.
1537
1538 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1539
1540 PR gas/20145
1541 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1542 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1543 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1544 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1545 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1546 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1547 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1548 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1549 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1550 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1551 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1552 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1553 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1554 CpuRegMask for AVX512.
1555 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1556 and CpuRegMask.
1557 (set_bitfield_from_cpu_flag_init): New function.
1558 (set_bitfield): Remove const on f. Call
1559 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1560 * i386-opc.h (CpuRegMMX): New.
1561 (CpuRegXMM): Likewise.
1562 (CpuRegYMM): Likewise.
1563 (CpuRegZMM): Likewise.
1564 (CpuRegMask): Likewise.
1565 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1566 and cpuregmask.
1567 * i386-init.h: Regenerated.
1568 * i386-tbl.h: Likewise.
1569
1570 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1571
1572 PR gas/20154
1573 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1574 (opcode_modifiers): Add AMD64 and Intel64.
1575 (main): Properly verify CpuMax.
1576 * i386-opc.h (CpuAMD64): Removed.
1577 (CpuIntel64): Likewise.
1578 (CpuMax): Set to CpuNo64.
1579 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1580 (AMD64): New.
1581 (Intel64): Likewise.
1582 (i386_opcode_modifier): Add amd64 and intel64.
1583 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1584 on call and jmp.
1585 * i386-init.h: Regenerated.
1586 * i386-tbl.h: Likewise.
1587
1588 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1589
1590 PR gas/20154
1591 * i386-gen.c (main): Fail if CpuMax is incorrect.
1592 * i386-opc.h (CpuMax): Set to CpuIntel64.
1593 * i386-tbl.h: Regenerated.
1594
1595 2016-05-27 Nick Clifton <nickc@redhat.com>
1596
1597 PR target/20150
1598 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1599 (msp430dis_opcode_unsigned): New function.
1600 (msp430dis_opcode_signed): New function.
1601 (msp430_singleoperand): Use the new opcode reading functions.
1602 Only disassenmble bytes if they were successfully read.
1603 (msp430_doubleoperand): Likewise.
1604 (msp430_branchinstr): Likewise.
1605 (msp430x_callx_instr): Likewise.
1606 (print_insn_msp430): Check that it is safe to read bytes before
1607 attempting disassembly. Use the new opcode reading functions.
1608
1609 2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1610
1611 * ppc-opc.c (CY): New define. Document it.
1612 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1613
1614 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1615
1616 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1617 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1618 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1619 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1620 CPU_ANY_AVX_FLAGS.
1621 * i386-init.h: Regenerated.
1622
1623 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1624
1625 PR gas/20141
1626 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1627 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1628 * i386-init.h: Regenerated.
1629
1630 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1631
1632 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1633 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1634 * i386-init.h: Regenerated.
1635
1636 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1637
1638 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1639 information.
1640 (print_insn_arc): Set insn_type information.
1641 * arc-opc.c (C_CC): Add F_CLASS_COND.
1642 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1643 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1644 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1645 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1646 (brne, brne_s, jeq_s, jne_s): Likewise.
1647
1648 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1649
1650 * arc-tbl.h (neg): New instruction variant.
1651
1652 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1653
1654 * arc-dis.c (find_format, find_format, get_auxreg)
1655 (print_insn_arc): Changed.
1656 * arc-ext.h (INSERT_XOP): Likewise.
1657
1658 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1659
1660 * tic54x-dis.c (sprint_mmr): Adjust.
1661 * tic54x-opc.c: Likewise.
1662
1663 2016-05-19 Alan Modra <amodra@gmail.com>
1664
1665 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1666
1667 2016-05-19 Alan Modra <amodra@gmail.com>
1668
1669 * ppc-opc.c: Formatting.
1670 (NSISIGNOPT): Define.
1671 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1672
1673 2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1674
1675 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1676 replacing references to `micromips_ase' throughout.
1677 (_print_insn_mips): Don't use file-level microMIPS annotation to
1678 determine the disassembly mode with the symbol table.
1679
1680 2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1681
1682 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1683
1684 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1685
1686 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1687 mips64r6.
1688 * mips-opc.c (D34): New macro.
1689 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1690
1691 2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1692
1693 * i386-dis.c (prefix_table): Add RDPID instruction.
1694 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1695 (cpu_flags): Add RDPID bitfield.
1696 * i386-opc.h (enum): Add RDPID element.
1697 (i386_cpu_flags): Add RDPID field.
1698 * i386-opc.tbl: Add RDPID instruction.
1699 * i386-init.h: Regenerate.
1700 * i386-tbl.h: Regenerate.
1701
1702 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1703
1704 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1705 branch type of a symbol.
1706 (print_insn): Likewise.
1707
1708 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1709
1710 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1711 Mainline Security Extensions instructions.
1712 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1713 Extensions instructions.
1714 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1715 instructions.
1716 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1717 special registers.
1718
1719 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1720
1721 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1722
1723 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1724
1725 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1726 (arcExtMap_genOpcode): Likewise.
1727 * arc-opc.c (arg_32bit_rc): Define new variable.
1728 (arg_32bit_u6): Likewise.
1729 (arg_32bit_limm): Likewise.
1730
1731 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1732
1733 * aarch64-gen.c (VERIFIER): Define.
1734 * aarch64-opc.c (VERIFIER): Define.
1735 (verify_ldpsw): Use static linkage.
1736 * aarch64-opc.h (verify_ldpsw): Remove.
1737 * aarch64-tbl.h: Use VERIFIER for verifiers.
1738
1739 2016-04-28 Nick Clifton <nickc@redhat.com>
1740
1741 PR target/19722
1742 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1743 * aarch64-opc.c (verify_ldpsw): New function.
1744 * aarch64-opc.h (verify_ldpsw): New prototype.
1745 * aarch64-tbl.h: Add initialiser for verifier field.
1746 (LDPSW): Set verifier to verify_ldpsw.
1747
1748 2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1749
1750 PR binutils/19983
1751 PR binutils/19984
1752 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1753 smaller than address size.
1754
1755 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1756
1757 * alpha-dis.c: Regenerate.
1758 * crx-dis.c: Likewise.
1759 * disassemble.c: Likewise.
1760 * epiphany-opc.c: Likewise.
1761 * fr30-opc.c: Likewise.
1762 * frv-opc.c: Likewise.
1763 * ip2k-opc.c: Likewise.
1764 * iq2000-opc.c: Likewise.
1765 * lm32-opc.c: Likewise.
1766 * lm32-opinst.c: Likewise.
1767 * m32c-opc.c: Likewise.
1768 * m32r-opc.c: Likewise.
1769 * m32r-opinst.c: Likewise.
1770 * mep-opc.c: Likewise.
1771 * mt-opc.c: Likewise.
1772 * or1k-opc.c: Likewise.
1773 * or1k-opinst.c: Likewise.
1774 * tic80-opc.c: Likewise.
1775 * xc16x-opc.c: Likewise.
1776 * xstormy16-opc.c: Likewise.
1777
1778 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1779
1780 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1781 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1782 calcsd, and calcxd instructions.
1783 * arc-opc.c (insert_nps_bitop_size): Delete.
1784 (extract_nps_bitop_size): Delete.
1785 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1786 (extract_nps_qcmp_m3): Define.
1787 (extract_nps_qcmp_m2): Define.
1788 (extract_nps_qcmp_m1): Define.
1789 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1790 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1791 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1792 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1793 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1794 NPS_QCMP_M3.
1795
1796 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1797
1798 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1799
1800 2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1801
1802 * Makefile.in: Regenerated with automake 1.11.6.
1803 * aclocal.m4: Likewise.
1804
1805 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1806
1807 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1808 instructions.
1809 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1810 (extract_nps_cmem_uimm16): New function.
1811 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1812
1813 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1814
1815 * arc-dis.c (arc_insn_length): New function.
1816 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1817 (find_format): Change insnLen parameter to unsigned.
1818
1819 2016-04-13 Nick Clifton <nickc@redhat.com>
1820
1821 PR target/19937
1822 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1823 the LD.B and LD.BU instructions.
1824
1825 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1826
1827 * arc-dis.c (find_format): Check for extension flags.
1828 (print_flags): New function.
1829 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1830 .extAuxRegister.
1831 * arc-ext.c (arcExtMap_coreRegName): Use
1832 LAST_EXTENSION_CORE_REGISTER.
1833 (arcExtMap_coreReadWrite): Likewise.
1834 (dump_ARC_extmap): Update printing.
1835 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1836 (arc_aux_regs): Add cpu field.
1837 * arc-regs.h: Add cpu field, lower case name aux registers.
1838
1839 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1840
1841 * arc-tbl.h: Add rtsc, sleep with no arguments.
1842
1843 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1844
1845 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1846 Initialize.
1847 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1848 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1849 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1850 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1851 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1852 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1853 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1854 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1855 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1856 (arc_opcode arc_opcodes): Null terminate the array.
1857 (arc_num_opcodes): Remove.
1858 * arc-ext.h (INSERT_XOP): Define.
1859 (extInstruction_t): Likewise.
1860 (arcExtMap_instName): Delete.
1861 (arcExtMap_insn): New function.
1862 (arcExtMap_genOpcode): Likewise.
1863 * arc-ext.c (ExtInstruction): Remove.
1864 (create_map): Zero initialize instruction fields.
1865 (arcExtMap_instName): Remove.
1866 (arcExtMap_insn): New function.
1867 (dump_ARC_extmap): More info while debuging.
1868 (arcExtMap_genOpcode): New function.
1869 * arc-dis.c (find_format): New function.
1870 (print_insn_arc): Use find_format.
1871 (arc_get_disassembler): Enable dump_ARC_extmap only when
1872 debugging.
1873
1874 2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1875
1876 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1877 instruction bits out.
1878
1879 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1880
1881 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1882 * arc-opc.c (arc_flag_operands): Add new flags.
1883 (arc_flag_classes): Add new classes.
1884
1885 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1886
1887 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1888
1889 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1890
1891 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1892 encode1, rflt, crc16, and crc32 instructions.
1893 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1894 (arc_flag_classes): Add C_NPS_R.
1895 (insert_nps_bitop_size_2b): New function.
1896 (extract_nps_bitop_size_2b): Likewise.
1897 (insert_nps_bitop_uimm8): Likewise.
1898 (extract_nps_bitop_uimm8): Likewise.
1899 (arc_operands): Add new operand entries.
1900
1901 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1902
1903 * arc-regs.h: Add a new subclass field. Add double assist
1904 accumulator register values.
1905 * arc-tbl.h: Use DPA subclass to mark the double assist
1906 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1907 * arc-opc.c (RSP): Define instead of SP.
1908 (arc_aux_regs): Add the subclass field.
1909
1910 2016-04-05 Jiong Wang <jiong.wang@arm.com>
1911
1912 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1913
1914 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
1915
1916 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1917 NPS_R_SRC1.
1918
1919 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1920
1921 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1922 issues. No functional changes.
1923
1924 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1925
1926 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1927 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1928 (RTT): Remove duplicate.
1929 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1930 (PCT_CONFIG*): Remove.
1931 (D1L, D1H, D2H, D2L): Define.
1932
1933 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1934
1935 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1936
1937 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1938
1939 * arc-tbl.h (invld07): Remove.
1940 * arc-ext-tbl.h: New file.
1941 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1942 * arc-opc.c (arc_opcodes): Add ext-tbl include.
1943
1944 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1945
1946 Fix -Wstack-usage warnings.
1947 * aarch64-dis.c (print_operands): Substitute size.
1948 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1949
1950 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1951
1952 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1953 to get a proper diagnostic when an invalid ASR register is used.
1954
1955 2016-03-22 Nick Clifton <nickc@redhat.com>
1956
1957 * configure: Regenerate.
1958
1959 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1960
1961 * arc-nps400-tbl.h: New file.
1962 * arc-opc.c: Add top level comment.
1963 (insert_nps_3bit_dst): New function.
1964 (extract_nps_3bit_dst): New function.
1965 (insert_nps_3bit_src2): New function.
1966 (extract_nps_3bit_src2): New function.
1967 (insert_nps_bitop_size): New function.
1968 (extract_nps_bitop_size): New function.
1969 (arc_flag_operands): Add nps400 entries.
1970 (arc_flag_classes): Add nps400 entries.
1971 (arc_operands): Add nps400 entries.
1972 (arc_opcodes): Add nps400 include.
1973
1974 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1975
1976 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1977 the new class enum values.
1978
1979 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1980
1981 * arc-dis.c (print_insn_arc): Handle nps400.
1982
1983 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1984
1985 * arc-opc.c (BASE): Delete.
1986
1987 2016-03-18 Nick Clifton <nickc@redhat.com>
1988
1989 PR target/19721
1990 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1991 of MOV insn that aliases an ORR insn.
1992
1993 2016-03-16 Jiong Wang <jiong.wang@arm.com>
1994
1995 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1996
1997 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1998
1999 * mcore-opc.h: Add const qualifiers.
2000 * microblaze-opc.h (struct op_code_struct): Likewise.
2001 * sh-opc.h: Likewise.
2002 * tic4x-dis.c (tic4x_print_indirect): Likewise.
2003 (tic4x_print_op): Likewise.
2004
2005 2016-03-02 Alan Modra <amodra@gmail.com>
2006
2007 * or1k-desc.h: Regenerate.
2008 * fr30-ibld.c: Regenerate.
2009 * rl78-decode.c: Regenerate.
2010
2011 2016-03-01 Nick Clifton <nickc@redhat.com>
2012
2013 PR target/19747
2014 * rl78-dis.c (print_insn_rl78_common): Fix typo.
2015
2016 2016-02-24 Renlin Li <renlin.li@arm.com>
2017
2018 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
2019 (print_insn_coprocessor): Support fp16 instructions.
2020
2021 2016-02-24 Renlin Li <renlin.li@arm.com>
2022
2023 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
2024 vminnm, vrint(mpna).
2025
2026 2016-02-24 Renlin Li <renlin.li@arm.com>
2027
2028 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
2029 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
2030
2031 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
2032
2033 * i386-dis.c (print_insn): Parenthesize expression to prevent
2034 truncated addresses.
2035 (OP_J): Likewise.
2036
2037 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
2038 Janek van Oirschot <jvanoirs@synopsys.com>
2039
2040 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
2041 variable.
2042
2043 2016-02-04 Nick Clifton <nickc@redhat.com>
2044
2045 PR target/19561
2046 * msp430-dis.c (print_insn_msp430): Add a special case for
2047 decoding an RRC instruction with the ZC bit set in the extension
2048 word.
2049
2050 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
2051
2052 * cgen-ibld.in (insert_normal): Rework calculation of shift.
2053 * epiphany-ibld.c: Regenerate.
2054 * fr30-ibld.c: Regenerate.
2055 * frv-ibld.c: Regenerate.
2056 * ip2k-ibld.c: Regenerate.
2057 * iq2000-ibld.c: Regenerate.
2058 * lm32-ibld.c: Regenerate.
2059 * m32c-ibld.c: Regenerate.
2060 * m32r-ibld.c: Regenerate.
2061 * mep-ibld.c: Regenerate.
2062 * mt-ibld.c: Regenerate.
2063 * or1k-ibld.c: Regenerate.
2064 * xc16x-ibld.c: Regenerate.
2065 * xstormy16-ibld.c: Regenerate.
2066
2067 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
2068
2069 * epiphany-dis.c: Regenerated from latest cpu files.
2070
2071 2016-02-01 Michael McConville <mmcco@mykolab.com>
2072
2073 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
2074 test bit.
2075
2076 2016-01-25 Renlin Li <renlin.li@arm.com>
2077
2078 * arm-dis.c (mapping_symbol_for_insn): New function.
2079 (find_ifthen_state): Call mapping_symbol_for_insn().
2080
2081 2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
2082
2083 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
2084 of MSR UAO immediate operand.
2085
2086 2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
2087
2088 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
2089 instruction support.
2090
2091 2016-01-17 Alan Modra <amodra@gmail.com>
2092
2093 * configure: Regenerate.
2094
2095 2016-01-14 Nick Clifton <nickc@redhat.com>
2096
2097 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
2098 instructions that can support stack pointer operations.
2099 * rl78-decode.c: Regenerate.
2100 * rl78-dis.c: Fix display of stack pointer in MOVW based
2101 instructions.
2102
2103 2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
2104
2105 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
2106 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
2107 erxtatus_el1 and erxaddr_el1.
2108
2109 2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
2110
2111 * arm-dis.c (arm_opcodes): Add "esb".
2112 (thumb_opcodes): Likewise.
2113
2114 2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
2115
2116 * ppc-opc.c <xscmpnedp>: Delete.
2117 <xvcmpnedp>: Likewise.
2118 <xvcmpnedp.>: Likewise.
2119 <xvcmpnesp>: Likewise.
2120 <xvcmpnesp.>: Likewise.
2121
2122 2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
2123
2124 PR gas/13050
2125 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
2126 addition to ISA_A.
2127
2128 2016-01-01 Alan Modra <amodra@gmail.com>
2129
2130 Update year range in copyright notice of all files.
2131
2132 For older changes see ChangeLog-2015
2133 \f
2134 Copyright (C) 2016 Free Software Foundation, Inc.
2135
2136 Copying and distribution of this file, with or without modification,
2137 are permitted in any medium without royalty provided the copyright
2138 notice and this notice are preserved.
2139
2140 Local Variables:
2141 mode: change-log
2142 left-margin: 8
2143 fill-column: 74
2144 version-control: never
2145 End: