opcodes/ChangeLog

   1 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
   2
   3         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
   4         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
   5         (CGEN_CPUS): Add cris.
   6         (CRIS_DEPS): Define.
   7         (stamp-cris): New rule.
   8         * cgen.sh: Handle desc action.
   9         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
  10         * Makefile.in, configure: Regenerate.
  11
  12 2021-05-18  Job Noorman  <mtvec@pm.me>
  13
  14         PR 27814
  15         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
  16         the elf objects.
  17
  18 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
  19
  20         * arm-dis.c (mve_opcodes): Fix disassembly of
  21         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
  22         (is_mve_encoding_conflict): MVE vector loads should not match
  23         when P = W = 0.
  24         (is_mve_unpredictable): It's not unpredictable to use the same
  25         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
  26
  27 2021-05-11  Nick Clifton  <nickc@redhat.com>
  28
  29         PR 27840
  30         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
  31         the end of the code buffer.
  32
  33 2021-05-06  Stafford Horne  <shorne@gmail.com>
  34
  35         PR 21464
  36         * or1k-asm.c: Regenerate.
  37
  38 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
  39
  40         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
  41         info->insn_info_valid.
  42
  43 2021-04-26  Jan Beulich  <jbeulich@suse.com>
  44
  45         * i386-opc.tbl (lea): Add Optimize.
  46         * opcodes/i386-tbl.h: Re-generate.
  47
  48 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
  49
  50         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
  51         of l32r fetch and display referenced literal value.
  52
  53 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
  54
  55         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
  56         to 4 for literal disassembly.
  57
  58 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  59
  60         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
  61         for TLBI instruction.
  62
  63 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  64
  65         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
  66         DC instruction.
  67
  68 2021-04-19  Jan Beulich  <jbeulich@suse.com>
  69
  70         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
  71         "qualifier".
  72         (convert_mov_to_movewide): Add initializer for "value".
  73
  74 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  75
  76         * aarch64-opc.c: Add RME system registers.
  77
  78 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
  79
  80         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
  81         "addi d,CV,z" to "c.mv d,CV".
  82
  83 2021-04-12  Alan Modra  <amodra@gmail.com>
  84
  85         * configure.ac (--enable-checking): Add support.
  86         * config.in: Regenerate.
  87         * configure: Regenerate.
  88
  89 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
  90
  91         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
  92         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
  93
  94 2021-04-09  Alan Modra  <amodra@gmail.com>
  95
  96         * ppc-dis.c (struct dis_private): Add "special".
  97         (POWERPC_DIALECT): Delete.  Replace uses with..
  98         (private_data): ..this.  New inline function.
  99         (disassemble_init_powerpc): Init "special" names.
 100         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 101         field of prefix instructions.
 102         (bsearch_reloc, print_got_plt): New functions.
 103         (print_insn_powerpc): For pcrel instructions, print target address
 104         and symbol if known, and decode plt and got loads too.
 105
 106 2021-04-08  Alan Modra  <amodra@gmail.com>
 107
 108         PR 27684
 109         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 110
 111 2021-04-08  Alan Modra  <amodra@gmail.com>
 112
 113         PR 27676
 114         * ppc-opc.c (DCBT_EO): Move earlier.
 115         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 116         (powerpc_operands): Add THCT and THDS entries.
 117         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 118
 119 2021-04-06  Alan Modra  <amodra@gmail.com>
 120
 121         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 122         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 123         symbol_at_address_func.
 124
 125 2021-04-05  Alan Modra  <amodra@gmail.com>
 126
 127         * configure.ac: Don't check for limits.h, string.h, strings.h or
 128         stdlib.h.
 129         (AC_ISC_POSIX): Don't invoke.
 130         * sysdep.h: Include stdlib.h and string.h unconditionally.
 131         * i386-opc.h: Include limits.h unconditionally.
 132         * wasm32-dis.c: Likewise.
 133         * cgen-opc.c: Don't include alloca-conf.h.
 134         * config.in: Regenerate.
 135         * configure: Regenerate.
 136
 137 2021-04-01  Martin Liska  <mliska@suse.cz>
 138
 139         * arm-dis.c (strneq): Remove strneq and use startswith.
 140         * cr16-dis.c (print_insn_cr16): Likewise.
 141         * score-dis.c (streq): Likewise.
 142         (strneq): Likewise.
 143         * score7-dis.c (strneq): Likewise.
 144
 145 2021-04-01  Alan Modra  <amodra@gmail.com>
 146
 147         PR 27675
 148         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 149
 150 2021-03-31  Alan Modra  <amodra@gmail.com>
 151
 152         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 153         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 154         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 155         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 156         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 157         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 158         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 159         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 160         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 161         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 162         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 163         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 164         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 165         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 166         and TRUE with true throughout.
 167
 168 2021-03-31  Alan Modra  <amodra@gmail.com>
 169
 170         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 171         * aarch64-dis.h: Likewise.
 172         * aarch64-opc.c: Likewise.
 173         * avr-dis.c: Likewise.
 174         * csky-dis.c: Likewise.
 175         * nds32-asm.c: Likewise.
 176         * nds32-dis.c: Likewise.
 177         * nfp-dis.c: Likewise.
 178         * riscv-dis.c: Likewise.
 179         * s12z-dis.c: Likewise.
 180         * wasm32-dis.c: Likewise.
 181
 182 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 183
 184         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 185         (i386_seg_prefixes): New.
 186         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 187         (i386_seg_prefixes): Declare.
 188
 189 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 190
 191         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 192
 193 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 194
 195         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 196         * i386-reg.tbl (st): Move down.
 197         (st(0)): Delete. Extend comment.
 198         * i386-tbl.h: Re-generate.
 199
 200 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 201
 202         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 203         (cmpsd): Move next to cmps.
 204         (movsd): Move next to movs.
 205         (cmpxchg16b): Move to separate section.
 206         (fisttp, fisttpll): Likewise.
 207         (monitor, mwait): Likewise.
 208         * i386-tbl.h: Re-generate.
 209
 210 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 211
 212         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 213         (vpsadbw): Add C.
 214         * i386-tbl.h: Re-generate.
 215
 216 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 217
 218         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 219         pclmul, gfni): New templates. Use them wherever possible. Move
 220         SSE4.1 pextrw into respective section.
 221         * i386-tbl.h: Re-generate.
 222
 223 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 224
 225         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 226         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 227         "length".
 228         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 229         Convert all of their uses to representation in opcode.
 230
 231 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 232
 233         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 234         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 235         value of None. Shrink operands to 3 bits.
 236
 237 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 238
 239         * i386-gen.c (process_i386_opcode_modifier): New parameter
 240         "space".
 241         (output_i386_opcode): New local variable "space". Adjust
 242         process_i386_opcode_modifier() invocation.
 243         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 244         invocation.
 245         * i386-tbl.h: Re-generate.
 246
 247 2021-03-29  Alan Modra  <amodra@gmail.com>
 248
 249         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 250         (fp_qualifier_p, get_data_pattern): Likewise.
 251         (aarch64_get_operand_modifier_from_value): Likewise.
 252         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 253         (operand_variant_qualifier_p): Likewise.
 254         (qualifier_value_in_range_constraint_p): Likewise.
 255         (aarch64_get_qualifier_esize): Likewise.
 256         (aarch64_get_qualifier_nelem): Likewise.
 257         (aarch64_get_qualifier_standard_value): Likewise.
 258         (get_lower_bound, get_upper_bound): Likewise.
 259         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 260         (aarch64_print_operand): Likewise.
 261         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 262         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 263         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 264         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 265         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 266         (print_insn_tic6x): Likewise.
 267
 268 2021-03-29  Alan Modra  <amodra@gmail.com>
 269
 270         * arc-dis.c (extract_operand_value): Correct NULL cast.
 271         * frv-opc.h: Regenerate.
 272
 273 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 274
 275         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 276         MMX form.
 277         * i386-tbl.h: Re-generate.
 278
 279 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 280
 281         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 282         immediate in br.n instruction.
 283
 284 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 285
 286         * i386-dis.c (XMGatherD, VexGatherD): New.
 287         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 288         (print_insn): Check masking for S/G insns.
 289         (OP_E_memory): New local variable check_gather. Extend mandatory
 290         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 291         Extend check for disallowed 16-bit addressing.
 292         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 293         if()s to switch(). Check register conflicts for (VEX-encoded)
 294         gathers. Drop no longer reachable cases.
 295         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 296         vgatherdp*.
 297
 298 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 299
 300         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 301         zeroing-masking without masking.
 302
 303 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 304
 305         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 306         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 307         single-operand forms as deprecated.
 308         * i386-tbl.h: Re-generate.
 309
 310 2021-03-25  Alan Modra  <amodra@gmail.com>
 311
 312         PR 27647
 313         * ppc-opc.c (XLOCB_MASK): Delete.
 314         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 315         XLBH_MASK.
 316         (powerpc_opcodes): Accept a BH field on all extended forms of
 317         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 318
 319 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 320
 321         * i386-gen.c (output_i386_opcode): Drop processing of
 322         opcode_length. Calculate length from base_opcode. Adjust prefix
 323         encoding determination.
 324         (process_i386_opcodes): Drop output of fake opcode_length.
 325         * i386-opc.h (struct insn_template): Drop opcode_length field.
 326         * i386-opc.tbl: Drop opcode length field from all templates.
 327         * i386-tbl.h: Re-generate.
 328
 329 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 330
 331         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 332         parameter "prefix". Drop local variable "regular_encoding".
 333         Record prefix setting / check for consistency.
 334         (output_i386_opcode): Parse opcode_length and base_opcode
 335         earlier. Derive prefix encoding. Drop no longer applicable
 336         consistency checking. Adjust process_i386_opcode_modifier()
 337         invocation.
 338         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 339         invocation.
 340         * i386-tbl.h: Re-generate.
 341
 342 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 343
 344         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 345         check.
 346         * i386-opc.h (Prefix_*): Move #define-s.
 347         * i386-opc.tbl: Move pseudo prefix enumerator values to
 348         extension opcode field. Introduce pseudopfx template.
 349         * i386-tbl.h: Re-generate.
 350
 351 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 352
 353         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 354         comment.
 355         * i386-tbl.h: Re-generate.
 356
 357 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 358
 359         * i386-opc.h (struct insn_template): Move cpu_flags field past
 360         opcode_modifier one.
 361         * i386-tbl.h: Re-generate.
 362
 363 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 364
 365         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 366         * i386-opc.h (OpcodeSpace): New enumerator.
 367         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 368         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 369         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 370         (struct i386_opcode_modifier): New field opcodespace. Shrink
 371         opcodeprefix field.
 372         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 373         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 374         OpcodePrefix uses.
 375         * i386-tbl.h: Re-generate.
 376
 377 2021-03-22  Martin Liska  <mliska@suse.cz>
 378
 379         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 380         * arc-dis.c (parse_option): Likewise.
 381         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 382         * cris-dis.c (print_with_operands): Likewise.
 383         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 384         * i386-dis.c (print_insn): Likewise.
 385         * ia64-gen.c (fetch_insn_class): Likewise.
 386         (parse_resource_users): Likewise.
 387         (in_iclass): Likewise.
 388         (lookup_specifier): Likewise.
 389         (insert_opcode_dependencies): Likewise.
 390         * mips-dis.c (parse_mips_ase_option): Likewise.
 391         (parse_mips_dis_option): Likewise.
 392         * s390-dis.c (disassemble_init_s390): Likewise.
 393         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 394
 395 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 396
 397         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 398
 399 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 400
 401         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 402         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 403
 404 2021-03-12  Alan Modra  <amodra@gmail.com>
 405
 406         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 407
 408 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 409
 410         * i386-dis.c (OP_XMM): Re-order checks.
 411
 412 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 413
 414         * i386-dis.c (putop): Drop need_vex check when also checking
 415         vex.evex.
 416         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 417         checking vex.b.
 418
 419 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 420
 421         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 422         checks. Move case label past broadcast check.
 423
 424 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 425
 426         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 427         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 428         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 429         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 430         EVEX_W_0F38C7_M_0_L_2): Delete.
 431         (REG_EVEX_0F38C7_M_0_L_2): New.
 432         (intel_operand_size): Handle VEX and EVEX the same for
 433         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 434         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 435         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 436         vex_vsib_q_w_d_mode uses.
 437         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 438         0F38A1, and 0F38A3 entries.
 439         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 440         entry.
 441         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 442         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 443         0F38A3 entries.
 444
 445 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 446
 447         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 448         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 449         MOD_VEX_0FXOP_09_12): Rename to ...
 450         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 451         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 452         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 453         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 454         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 455         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 456         (reg_table): Adjust comments.
 457         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 458         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 459         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 460         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 461         (vex_len_table): Adjust opcode 0A_12 entry.
 462         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 463         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 464         (rm_table): Move hreset entry.
 465
 466 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 467
 468         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 469         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 470         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 471         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 472         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 473         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 474         (get_valid_dis386): Also handle 512-bit vector length when
 475         vectoring into vex_len_table[].
 476         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 477         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 478         entries.
 479         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 480         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 481         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 482         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 483         entries.
 484
 485 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 486
 487         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 488         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 489         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 490         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 491         entries.
 492         * i386-dis-evex-len.h (evex_len_table): Likewise.
 493         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 494
 495 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 496
 497         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 498         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 499         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 500         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 501         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 502         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 503         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 504         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 505         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 506         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 507         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 508         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 509         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 510         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 511         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 512         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 513         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 514         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 515         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 516         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 517         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 518         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 519         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 520         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 521         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 522         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 523         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 524         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 525         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 526         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 527         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 528         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 529         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 530         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 531         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 532         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 533         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 534         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 535         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 536         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 537         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 538         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 539         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 540         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 541         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 542         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 543         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 544         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 545         EVEX_W_0F3A43_L_n): New.
 546         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 547         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 548         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 549         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 550         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 551         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 552         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 553         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 554         0F385B, 0F38C6, and 0F38C7 entries.
 555         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 556         0F38C6 and 0F38C7.
 557         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 558         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 559         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 560         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 561
 562 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 563
 564         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 565         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 566         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 567         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 568         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 569         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 570         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 571         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 572         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 573         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 574         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 575         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 576         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 577         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 578         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 579         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 580         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 581         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 582         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 583         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 584         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 585         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 586         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 587         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 588         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 589         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 590         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 591         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 592         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 593         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 594         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 595         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 596         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 597         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 598         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 599         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 600         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 601         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 602         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 603         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 604         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 605         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 606         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 607         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 608         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 609         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 610         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 611         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 612         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 613         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 614         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 615         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 616         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 617         VEX_W_0F99_P_2_LEN_0): Delete.
 618         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 619         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 620         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 621         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 622         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 623         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 624         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 625         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 626         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 627         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 628         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 629         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 630         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 631         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 632         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 633         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 634         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 635         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 636         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 637         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 638         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 639         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 640         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 641         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 642         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 643         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 644         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 645         (prefix_table): No longer link to vex_len_table[] for opcodes
 646         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 647         0F92, 0F93, 0F98, and 0F99.
 648         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 649         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 650         0F98, and 0F99.
 651         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 652         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 653         0F98, and 0F99.
 654         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 655         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 656         0F98, and 0F99.
 657         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 658         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 659         0F98, and 0F99.
 660
 661 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 662
 663         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 664         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 665         REG_VEX_0F73_M_0 respectively.
 666         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 667         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 668         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 669         MOD_VEX_0F73_REG_7): Delete.
 670         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 671         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 672         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 673         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 674         PREFIX_VEX_0F3AF0_L_0 respectively.
 675         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 676         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 677         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 678         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 679         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 680         VEX_LEN_0F38F7): New.
 681         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 682         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 683         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 684         0F38F3.
 685         (prefix_table): No longer link to vex_len_table[] for opcodes
 686         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 687         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 688         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 689         0F38F6, 0F38F7, and 0F3AF0.
 690         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 691         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 692         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 693         0F73.
 694
 695 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 696
 697         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 698         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 699         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 700         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 701         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 702         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 703         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 704         73.
 705         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 706         0F72, and 0F73.
 707         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 708         0F73.
 709
 710 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 711
 712         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 713         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 714         (reg_table): Don't link to mod_table[] where not needed. Add
 715         PREFIX_IGNORED to nop entries.
 716         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 717         (mod_table): Add nop entries next to prefetch ones. Drop
 718         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 719         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 720         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 721         PREFIX_OPCODE from endbr* entries.
 722         (get_valid_dis386): Also consider entry's name when zapping
 723         vindex.
 724         (print_insn): Handle PREFIX_IGNORED.
 725
 726 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 727
 728         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 729         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 730         element.
 731         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 732         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 733         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 734         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 735         (struct i386_opcode_modifier): Delete notrackprefixok,
 736         islockable, hleprefixok, and repprefixok fields. Add prefixok
 737         field.
 738         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 739         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 740         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 741         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 742         Replace HLEPrefixOk.
 743         * opcodes/i386-tbl.h: Re-generate.
 744
 745 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 746
 747         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 748         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 749         64-bit form.
 750         * opcodes/i386-tbl.h: Re-generate.
 751
 752 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 753
 754         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 755         for {} instead of {0}. Don't look for '0'.
 756         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 757         size specifiers.
 758
 759 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 760
 761         PR 27158
 762         * riscv-dis.c (print_insn_args): Updated encoding macros.
 763         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 764         (match_c_addi16sp): Updated encoding macros.
 765         (match_c_lui): Likewise.
 766         (match_c_lui_with_hint): Likewise.
 767         (match_c_addi4spn): Likewise.
 768         (match_c_slli): Likewise.
 769         (match_slli_as_c_slli): Likewise.
 770         (match_c_slli64): Likewise.
 771         (match_srxi_as_c_srxi): Likewise.
 772         (riscv_insn_types): Added .insn css/cl/cs.
 773
 774 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 775
 776         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 777         (default_priv_spec): Updated type to riscv_spec_class.
 778         (parse_riscv_dis_option): Updated.
 779         * riscv-opc.c: Moved stuff and make the file tidy.
 780
 781 2021-02-17  Alan Modra  <amodra@gmail.com>
 782
 783         * wasm32-dis.c: Include limits.h.
 784         (CHAR_BIT): Provide backup define.
 785         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 786         Correct signed overflow checking.
 787
 788 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 789
 790         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 791         * i386-tbl.h: Re-generate.
 792
 793 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 794
 795         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 796         Oword.
 797         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 798
 799 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 800
 801         * s390-mkopc.c (main): Accept arch14 as cpu string.
 802         * s390-opc.txt: Add new arch14 instructions.
 803
 804 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 805
 806         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 807         favour of LIBINTL.
 808         * configure: Regenerated.
 809
 810 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 811
 812         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 813         * tic54x-opc.c (regs): Rename to ...
 814         (tic54x_regs): ... this.
 815         (mmregs): Rename to ...
 816         (tic54x_mmregs): ... this.
 817         (condition_codes): Rename to ...
 818         (tic54x_condition_codes): ... this.
 819         (cc2_codes): Rename to ...
 820         (tic54x_cc2_codes): ... this.
 821         (cc3_codes): Rename to ...
 822         (tic54x_cc3_codes): ... this.
 823         (status_bits): Rename to ...
 824         (tic54x_status_bits): ... this.
 825         (misc_symbols): Rename to ...
 826         (tic54x_misc_symbols): ... this.
 827
 828 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 829
 830         * riscv-opc.c (MASK_RVB_IMM): Removed.
 831         (riscv_opcodes): Removed zb* instructions.
 832         (riscv_ext_version_table): Removed versions for zb*.
 833
 834 2021-01-26  Alan Modra  <amodra@gmail.com>
 835
 836         * i386-gen.c (parse_template): Ensure entire template_instance
 837         is initialised.
 838
 839 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 840
 841         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 842         (riscv_fpr_names_abi): Likewise.
 843         (riscv_opcodes): Likewise.
 844         (riscv_insn_types): Likewise.
 845
 846 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 847
 848         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 849
 850 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 851
 852         * riscv-dis.c: Comments tidy and improvement.
 853         * riscv-opc.c: Likewise.
 854
 855 2021-01-13  Alan Modra  <amodra@gmail.com>
 856
 857         * Makefile.in: Regenerate.
 858
 859 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 860
 861         PR binutils/26792
 862         * configure.ac: Use GNU_MAKE_JOBSERVER.
 863         * aclocal.m4: Regenerated.
 864         * configure: Likewise.
 865
 866 2021-01-12  Nick Clifton  <nickc@redhat.com>
 867
 868         * po/sr.po: Updated Serbian translation.
 869
 870 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 871
 872         PR ld/27173
 873         * configure: Regenerated.
 874
 875 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 876
 877         * aarch64-asm-2.c: Regenerate.
 878         * aarch64-dis-2.c: Likewise.
 879         * aarch64-opc-2.c: Likewise.
 880         * aarch64-opc.c (aarch64_print_operand):
 881         Delete handling of AARCH64_OPND_CSRE_CSR.
 882         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 883         (CSRE): Likewise.
 884         (_CSRE_INSN): Likewise.
 885         (aarch64_opcode_table): Delete csr.
 886
 887 2021-01-11  Nick Clifton  <nickc@redhat.com>
 888
 889         * po/de.po: Updated German translation.
 890         * po/fr.po: Updated French translation.
 891         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 892         * po/sv.po: Updated Swedish translation.
 893         * po/uk.po: Updated Ukranian translation.
 894
 895 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 896
 897         * configure: Regenerated.
 898
 899 2021-01-09  Nick Clifton  <nickc@redhat.com>
 900
 901         * configure: Regenerate.
 902         * po/opcodes.pot: Regenerate.
 903
 904 2021-01-09  Nick Clifton  <nickc@redhat.com>
 905
 906         * 2.36 release branch crated.
 907
 908 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 909
 910         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 911         (DW, (XRC_MASK): Define.
 912         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 913
 914 2021-01-09  Alan Modra  <amodra@gmail.com>
 915
 916         * configure: Regenerate.
 917
 918 2021-01-08  Nick Clifton  <nickc@redhat.com>
 919
 920         * po/sv.po: Updated Swedish translation.
 921
 922 2021-01-08  Nick Clifton  <nickc@redhat.com>
 923
 924         PR 27129
 925         * aarch64-dis.c (determine_disassembling_preference): Move call to
 926         aarch64_match_operands_constraint outside of the assertion.
 927         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 928         Replace with a return of FALSE.
 929
 930         PR 27139
 931         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 932         core system register.
 933
 934 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 935
 936         * configure: Regenerate.
 937
 938 2021-01-07  Nick Clifton  <nickc@redhat.com>
 939
 940         * po/fr.po: Updated French translation.
 941
 942 2021-01-07  Fredrik Noring  <noring@nocrew.org>
 943
 944         * m68k-opc.c (chkl): Change minimum architecture requirement to
 945         m68020.
 946
 947 2021-01-07  Philipp Tomsich  <prt@gnu.org>
 948
 949         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
 950
 951 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
 952             Jim Wilson  <jimw@sifive.com>
 953             Andrew Waterman  <andrew@sifive.com>
 954             Maxim Blinov  <maxim.blinov@embecosm.com>
 955             Kito Cheng  <kito.cheng@sifive.com>
 956             Nelson Chu  <nelson.chu@sifive.com>
 957
 958         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
 959         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
 960
 961 2021-01-01  Alan Modra  <amodra@gmail.com>
 962
 963         Update year range in copyright notice of all files.
 964
 965 For older changes see ChangeLog-2020
 966 \f
 967 Copyright (C) 2021 Free Software Foundation, Inc.
 968
 969 Copying and distribution of this file, with or without modification,
 970 are permitted in any medium without royalty provided the copyright
 971 notice and this notice are preserved.
 972
 973 Local Variables:
 974 mode: change-log
 975 left-margin: 8
 976 fill-column: 74
 977 version-control: never
 978 End: