opcodes/ChangeLog

   1 2022-01-24  Nick Clifton  <nickc@redhat.com>
   2
   3         * po/ro.po: Updated Romanian translation.
   4         * po/uk.po: Updated Ukranian translation.
   5
   6 2022-01-22  Nick Clifton  <nickc@redhat.com>
   7
   8         * configure: Regenerate.
   9         * po/opcodes.pot: Regenerate.
  10
  11 2022-01-22  Nick Clifton  <nickc@redhat.com>
  12
  13         * 2.38 release branch created.
  14
  15 2022-01-17  Nick Clifton  <nickc@redhat.com>
  16
  17         * Makefile.in: Regenerate.
  18         * po/opcodes.pot: Regenerate.
  19
  20 2021-12-02  Marcus Nilsson  <brainbomb@gmail.com>
  21
  22         * avr-dis.c (avr_operand); Pass in disassemble_info and fill
  23         in insn_type on branching instructions.
  24
  25 2021-11-25  Andrew Burgess  <aburgess@redhat.com>
  26             Simon Cook  <simon.cook@embecosm.com>
  27
  28         * riscv-dis.c (enum riscv_option_arg_t): New enum typedef.
  29         (riscv_options): New static global.
  30         (disassembler_options_riscv): New function.
  31         (print_riscv_disassembler_options): Rewrite to use
  32         disassembler_options_riscv.
  33
  34 2021-11-25  Nick Clifton  <nickc@redhat.com>
  35
  36         PR 28614
  37         * aarch64-asm.c: Replace assert(0) with real code.
  38         * aarch64-dis.c: Likewise.
  39         * aarch64-opc.c: Likewise.
  40
  41 2021-11-25  Nick Clifton  <nickc@redhat.com>
  42
  43         * po/fr.po; Updated French translation.
  44
  45 2021-10-27  Maciej W. Rozycki  <macro@embecosm.com>
  46
  47         * Makefile.am: Remove obsolete comment.
  48         * configure.ac: Refer `libbfd.la' to link shared BFD library
  49         except for Cygwin.
  50         * Makefile.in: Regenerate.
  51         * configure: Regenerate.
  52
  53 2021-09-27  Nick Alcock  <nick.alcock@oracle.com>
  54
  55         * configure: Regenerate.
  56
  57 2021-09-25  Peter Bergner  <bergner@linux.ibm.com>
  58
  59         * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
  60         on POWER5 and later.
  61
  62 2021-09-20  Andrew Burgess  <andrew.burgess@embecosm.com>
  63
  64         * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
  65         before an unknown instruction, '%d' is replaced with the
  66         instruction length.
  67
  68 2021-09-02  Nick Clifton  <nickc@redhat.com>
  69
  70         PR 28292
  71         * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
  72         of BFD_RELOC_16.
  73
  74 2021-08-17  Shahab Vahedi <shahab@synopsys.com>
  75
  76         * arc-regs.h (DEF): Fix the register numbers.
  77
  78 2021-08-10  Nick Clifton  <nickc@redhat.com>
  79
  80         * po/sr.po: Updated Serbian translation.
  81
  82 2021-07-26  Chenghua Xu  <xuchenghua@loongson.cn>
  83
  84         * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
  85
  86 2021-06-07  Andreas Krebbel  <krebbel@linux.ibm.com>
  87
  88         * s390-opc.txt: Add qpaci.
  89
  90 2021-07-03  Nick Clifton  <nickc@redhat.com>
  91
  92         * configure: Regenerate.
  93         * po/opcodes.pot: Regenerate.
  94
  95 2021-07-03  Nick Clifton  <nickc@redhat.com>
  96
  97         * 2.37 release branch created.
  98
  99 2021-07-02  Alan Modra  <amodra@gmail.com>
 100
 101         * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
 102         (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
 103         (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
 104         (nds32_opcodes, nds32_operand_fields, nds32_keywords),
 105         (nds32_keyword_gpr): Move declarations to..
 106         * nds32-asm.h: ..here, constifying to match definitions.
 107
 108 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 109
 110         * Makefile.am (GUILE): New variable.
 111         (CGEN): Use $(GUILE).
 112         * Makefile.in: Regenerate.
 113
 114 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 115
 116         * mep-asm.c (macros): Mark static & const.
 117         (lookup_macro): Change return & m to const.
 118         (expand_macro): Change mac to const.
 119         (expand_string): Change pmacro to const.
 120
 121 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 122
 123         * nds32-asm.c (operand_fields): Rename to ...
 124         (nds32_operand_fields): ... this.
 125         (keyword_gpr): Rename to ...
 126         (nds32_keyword_gpr): ... this.
 127         (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
 128         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
 129         keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
 130         keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
 131         keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
 132         Mark static.
 133         (keywords): Rename to ...
 134         (nds32_keywords): ... this.
 135         * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
 136         keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
 137
 138 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 139
 140         * z80-dis.c (opc_ed): Make const.
 141         (pref_ed): Make p const.
 142
 143 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 144
 145         * microblaze-dis.c (get_field_special): Make op const.
 146         (read_insn_microblaze): Make opr & op const.  Rename opcodes to
 147         microblaze_opcodes.
 148         (print_insn_microblaze): Make op & pop const.
 149         (get_insn_microblaze): Make op const.  Rename opcodes to
 150         microblaze_opcodes.
 151         (microblaze_get_target_address): Likewise.
 152         * microblaze-opc.h (struct op_code_struct): Make const.
 153         Rename opcodes to microblaze_opcodes.
 154
 155 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 156
 157         * aarch64-gen.c (aarch64_opcode_table): Add const.
 158         * aarch64-tbl.h (aarch64_opcode_table): Likewise.
 159
 160 2021-06-22  Andrew Burgess  <andrew.burgess@embecosm.com>
 161
 162         * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
 163         available.
 164
 165 2021-06-22  Alan Modra  <amodra@gmail.com>
 166
 167         * pj-dis.c (print_insn_pj): Don't print trailing tab.  Do
 168         print separator for pcrel insns.
 169
 170 2021-06-19  Alan Modra  <amodra@gmail.com>
 171
 172         * vax-dis.c (print_insn_vax): Avoid pointer overflow.
 173
 174 2021-06-19  Alan Modra  <amodra@gmail.com>
 175
 176         * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
 177         entire buffer.
 178
 179 2021-06-17  Alan Modra  <amodra@gmail.com>
 180
 181         * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
 182         in table.
 183
 184 2021-06-03  Alan Modra  <amodra@gmail.com>
 185
 186         PR 1202
 187         * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
 188         Use unsigned int for inst.
 189
 190 2021-06-02  Shahab Vahedi  <shahab@synopsys.com>
 191
 192         * arc-dis.c (arc_option_arg_t): New enumeration.
 193         (arc_options): New variable.
 194         (disassembler_options_arc): New function.
 195         (print_arc_disassembler_options): Reimplement in terms of
 196         "disassembler_options_arc".
 197
 198 2021-05-29  Alan Modra  <amodra@gmail.com>
 199
 200         * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
 201         Don't special case PPC_OPCODE_RAW.
 202         (lookup_prefix): Likewise.
 203         (lookup_vle, lookup_spe2): Similarly.  Add dialect parameter and..
 204         (print_insn_powerpc): ..update caller.
 205         * ppc-opc.c (EXT): Define.
 206         (powerpc_opcodes): Mark extended mnemonics with EXT.
 207         (prefix_opcodes, vle_opcodes): Likewise.
 208         (XISEL, XISEL_MASK): Add cr field and simplify.
 209         (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
 210         all isel variants to where the base mnemonic belongs.  Sort dstt,
 211         dststt and dssall.
 212
 213 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 214
 215         * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
 216         COP3 opcode instructions.
 217
 218 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 219
 220         * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
 221         "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
 222         "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
 223         "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
 224         "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
 225         "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
 226         "cop2", and "cop3" entries.
 227
 228 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 229
 230         * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
 231         entries and associated comments.
 232
 233 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 234
 235         * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
 236         of "c0".
 237
 238 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 239
 240         * mips-dis.c (mips_cp1_names_mips): New variable.
 241         (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
 242         for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
 243         "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
 244         "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
 245         "r12000", "r14000", "r16000", "mips5", "loongson2e", and
 246         "loongson2f".
 247
 248 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 249
 250         * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
 251         handling code over to...
 252         <OP_REG_CONTROL>: ... this new case.
 253         * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
 254         (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
 255         "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
 256         replacing the `G' operand code with `g'.  Update "cftc1" and
 257         "cftc2" entries replacing the `E' operand code with `y'.
 258         * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
 259         (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
 260         entries replacing the `G' operand code with `g'.
 261
 262 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 263
 264         * mips-dis.c (mips_cp0_names_r3900): New variable.
 265         (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
 266         for "r3900".
 267
 268 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 269
 270         * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
 271         and "mtthc2" to using the `G' rather than `g' operand code for
 272         the coprocessor control register referred.
 273
 274 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 275
 276         * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
 277         entries with each other.
 278
 279 2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
 280
 281         * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
 282
 283 2021-05-25  Alan Modra  <amodra@gmail.com>
 284
 285         * cris-desc.c: Regenerate.
 286         * cris-desc.h: Regenerate.
 287         * cris-opc.h: Regenerate.
 288         * po/POTFILES.in: Regenerate.
 289
 290 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
 291
 292         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
 293         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
 294         (CGEN_CPUS): Add cris.
 295         (CRIS_DEPS): Define.
 296         (stamp-cris): New rule.
 297         * cgen.sh: Handle desc action.
 298         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
 299         * Makefile.in, configure: Regenerate.
 300
 301 2021-05-18  Job Noorman  <mtvec@pm.me>
 302
 303         PR 27814
 304         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
 305         the elf objects.
 306
 307 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
 308
 309         * arm-dis.c (mve_opcodes): Fix disassembly of
 310         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
 311         (is_mve_encoding_conflict): MVE vector loads should not match
 312         when P = W = 0.
 313         (is_mve_unpredictable): It's not unpredictable to use the same
 314         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
 315
 316 2021-05-11  Nick Clifton  <nickc@redhat.com>
 317
 318         PR 27840
 319         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
 320         the end of the code buffer.
 321
 322 2021-05-06  Stafford Horne  <shorne@gmail.com>
 323
 324         PR 21464
 325         * or1k-asm.c: Regenerate.
 326
 327 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
 328
 329         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
 330         info->insn_info_valid.
 331
 332 2021-04-26  Jan Beulich  <jbeulich@suse.com>
 333
 334         * i386-opc.tbl (lea): Add Optimize.
 335         * opcodes/i386-tbl.h: Re-generate.
 336
 337 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 338
 339         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
 340         of l32r fetch and display referenced literal value.
 341
 342 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 343
 344         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
 345         to 4 for literal disassembly.
 346
 347 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 348
 349         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
 350         for TLBI instruction.
 351
 352 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 353
 354         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
 355         DC instruction.
 356
 357 2021-04-19  Jan Beulich  <jbeulich@suse.com>
 358
 359         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
 360         "qualifier".
 361         (convert_mov_to_movewide): Add initializer for "value".
 362
 363 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 364
 365         * aarch64-opc.c: Add RME system registers.
 366
 367 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
 368
 369         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
 370         "addi d,CV,z" to "c.mv d,CV".
 371
 372 2021-04-12  Alan Modra  <amodra@gmail.com>
 373
 374         * configure.ac (--enable-checking): Add support.
 375         * config.in: Regenerate.
 376         * configure: Regenerate.
 377
 378 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
 379
 380         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
 381         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 382
 383 2021-04-09  Alan Modra  <amodra@gmail.com>
 384
 385         * ppc-dis.c (struct dis_private): Add "special".
 386         (POWERPC_DIALECT): Delete.  Replace uses with..
 387         (private_data): ..this.  New inline function.
 388         (disassemble_init_powerpc): Init "special" names.
 389         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 390         field of prefix instructions.
 391         (bsearch_reloc, print_got_plt): New functions.
 392         (print_insn_powerpc): For pcrel instructions, print target address
 393         and symbol if known, and decode plt and got loads too.
 394
 395 2021-04-08  Alan Modra  <amodra@gmail.com>
 396
 397         PR 27684
 398         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 399
 400 2021-04-08  Alan Modra  <amodra@gmail.com>
 401
 402         PR 27676
 403         * ppc-opc.c (DCBT_EO): Move earlier.
 404         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 405         (powerpc_operands): Add THCT and THDS entries.
 406         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 407
 408 2021-04-06  Alan Modra  <amodra@gmail.com>
 409
 410         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 411         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 412         symbol_at_address_func.
 413
 414 2021-04-05  Alan Modra  <amodra@gmail.com>
 415
 416         * configure.ac: Don't check for limits.h, string.h, strings.h or
 417         stdlib.h.
 418         (AC_ISC_POSIX): Don't invoke.
 419         * sysdep.h: Include stdlib.h and string.h unconditionally.
 420         * i386-opc.h: Include limits.h unconditionally.
 421         * wasm32-dis.c: Likewise.
 422         * cgen-opc.c: Don't include alloca-conf.h.
 423         * config.in: Regenerate.
 424         * configure: Regenerate.
 425
 426 2021-04-01  Martin Liska  <mliska@suse.cz>
 427
 428         * arm-dis.c (strneq): Remove strneq and use startswith.
 429         * cr16-dis.c (print_insn_cr16): Likewise.
 430         * score-dis.c (streq): Likewise.
 431         (strneq): Likewise.
 432         * score7-dis.c (strneq): Likewise.
 433
 434 2021-04-01  Alan Modra  <amodra@gmail.com>
 435
 436         PR 27675
 437         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 438
 439 2021-03-31  Alan Modra  <amodra@gmail.com>
 440
 441         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 442         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 443         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 444         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 445         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 446         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 447         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 448         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 449         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 450         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 451         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 452         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 453         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 454         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 455         and TRUE with true throughout.
 456
 457 2021-03-31  Alan Modra  <amodra@gmail.com>
 458
 459         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 460         * aarch64-dis.h: Likewise.
 461         * aarch64-opc.c: Likewise.
 462         * avr-dis.c: Likewise.
 463         * csky-dis.c: Likewise.
 464         * nds32-asm.c: Likewise.
 465         * nds32-dis.c: Likewise.
 466         * nfp-dis.c: Likewise.
 467         * riscv-dis.c: Likewise.
 468         * s12z-dis.c: Likewise.
 469         * wasm32-dis.c: Likewise.
 470
 471 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 472
 473         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 474         (i386_seg_prefixes): New.
 475         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 476         (i386_seg_prefixes): Declare.
 477
 478 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 479
 480         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 481
 482 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 483
 484         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 485         * i386-reg.tbl (st): Move down.
 486         (st(0)): Delete. Extend comment.
 487         * i386-tbl.h: Re-generate.
 488
 489 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 490
 491         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 492         (cmpsd): Move next to cmps.
 493         (movsd): Move next to movs.
 494         (cmpxchg16b): Move to separate section.
 495         (fisttp, fisttpll): Likewise.
 496         (monitor, mwait): Likewise.
 497         * i386-tbl.h: Re-generate.
 498
 499 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 500
 501         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 502         (vpsadbw): Add C.
 503         * i386-tbl.h: Re-generate.
 504
 505 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 506
 507         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 508         pclmul, gfni): New templates. Use them wherever possible. Move
 509         SSE4.1 pextrw into respective section.
 510         * i386-tbl.h: Re-generate.
 511
 512 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 513
 514         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 515         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 516         "length".
 517         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 518         Convert all of their uses to representation in opcode.
 519
 520 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 521
 522         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 523         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 524         value of None. Shrink operands to 3 bits.
 525
 526 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 527
 528         * i386-gen.c (process_i386_opcode_modifier): New parameter
 529         "space".
 530         (output_i386_opcode): New local variable "space". Adjust
 531         process_i386_opcode_modifier() invocation.
 532         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 533         invocation.
 534         * i386-tbl.h: Re-generate.
 535
 536 2021-03-29  Alan Modra  <amodra@gmail.com>
 537
 538         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 539         (fp_qualifier_p, get_data_pattern): Likewise.
 540         (aarch64_get_operand_modifier_from_value): Likewise.
 541         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 542         (operand_variant_qualifier_p): Likewise.
 543         (qualifier_value_in_range_constraint_p): Likewise.
 544         (aarch64_get_qualifier_esize): Likewise.
 545         (aarch64_get_qualifier_nelem): Likewise.
 546         (aarch64_get_qualifier_standard_value): Likewise.
 547         (get_lower_bound, get_upper_bound): Likewise.
 548         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 549         (aarch64_print_operand): Likewise.
 550         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 551         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 552         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 553         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 554         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 555         (print_insn_tic6x): Likewise.
 556
 557 2021-03-29  Alan Modra  <amodra@gmail.com>
 558
 559         * arc-dis.c (extract_operand_value): Correct NULL cast.
 560         * frv-opc.h: Regenerate.
 561
 562 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 563
 564         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 565         MMX form.
 566         * i386-tbl.h: Re-generate.
 567
 568 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 569
 570         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 571         immediate in br.n instruction.
 572
 573 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 574
 575         * i386-dis.c (XMGatherD, VexGatherD): New.
 576         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 577         (print_insn): Check masking for S/G insns.
 578         (OP_E_memory): New local variable check_gather. Extend mandatory
 579         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 580         Extend check for disallowed 16-bit addressing.
 581         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 582         if()s to switch(). Check register conflicts for (VEX-encoded)
 583         gathers. Drop no longer reachable cases.
 584         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 585         vgatherdp*.
 586
 587 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 588
 589         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 590         zeroing-masking without masking.
 591
 592 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 593
 594         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 595         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 596         single-operand forms as deprecated.
 597         * i386-tbl.h: Re-generate.
 598
 599 2021-03-25  Alan Modra  <amodra@gmail.com>
 600
 601         PR 27647
 602         * ppc-opc.c (XLOCB_MASK): Delete.
 603         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 604         XLBH_MASK.
 605         (powerpc_opcodes): Accept a BH field on all extended forms of
 606         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 607
 608 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 609
 610         * i386-gen.c (output_i386_opcode): Drop processing of
 611         opcode_length. Calculate length from base_opcode. Adjust prefix
 612         encoding determination.
 613         (process_i386_opcodes): Drop output of fake opcode_length.
 614         * i386-opc.h (struct insn_template): Drop opcode_length field.
 615         * i386-opc.tbl: Drop opcode length field from all templates.
 616         * i386-tbl.h: Re-generate.
 617
 618 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 619
 620         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 621         parameter "prefix". Drop local variable "regular_encoding".
 622         Record prefix setting / check for consistency.
 623         (output_i386_opcode): Parse opcode_length and base_opcode
 624         earlier. Derive prefix encoding. Drop no longer applicable
 625         consistency checking. Adjust process_i386_opcode_modifier()
 626         invocation.
 627         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 628         invocation.
 629         * i386-tbl.h: Re-generate.
 630
 631 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 632
 633         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 634         check.
 635         * i386-opc.h (Prefix_*): Move #define-s.
 636         * i386-opc.tbl: Move pseudo prefix enumerator values to
 637         extension opcode field. Introduce pseudopfx template.
 638         * i386-tbl.h: Re-generate.
 639
 640 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 641
 642         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 643         comment.
 644         * i386-tbl.h: Re-generate.
 645
 646 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 647
 648         * i386-opc.h (struct insn_template): Move cpu_flags field past
 649         opcode_modifier one.
 650         * i386-tbl.h: Re-generate.
 651
 652 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 653
 654         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 655         * i386-opc.h (OpcodeSpace): New enumerator.
 656         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 657         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 658         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 659         (struct i386_opcode_modifier): New field opcodespace. Shrink
 660         opcodeprefix field.
 661         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 662         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 663         OpcodePrefix uses.
 664         * i386-tbl.h: Re-generate.
 665
 666 2021-03-22  Martin Liska  <mliska@suse.cz>
 667
 668         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 669         * arc-dis.c (parse_option): Likewise.
 670         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 671         * cris-dis.c (print_with_operands): Likewise.
 672         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 673         * i386-dis.c (print_insn): Likewise.
 674         * ia64-gen.c (fetch_insn_class): Likewise.
 675         (parse_resource_users): Likewise.
 676         (in_iclass): Likewise.
 677         (lookup_specifier): Likewise.
 678         (insert_opcode_dependencies): Likewise.
 679         * mips-dis.c (parse_mips_ase_option): Likewise.
 680         (parse_mips_dis_option): Likewise.
 681         * s390-dis.c (disassemble_init_s390): Likewise.
 682         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 683
 684 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 685
 686         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 687
 688 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 689
 690         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 691         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 692
 693 2021-03-12  Alan Modra  <amodra@gmail.com>
 694
 695         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 696
 697 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 698
 699         * i386-dis.c (OP_XMM): Re-order checks.
 700
 701 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 702
 703         * i386-dis.c (putop): Drop need_vex check when also checking
 704         vex.evex.
 705         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 706         checking vex.b.
 707
 708 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 709
 710         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 711         checks. Move case label past broadcast check.
 712
 713 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 714
 715         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 716         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 717         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 718         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 719         EVEX_W_0F38C7_M_0_L_2): Delete.
 720         (REG_EVEX_0F38C7_M_0_L_2): New.
 721         (intel_operand_size): Handle VEX and EVEX the same for
 722         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 723         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 724         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 725         vex_vsib_q_w_d_mode uses.
 726         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 727         0F38A1, and 0F38A3 entries.
 728         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 729         entry.
 730         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 731         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 732         0F38A3 entries.
 733
 734 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 735
 736         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 737         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 738         MOD_VEX_0FXOP_09_12): Rename to ...
 739         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 740         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 741         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 742         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 743         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 744         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 745         (reg_table): Adjust comments.
 746         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 747         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 748         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 749         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 750         (vex_len_table): Adjust opcode 0A_12 entry.
 751         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 752         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 753         (rm_table): Move hreset entry.
 754
 755 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 756
 757         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 758         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 759         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 760         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 761         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 762         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 763         (get_valid_dis386): Also handle 512-bit vector length when
 764         vectoring into vex_len_table[].
 765         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 766         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 767         entries.
 768         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 769         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 770         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 771         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 772         entries.
 773
 774 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 775
 776         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 777         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 778         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 779         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 780         entries.
 781         * i386-dis-evex-len.h (evex_len_table): Likewise.
 782         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 783
 784 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 785
 786         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 787         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 788         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 789         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 790         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 791         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 792         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 793         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 794         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 795         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 796         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 797         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 798         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 799         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 800         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 801         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 802         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 803         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 804         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 805         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 806         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 807         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 808         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 809         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 810         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 811         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 812         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 813         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 814         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 815         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 816         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 817         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 818         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 819         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 820         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 821         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 822         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 823         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 824         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 825         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 826         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 827         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 828         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 829         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 830         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 831         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 832         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 833         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 834         EVEX_W_0F3A43_L_n): New.
 835         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 836         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 837         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 838         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 839         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 840         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 841         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 842         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 843         0F385B, 0F38C6, and 0F38C7 entries.
 844         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 845         0F38C6 and 0F38C7.
 846         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 847         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 848         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 849         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 850
 851 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 852
 853         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 854         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 855         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 856         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 857         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 858         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 859         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 860         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 861         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 862         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 863         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 864         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 865         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 866         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 867         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 868         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 869         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 870         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 871         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 872         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 873         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 874         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 875         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 876         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 877         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 878         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 879         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 880         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 881         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 882         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 883         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 884         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 885         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 886         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 887         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 888         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 889         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 890         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 891         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 892         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 893         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 894         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 895         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 896         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 897         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 898         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 899         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 900         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 901         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 902         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 903         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 904         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 905         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 906         VEX_W_0F99_P_2_LEN_0): Delete.
 907         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 908         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 909         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 910         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 911         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 912         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 913         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 914         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 915         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 916         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 917         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 918         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 919         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 920         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 921         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 922         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 923         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 924         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 925         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 926         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 927         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 928         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 929         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 930         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 931         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 932         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 933         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 934         (prefix_table): No longer link to vex_len_table[] for opcodes
 935         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 936         0F92, 0F93, 0F98, and 0F99.
 937         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 938         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 939         0F98, and 0F99.
 940         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 941         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 942         0F98, and 0F99.
 943         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 944         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 945         0F98, and 0F99.
 946         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 947         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 948         0F98, and 0F99.
 949
 950 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 951
 952         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 953         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 954         REG_VEX_0F73_M_0 respectively.
 955         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 956         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 957         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 958         MOD_VEX_0F73_REG_7): Delete.
 959         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 960         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 961         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 962         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 963         PREFIX_VEX_0F3AF0_L_0 respectively.
 964         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 965         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 966         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 967         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 968         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 969         VEX_LEN_0F38F7): New.
 970         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 971         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 972         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 973         0F38F3.
 974         (prefix_table): No longer link to vex_len_table[] for opcodes
 975         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 976         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 977         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 978         0F38F6, 0F38F7, and 0F3AF0.
 979         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 980         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 981         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 982         0F73.
 983
 984 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 985
 986         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 987         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 988         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 989         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 990         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 991         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 992         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 993         73.
 994         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 995         0F72, and 0F73.
 996         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 997         0F73.
 998
 999 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1000
1001         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
1002         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
1003         (reg_table): Don't link to mod_table[] where not needed. Add
1004         PREFIX_IGNORED to nop entries.
1005         (prefix_table): Replace PREFIX_OPCODE in nop entries.
1006         (mod_table): Add nop entries next to prefetch ones. Drop
1007         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
1008         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
1009         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
1010         PREFIX_OPCODE from endbr* entries.
1011         (get_valid_dis386): Also consider entry's name when zapping
1012         vindex.
1013         (print_insn): Handle PREFIX_IGNORED.
1014
1015 2021-03-09  Jan Beulich  <jbeulich@suse.com>
1016
1017         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
1018         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
1019         element.
1020         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
1021         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
1022         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
1023         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
1024         (struct i386_opcode_modifier): Delete notrackprefixok,
1025         islockable, hleprefixok, and repprefixok fields. Add prefixok
1026         field.
1027         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
1028         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
1029         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
1030         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
1031         Replace HLEPrefixOk.
1032         * opcodes/i386-tbl.h: Re-generate.
1033
1034 2021-03-09  Jan Beulich  <jbeulich@suse.com>
1035
1036         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
1037         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
1038         64-bit form.
1039         * opcodes/i386-tbl.h: Re-generate.
1040
1041 2021-03-03  Jan Beulich  <jbeulich@suse.com>
1042
1043         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
1044         for {} instead of {0}. Don't look for '0'.
1045         * i386-opc.tbl: Drop operand count field. Drop redundant operand
1046         size specifiers.
1047
1048 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
1049
1050         PR 27158
1051         * riscv-dis.c (print_insn_args): Updated encoding macros.
1052         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
1053         (match_c_addi16sp): Updated encoding macros.
1054         (match_c_lui): Likewise.
1055         (match_c_lui_with_hint): Likewise.
1056         (match_c_addi4spn): Likewise.
1057         (match_c_slli): Likewise.
1058         (match_slli_as_c_slli): Likewise.
1059         (match_c_slli64): Likewise.
1060         (match_srxi_as_c_srxi): Likewise.
1061         (riscv_insn_types): Added .insn css/cl/cs.
1062
1063 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
1064
1065         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1066         (default_priv_spec): Updated type to riscv_spec_class.
1067         (parse_riscv_dis_option): Updated.
1068         * riscv-opc.c: Moved stuff and make the file tidy.
1069
1070 2021-02-17  Alan Modra  <amodra@gmail.com>
1071
1072         * wasm32-dis.c: Include limits.h.
1073         (CHAR_BIT): Provide backup define.
1074         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1075         Correct signed overflow checking.
1076
1077 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1078
1079         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1080         * i386-tbl.h: Re-generate.
1081
1082 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1083
1084         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1085         Oword.
1086         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1087
1088 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
1089
1090         * s390-mkopc.c (main): Accept arch14 as cpu string.
1091         * s390-opc.txt: Add new arch14 instructions.
1092
1093 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
1094
1095         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1096         favour of LIBINTL.
1097         * configure: Regenerated.
1098
1099 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
1100
1101         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1102         * tic54x-opc.c (regs): Rename to ...
1103         (tic54x_regs): ... this.
1104         (mmregs): Rename to ...
1105         (tic54x_mmregs): ... this.
1106         (condition_codes): Rename to ...
1107         (tic54x_condition_codes): ... this.
1108         (cc2_codes): Rename to ...
1109         (tic54x_cc2_codes): ... this.
1110         (cc3_codes): Rename to ...
1111         (tic54x_cc3_codes): ... this.
1112         (status_bits): Rename to ...
1113         (tic54x_status_bits): ... this.
1114         (misc_symbols): Rename to ...
1115         (tic54x_misc_symbols): ... this.
1116
1117 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
1118
1119         * riscv-opc.c (MASK_RVB_IMM): Removed.
1120         (riscv_opcodes): Removed zb* instructions.
1121         (riscv_ext_version_table): Removed versions for zb*.
1122
1123 2021-01-26  Alan Modra  <amodra@gmail.com>
1124
1125         * i386-gen.c (parse_template): Ensure entire template_instance
1126         is initialised.
1127
1128 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1129
1130         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1131         (riscv_fpr_names_abi): Likewise.
1132         (riscv_opcodes): Likewise.
1133         (riscv_insn_types): Likewise.
1134
1135 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1136
1137         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1138
1139 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1140
1141         * riscv-dis.c: Comments tidy and improvement.
1142         * riscv-opc.c: Likewise.
1143
1144 2021-01-13  Alan Modra  <amodra@gmail.com>
1145
1146         * Makefile.in: Regenerate.
1147
1148 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
1149
1150         PR binutils/26792
1151         * configure.ac: Use GNU_MAKE_JOBSERVER.
1152         * aclocal.m4: Regenerated.
1153         * configure: Likewise.
1154
1155 2021-01-12  Nick Clifton  <nickc@redhat.com>
1156
1157         * po/sr.po: Updated Serbian translation.
1158
1159 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
1160
1161         PR ld/27173
1162         * configure: Regenerated.
1163
1164 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1165
1166         * aarch64-asm-2.c: Regenerate.
1167         * aarch64-dis-2.c: Likewise.
1168         * aarch64-opc-2.c: Likewise.
1169         * aarch64-opc.c (aarch64_print_operand):
1170         Delete handling of AARCH64_OPND_CSRE_CSR.
1171         * aarch64-tbl.h (aarch64_feature_csre): Delete.
1172         (CSRE): Likewise.
1173         (_CSRE_INSN): Likewise.
1174         (aarch64_opcode_table): Delete csr.
1175
1176 2021-01-11  Nick Clifton  <nickc@redhat.com>
1177
1178         * po/de.po: Updated German translation.
1179         * po/fr.po: Updated French translation.
1180         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1181         * po/sv.po: Updated Swedish translation.
1182         * po/uk.po: Updated Ukranian translation.
1183
1184 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
1185
1186         * configure: Regenerated.
1187
1188 2021-01-09  Nick Clifton  <nickc@redhat.com>
1189
1190         * configure: Regenerate.
1191         * po/opcodes.pot: Regenerate.
1192
1193 2021-01-09  Nick Clifton  <nickc@redhat.com>
1194
1195         * 2.36 release branch crated.
1196
1197 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
1198
1199         * ppc-opc.c (insert_dw, (extract_dw): New functions.
1200         (DW, (XRC_MASK): Define.
1201         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1202
1203 2021-01-09  Alan Modra  <amodra@gmail.com>
1204
1205         * configure: Regenerate.
1206
1207 2021-01-08  Nick Clifton  <nickc@redhat.com>
1208
1209         * po/sv.po: Updated Swedish translation.
1210
1211 2021-01-08  Nick Clifton  <nickc@redhat.com>
1212
1213         PR 27129
1214         * aarch64-dis.c (determine_disassembling_preference): Move call to
1215         aarch64_match_operands_constraint outside of the assertion.
1216         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1217         Replace with a return of FALSE.
1218
1219         PR 27139
1220         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1221         core system register.
1222
1223 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
1224
1225         * configure: Regenerate.
1226
1227 2021-01-07  Nick Clifton  <nickc@redhat.com>
1228
1229         * po/fr.po: Updated French translation.
1230
1231 2021-01-07  Fredrik Noring  <noring@nocrew.org>
1232
1233         * m68k-opc.c (chkl): Change minimum architecture requirement to
1234         m68020.
1235
1236 2021-01-07  Philipp Tomsich  <prt@gnu.org>
1237
1238         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1239
1240 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
1241             Jim Wilson  <jimw@sifive.com>
1242             Andrew Waterman  <andrew@sifive.com>
1243             Maxim Blinov  <maxim.blinov@embecosm.com>
1244             Kito Cheng  <kito.cheng@sifive.com>
1245             Nelson Chu  <nelson.chu@sifive.com>
1246
1247         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1248         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1249
1250 2021-01-01  Alan Modra  <amodra@gmail.com>
1251
1252         Update year range in copyright notice of all files.
1253
1254 For older changes see ChangeLog-2020
1255 \f
1256 Copyright (C) 2021-2022 Free Software Foundation, Inc.
1257
1258 Copying and distribution of this file, with or without modification,
1259 are permitted in any medium without royalty provided the copyright
1260 notice and this notice are preserved.
1261
1262 Local Variables:
1263 mode: change-log
1264 left-margin: 8
1265 fill-column: 74
1266 version-control: never
1267 End: