opcodes/ChangeLog

   1 2013-05-15  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
   2
   3         * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
   4         * i386-init.h: Regenerated.
   5
   6 2013-05-13  Yufeng Zhang  <yufeng.zhang@arm.com>
   7
   8         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
   9         * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
  10         check from [0, 255] to [-128, 255].
  11
  12 2013-05-09  Andrew Pinski  <apinski@cavium.com>
  13
  14         * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
  15         Add INSN_VIRT and INSN_VIRT64 to mips64r2.
  16         (parse_mips_dis_option): Handle the virt option.
  17         (print_insn_args): Handle "+J".
  18         (print_mips_disassembler_options): Print out message about virt64.
  19         * mips-opc.c (IVIRT): New define.
  20         (IVIRT64): New define.
  21         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
  22         tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
  23         Move rfe to the bottom as it conflicts with tlbgp.
  24
  25 2013-05-09  Alan Modra  <amodra@gmail.com>
  26
  27         * ppc-opc.c (extract_vlesi): Properly sign extend.
  28         (extract_vlensi): Likewise.  Comment reason for setting invalid.
  29
  30 2013-05-02  Nick Clifton  <nickc@redhat.com>
  31
  32         * msp430-dis.c: Add support for MSP430X instructions.
  33
  34 2013-04-24  Sandra Loosemore  <sandra@codesourcery.com>
  35
  36         * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
  37         to "eccinj".
  38
  39 2013-04-17  Wei-chen Wang  <cole945@gmail.com>
  40
  41         PR binutils/15369
  42         * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
  43         of CGEN_CPU_ENDIAN.
  44         (hash_insns_list): Likewise.
  45
  46 2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>
  47
  48         * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
  49         warning workaround.
  50
  51 2013-04-08  Jan Beulich <jbeulich@suse.com>
  52
  53         * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
  54         * i386-tbl.h: Re-generate.
  55
  56 2013-04-06  David S. Miller  <davem@davemloft.net>
  57
  58         * sparc-dis.c (compare_opcodes): When encountering multiple aliases
  59         of an opcode, prefer the one with F_PREFERRED set.
  60         * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
  61         lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
  62         ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
  63         mark existing mnenomics as aliases.  Add "cc" suffix to edge
  64         instructions generating condition codes, mark existing mnenomics
  65         as aliases.  Add "fp" prefix to VIS compare instructions, mark
  66         existing mnenomics as aliases.
  67
  68 2013-04-03  Nick Clifton  <nickc@redhat.com>
  69
  70         * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
  71         destination address by subtracting the operand from the current
  72         address.
  73         * v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
  74         a positive value in the insn.
  75         (extract_u16_loop): Do not negate the returned value.
  76         (D16_LOOP): Add V850_INVERSE_PCREL flag.
  77
  78         (ceilf.sw): Remove duplicate entry.
  79         (cvtf.hs): New entry.
  80         (cvtf.sh): Likewise.
  81         (fmaf.s): Likewise.
  82         (fmsf.s): Likewise.
  83         (fnmaf.s): Likewise.
  84         (fnmsf.s): Likewise.
  85         (maddf.s): Restrict to E3V5 architectures.
  86         (msubf.s): Likewise.
  87         (nmaddf.s): Likewise.
  88         (nmsubf.s): Likewise.
  89
  90 2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>
  91
  92         * i386-dis.c (get_sib): Add the sizeflag argument.  Properly
  93         check address mode.
  94         (print_insn): Pass sizeflag to get_sib.
  95
  96 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
  97
  98         PR binutils/15068
  99         * tic6x-dis.c: Add support for displaying 16-bit insns.
 100
 101 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 102
 103         PR gas/15095
 104         * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
 105         individual msb and lsb halves in src1 & src2 fields.  Discard the
 106         src1 (lsb) value and only use src2 (msb), discarding bit 0, to
 107         follow what Ti SDK does in that case as any value in the src1
 108         field yields the same output with SDK disassembler.
 109
 110 2013-03-12  Michael Eager <eager@eagercon.com>
 111
 112         * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
 113
 114 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 115
 116         * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
 117
 118 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 119
 120         * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
 121
 122 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 123
 124         * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
 125
 126 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 127
 128         * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
 129         (thumb32_opcodes): Likewise.
 130         (print_insn_thumb32): Handle 'S' control char.
 131
 132 2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
 133
 134         * lm32-desc.c: Regenerate.
 135
 136 2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 137
 138         * i386-reg.tbl (riz): Add RegRex64.
 139         * i386-tbl.h: Regenerated.
 140
 141 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 142
 143         * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
 144         (aarch64_feature_crc): New static.
 145         (CRC): New macro.
 146         (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
 147         crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
 148         * aarch64-asm-2.c: Re-generate.
 149         * aarch64-dis-2.c: Ditto.
 150         * aarch64-opc-2.c: Ditto.
 151
 152 2013-02-27  Alan Modra  <amodra@gmail.com>
 153
 154         * rl78-decode.opc (rl78_decode_opcode): Fix typo.
 155         * rl78-decode.c: Regenerate.
 156
 157 2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
 158
 159         * rl78-decode.opc: Fix encoding of DIVWU insn.
 160         * rl78-decode.c: Regenerate.
 161
 162 2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 163
 164         PR gas/15159
 165         * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
 166
 167         * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
 168         (cpu_flags): Add CpuSMAP.
 169
 170         * i386-opc.h (CpuSMAP): New.
 171         (i386_cpu_flags): Add cpusmap.
 172
 173         * i386-opc.tbl: Add clac and stac.
 174
 175         * i386-init.h: Regenerated.
 176         * i386-tbl.h: Likewise.
 177
 178 2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
 179
 180         * metag-dis.c: Initialize outf->bytes_per_chunk to 4
 181         which also makes the disassembler output be in little
 182         endian like it should be.
 183
 184 2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
 185
 186         * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
 187         fields to NULL.
 188         (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
 189
 190 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
 191
 192         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
 193         section disassembled.
 194
 195 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 196
 197         * arm-dis.c: Update strht pattern.
 198
 199 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
 200
 201         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
 202         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
 203         trunc.w.s macro for EE.
 204
 205 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
 206             Andrew Jenner <andrew@codesourcery.com>
 207
 208         Based on patches from Altera Corporation.
 209
 210         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
 211         nios2-opc.c.
 212         * Makefile.in: Regenerated.
 213         * configure.in: Add case for bfd_nios2_arch.
 214         * configure: Regenerated.
 215         * disassemble.c (ARCH_nios2): Define.
 216         (disassembler): Add case for bfd_arch_nios2.
 217         * nios2-dis.c: New file.
 218         * nios2-opc.c: New file.
 219
 220 2013-02-04  Alan Modra  <amodra@gmail.com>
 221
 222         * po/POTFILES.in: Regenerate.
 223         * rl78-decode.c: Regenerate.
 224         * rx-decode.c: Regenerate.
 225
 226 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
 227
 228         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
 229         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
 230         * aarch64-asm.c (convert_xtl_to_shll): New function.
 231         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 232         calling convert_xtl_to_shll.
 233         * aarch64-dis.c (convert_shll_to_xtl): New function.
 234         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 235         calling convert_shll_to_xtl.
 236         * aarch64-gen.c: Update copyright year.
 237         * aarch64-asm-2.c: Re-generate.
 238         * aarch64-dis-2.c: Re-generate.
 239         * aarch64-opc-2.c: Re-generate.
 240
 241 2013-01-24  Nick Clifton  <nickc@redhat.com>
 242
 243         * v850-dis.c: Add support for e3v5 architecture.
 244         * v850-opc.c: Likewise.
 245
 246 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 247
 248         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
 249         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
 250         * aarch64-opc.c (operand_general_constraint_met_p): For
 251         AARCH64_MOD_LSL, move the range check on the shift amount before the
 252         alignment check; change to call set_sft_amount_out_of_range_error
 253         instead of set_imm_out_of_range_error.
 254         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
 255         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
 256         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
 257         SIMD_IMM_SFT.
 258
 259 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
 260
 261         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
 262
 263         * i386-init.h: Regenerated.
 264         * i386-tbl.h: Likewise.
 265
 266 2013-01-15  Nick Clifton  <nickc@redhat.com>
 267
 268         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
 269         values.
 270         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
 271
 272 2013-01-14  Will Newton <will.newton@imgtec.com>
 273
 274         * metag-dis.c (REG_WIDTH): Increase to 64.
 275
 276 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
 277
 278         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
 279         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
 280         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
 281         (SH6): Update.
 282         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
 283         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
 284         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
 285         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
 286
 287 2013-01-10  Will Newton <will.newton@imgtec.com>
 288
 289         * Makefile.am: Add Meta.
 290         * configure.in: Add Meta.
 291         * disassemble.c: Add Meta support.
 292         * metag-dis.c: New file.
 293         * Makefile.in: Regenerate.
 294         * configure: Regenerate.
 295
 296 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 297
 298         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
 299         (match_opcode): Rename to cr16_match_opcode.
 300
 301 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
 302
 303         * mips-dis.c: Add names for CP0 registers of r5900.
 304         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
 305         instructions sq and lq.
 306         Add support for MIPS r5900 CPU.
 307         Add support for 128 bit MMI (Multimedia Instructions).
 308         Add support for EE instructions (Emotion Engine).
 309         Disable unsupported floating point instructions (64 bit and
 310         undefined compare operations).
 311         Enable instructions of MIPS ISA IV which are supported by r5900.
 312         Disable 64 bit co processor instructions.
 313         Disable 64 bit multiplication and division instructions.
 314         Disable instructions for co-processor 2 and 3, because these are
 315         not supported (preparation for later VU0 support (Vector Unit)).
 316         Disable cvt.w.s because this behaves like trunc.w.s and the
 317         correct execution can't be ensured on r5900.
 318         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
 319         will confuse less developers and compilers.
 320
 321 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 322
 323         * aarch64-opc.c (aarch64_print_operand): Change to print
 324         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
 325         in comment.
 326         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
 327         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
 328         OP_MOV_IMM_WIDE.
 329
 330 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 331
 332         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
 333         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
 334
 335 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
 336
 337         * i386-gen.c (process_copyright): Update copyright year to 2013.
 338
 339 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 340
 341         * cr16-dis.c (match_opcode,make_instruction): Remove static
 342         declaration.
 343         (dwordU,wordU): Moved typedefs to opcode/cr16.h
 344         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
 345
 346 For older changes see ChangeLog-2012
 347 \f
 348 Copyright (C) 2013 Free Software Foundation, Inc.
 349
 350 Copying and distribution of this file, with or without modification,
 351 are permitted in any medium without royalty provided the copyright
 352 notice and this notice are preserved.
 353
 354 Local Variables:
 355 mode: change-log
 356 left-margin: 8
 357 fill-column: 74
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 359 End: