opcodes/ChangeLog

   1 2021-09-20  Andrew Burgess  <andrew.burgess@embecosm.com>
   2
   3         * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
   4         before an unknown instruction, '%d' is replaced with the
   5         instruction length.
   6
   7 2021-09-02  Nick Clifton  <nickc@redhat.com>
   8
   9         PR 28292
  10         * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
  11         of BFD_RELOC_16.
  12
  13 2021-08-17  Shahab Vahedi <shahab@synopsys.com>
  14
  15         * arc-regs.h (DEF): Fix the register numbers.
  16
  17 2021-08-10  Nick Clifton  <nickc@redhat.com>
  18
  19         * po/sr.po: Updated Serbian translation.
  20
  21 2021-07-26  Chenghua Xu  <xuchenghua@loongson.cn>
  22
  23         * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
  24
  25 2021-06-07  Andreas Krebbel  <krebbel@linux.ibm.com>
  26
  27         * s390-opc.txt: Add qpaci.
  28
  29 2021-07-03  Nick Clifton  <nickc@redhat.com>
  30
  31         * configure: Regenerate.
  32         * po/opcodes.pot: Regenerate.
  33
  34 2021-07-03  Nick Clifton  <nickc@redhat.com>
  35
  36         * 2.37 release branch created.
  37
  38 2021-07-02  Alan Modra  <amodra@gmail.com>
  39
  40         * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
  41         (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
  42         (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
  43         (nds32_opcodes, nds32_operand_fields, nds32_keywords),
  44         (nds32_keyword_gpr): Move declarations to..
  45         * nds32-asm.h: ..here, constifying to match definitions.
  46
  47 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  48
  49         * Makefile.am (GUILE): New variable.
  50         (CGEN): Use $(GUILE).
  51         * Makefile.in: Regenerate.
  52
  53 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  54
  55         * mep-asm.c (macros): Mark static & const.
  56         (lookup_macro): Change return & m to const.
  57         (expand_macro): Change mac to const.
  58         (expand_string): Change pmacro to const.
  59
  60 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  61
  62         * nds32-asm.c (operand_fields): Rename to ...
  63         (nds32_operand_fields): ... this.
  64         (keyword_gpr): Rename to ...
  65         (nds32_keyword_gpr): ... this.
  66         (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
  67         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
  68         keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
  69         keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
  70         keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
  71         Mark static.
  72         (keywords): Rename to ...
  73         (nds32_keywords): ... this.
  74         * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
  75         keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
  76
  77 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  78
  79         * z80-dis.c (opc_ed): Make const.
  80         (pref_ed): Make p const.
  81
  82 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  83
  84         * microblaze-dis.c (get_field_special): Make op const.
  85         (read_insn_microblaze): Make opr & op const.  Rename opcodes to
  86         microblaze_opcodes.
  87         (print_insn_microblaze): Make op & pop const.
  88         (get_insn_microblaze): Make op const.  Rename opcodes to
  89         microblaze_opcodes.
  90         (microblaze_get_target_address): Likewise.
  91         * microblaze-opc.h (struct op_code_struct): Make const.
  92         Rename opcodes to microblaze_opcodes.
  93
  94 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  95
  96         * aarch64-gen.c (aarch64_opcode_table): Add const.
  97         * aarch64-tbl.h (aarch64_opcode_table): Likewise.
  98
  99 2021-06-22  Andrew Burgess  <andrew.burgess@embecosm.com>
 100
 101         * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
 102         available.
 103
 104 2021-06-22  Alan Modra  <amodra@gmail.com>
 105
 106         * pj-dis.c (print_insn_pj): Don't print trailing tab.  Do
 107         print separator for pcrel insns.
 108
 109 2021-06-19  Alan Modra  <amodra@gmail.com>
 110
 111         * vax-dis.c (print_insn_vax): Avoid pointer overflow.
 112
 113 2021-06-19  Alan Modra  <amodra@gmail.com>
 114
 115         * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
 116         entire buffer.
 117
 118 2021-06-17  Alan Modra  <amodra@gmail.com>
 119
 120         * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
 121         in table.
 122
 123 2021-06-03  Alan Modra  <amodra@gmail.com>
 124
 125         PR 1202
 126         * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
 127         Use unsigned int for inst.
 128
 129 2021-06-02  Shahab Vahedi  <shahab@synopsys.com>
 130
 131         * arc-dis.c (arc_option_arg_t): New enumeration.
 132         (arc_options): New variable.
 133         (disassembler_options_arc): New function.
 134         (print_arc_disassembler_options): Reimplement in terms of
 135         "disassembler_options_arc".
 136
 137 2021-05-29  Alan Modra  <amodra@gmail.com>
 138
 139         * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
 140         Don't special case PPC_OPCODE_RAW.
 141         (lookup_prefix): Likewise.
 142         (lookup_vle, lookup_spe2): Similarly.  Add dialect parameter and..
 143         (print_insn_powerpc): ..update caller.
 144         * ppc-opc.c (EXT): Define.
 145         (powerpc_opcodes): Mark extended mnemonics with EXT.
 146         (prefix_opcodes, vle_opcodes): Likewise.
 147         (XISEL, XISEL_MASK): Add cr field and simplify.
 148         (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
 149         all isel variants to where the base mnemonic belongs.  Sort dstt,
 150         dststt and dssall.
 151
 152 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 153
 154         * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
 155         COP3 opcode instructions.
 156
 157 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 158
 159         * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
 160         "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
 161         "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
 162         "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
 163         "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
 164         "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
 165         "cop2", and "cop3" entries.
 166
 167 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 168
 169         * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
 170         entries and associated comments.
 171
 172 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 173
 174         * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
 175         of "c0".
 176
 177 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 178
 179         * mips-dis.c (mips_cp1_names_mips): New variable.
 180         (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
 181         for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
 182         "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
 183         "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
 184         "r12000", "r14000", "r16000", "mips5", "loongson2e", and
 185         "loongson2f".
 186
 187 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 188
 189         * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
 190         handling code over to...
 191         <OP_REG_CONTROL>: ... this new case.
 192         * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
 193         (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
 194         "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
 195         replacing the `G' operand code with `g'.  Update "cftc1" and
 196         "cftc2" entries replacing the `E' operand code with `y'.
 197         * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
 198         (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
 199         entries replacing the `G' operand code with `g'.
 200
 201 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 202
 203         * mips-dis.c (mips_cp0_names_r3900): New variable.
 204         (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
 205         for "r3900".
 206
 207 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 208
 209         * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
 210         and "mtthc2" to using the `G' rather than `g' operand code for
 211         the coprocessor control register referred.
 212
 213 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 214
 215         * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
 216         entries with each other.
 217
 218 2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
 219
 220         * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
 221
 222 2021-05-25  Alan Modra  <amodra@gmail.com>
 223
 224         * cris-desc.c: Regenerate.
 225         * cris-desc.h: Regenerate.
 226         * cris-opc.h: Regenerate.
 227         * po/POTFILES.in: Regenerate.
 228
 229 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
 230
 231         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
 232         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
 233         (CGEN_CPUS): Add cris.
 234         (CRIS_DEPS): Define.
 235         (stamp-cris): New rule.
 236         * cgen.sh: Handle desc action.
 237         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
 238         * Makefile.in, configure: Regenerate.
 239
 240 2021-05-18  Job Noorman  <mtvec@pm.me>
 241
 242         PR 27814
 243         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
 244         the elf objects.
 245
 246 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
 247
 248         * arm-dis.c (mve_opcodes): Fix disassembly of
 249         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
 250         (is_mve_encoding_conflict): MVE vector loads should not match
 251         when P = W = 0.
 252         (is_mve_unpredictable): It's not unpredictable to use the same
 253         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
 254
 255 2021-05-11  Nick Clifton  <nickc@redhat.com>
 256
 257         PR 27840
 258         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
 259         the end of the code buffer.
 260
 261 2021-05-06  Stafford Horne  <shorne@gmail.com>
 262
 263         PR 21464
 264         * or1k-asm.c: Regenerate.
 265
 266 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
 267
 268         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
 269         info->insn_info_valid.
 270
 271 2021-04-26  Jan Beulich  <jbeulich@suse.com>
 272
 273         * i386-opc.tbl (lea): Add Optimize.
 274         * opcodes/i386-tbl.h: Re-generate.
 275
 276 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 277
 278         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
 279         of l32r fetch and display referenced literal value.
 280
 281 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 282
 283         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
 284         to 4 for literal disassembly.
 285
 286 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 287
 288         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
 289         for TLBI instruction.
 290
 291 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 292
 293         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
 294         DC instruction.
 295
 296 2021-04-19  Jan Beulich  <jbeulich@suse.com>
 297
 298         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
 299         "qualifier".
 300         (convert_mov_to_movewide): Add initializer for "value".
 301
 302 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 303
 304         * aarch64-opc.c: Add RME system registers.
 305
 306 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
 307
 308         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
 309         "addi d,CV,z" to "c.mv d,CV".
 310
 311 2021-04-12  Alan Modra  <amodra@gmail.com>
 312
 313         * configure.ac (--enable-checking): Add support.
 314         * config.in: Regenerate.
 315         * configure: Regenerate.
 316
 317 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
 318
 319         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
 320         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 321
 322 2021-04-09  Alan Modra  <amodra@gmail.com>
 323
 324         * ppc-dis.c (struct dis_private): Add "special".
 325         (POWERPC_DIALECT): Delete.  Replace uses with..
 326         (private_data): ..this.  New inline function.
 327         (disassemble_init_powerpc): Init "special" names.
 328         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 329         field of prefix instructions.
 330         (bsearch_reloc, print_got_plt): New functions.
 331         (print_insn_powerpc): For pcrel instructions, print target address
 332         and symbol if known, and decode plt and got loads too.
 333
 334 2021-04-08  Alan Modra  <amodra@gmail.com>
 335
 336         PR 27684
 337         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 338
 339 2021-04-08  Alan Modra  <amodra@gmail.com>
 340
 341         PR 27676
 342         * ppc-opc.c (DCBT_EO): Move earlier.
 343         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 344         (powerpc_operands): Add THCT and THDS entries.
 345         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 346
 347 2021-04-06  Alan Modra  <amodra@gmail.com>
 348
 349         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 350         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 351         symbol_at_address_func.
 352
 353 2021-04-05  Alan Modra  <amodra@gmail.com>
 354
 355         * configure.ac: Don't check for limits.h, string.h, strings.h or
 356         stdlib.h.
 357         (AC_ISC_POSIX): Don't invoke.
 358         * sysdep.h: Include stdlib.h and string.h unconditionally.
 359         * i386-opc.h: Include limits.h unconditionally.
 360         * wasm32-dis.c: Likewise.
 361         * cgen-opc.c: Don't include alloca-conf.h.
 362         * config.in: Regenerate.
 363         * configure: Regenerate.
 364
 365 2021-04-01  Martin Liska  <mliska@suse.cz>
 366
 367         * arm-dis.c (strneq): Remove strneq and use startswith.
 368         * cr16-dis.c (print_insn_cr16): Likewise.
 369         * score-dis.c (streq): Likewise.
 370         (strneq): Likewise.
 371         * score7-dis.c (strneq): Likewise.
 372
 373 2021-04-01  Alan Modra  <amodra@gmail.com>
 374
 375         PR 27675
 376         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 377
 378 2021-03-31  Alan Modra  <amodra@gmail.com>
 379
 380         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 381         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 382         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 383         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 384         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 385         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 386         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 387         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 388         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 389         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 390         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 391         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 392         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 393         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 394         and TRUE with true throughout.
 395
 396 2021-03-31  Alan Modra  <amodra@gmail.com>
 397
 398         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 399         * aarch64-dis.h: Likewise.
 400         * aarch64-opc.c: Likewise.
 401         * avr-dis.c: Likewise.
 402         * csky-dis.c: Likewise.
 403         * nds32-asm.c: Likewise.
 404         * nds32-dis.c: Likewise.
 405         * nfp-dis.c: Likewise.
 406         * riscv-dis.c: Likewise.
 407         * s12z-dis.c: Likewise.
 408         * wasm32-dis.c: Likewise.
 409
 410 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 411
 412         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 413         (i386_seg_prefixes): New.
 414         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 415         (i386_seg_prefixes): Declare.
 416
 417 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 418
 419         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 420
 421 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 422
 423         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 424         * i386-reg.tbl (st): Move down.
 425         (st(0)): Delete. Extend comment.
 426         * i386-tbl.h: Re-generate.
 427
 428 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 429
 430         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 431         (cmpsd): Move next to cmps.
 432         (movsd): Move next to movs.
 433         (cmpxchg16b): Move to separate section.
 434         (fisttp, fisttpll): Likewise.
 435         (monitor, mwait): Likewise.
 436         * i386-tbl.h: Re-generate.
 437
 438 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 439
 440         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 441         (vpsadbw): Add C.
 442         * i386-tbl.h: Re-generate.
 443
 444 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 445
 446         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 447         pclmul, gfni): New templates. Use them wherever possible. Move
 448         SSE4.1 pextrw into respective section.
 449         * i386-tbl.h: Re-generate.
 450
 451 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 452
 453         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 454         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 455         "length".
 456         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 457         Convert all of their uses to representation in opcode.
 458
 459 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 460
 461         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 462         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 463         value of None. Shrink operands to 3 bits.
 464
 465 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 466
 467         * i386-gen.c (process_i386_opcode_modifier): New parameter
 468         "space".
 469         (output_i386_opcode): New local variable "space". Adjust
 470         process_i386_opcode_modifier() invocation.
 471         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 472         invocation.
 473         * i386-tbl.h: Re-generate.
 474
 475 2021-03-29  Alan Modra  <amodra@gmail.com>
 476
 477         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 478         (fp_qualifier_p, get_data_pattern): Likewise.
 479         (aarch64_get_operand_modifier_from_value): Likewise.
 480         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 481         (operand_variant_qualifier_p): Likewise.
 482         (qualifier_value_in_range_constraint_p): Likewise.
 483         (aarch64_get_qualifier_esize): Likewise.
 484         (aarch64_get_qualifier_nelem): Likewise.
 485         (aarch64_get_qualifier_standard_value): Likewise.
 486         (get_lower_bound, get_upper_bound): Likewise.
 487         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 488         (aarch64_print_operand): Likewise.
 489         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 490         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 491         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 492         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 493         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 494         (print_insn_tic6x): Likewise.
 495
 496 2021-03-29  Alan Modra  <amodra@gmail.com>
 497
 498         * arc-dis.c (extract_operand_value): Correct NULL cast.
 499         * frv-opc.h: Regenerate.
 500
 501 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 502
 503         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 504         MMX form.
 505         * i386-tbl.h: Re-generate.
 506
 507 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 508
 509         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 510         immediate in br.n instruction.
 511
 512 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 513
 514         * i386-dis.c (XMGatherD, VexGatherD): New.
 515         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 516         (print_insn): Check masking for S/G insns.
 517         (OP_E_memory): New local variable check_gather. Extend mandatory
 518         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 519         Extend check for disallowed 16-bit addressing.
 520         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 521         if()s to switch(). Check register conflicts for (VEX-encoded)
 522         gathers. Drop no longer reachable cases.
 523         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 524         vgatherdp*.
 525
 526 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 527
 528         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 529         zeroing-masking without masking.
 530
 531 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 532
 533         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 534         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 535         single-operand forms as deprecated.
 536         * i386-tbl.h: Re-generate.
 537
 538 2021-03-25  Alan Modra  <amodra@gmail.com>
 539
 540         PR 27647
 541         * ppc-opc.c (XLOCB_MASK): Delete.
 542         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 543         XLBH_MASK.
 544         (powerpc_opcodes): Accept a BH field on all extended forms of
 545         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 546
 547 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 548
 549         * i386-gen.c (output_i386_opcode): Drop processing of
 550         opcode_length. Calculate length from base_opcode. Adjust prefix
 551         encoding determination.
 552         (process_i386_opcodes): Drop output of fake opcode_length.
 553         * i386-opc.h (struct insn_template): Drop opcode_length field.
 554         * i386-opc.tbl: Drop opcode length field from all templates.
 555         * i386-tbl.h: Re-generate.
 556
 557 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 558
 559         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 560         parameter "prefix". Drop local variable "regular_encoding".
 561         Record prefix setting / check for consistency.
 562         (output_i386_opcode): Parse opcode_length and base_opcode
 563         earlier. Derive prefix encoding. Drop no longer applicable
 564         consistency checking. Adjust process_i386_opcode_modifier()
 565         invocation.
 566         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 567         invocation.
 568         * i386-tbl.h: Re-generate.
 569
 570 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 571
 572         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 573         check.
 574         * i386-opc.h (Prefix_*): Move #define-s.
 575         * i386-opc.tbl: Move pseudo prefix enumerator values to
 576         extension opcode field. Introduce pseudopfx template.
 577         * i386-tbl.h: Re-generate.
 578
 579 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 580
 581         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 582         comment.
 583         * i386-tbl.h: Re-generate.
 584
 585 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 586
 587         * i386-opc.h (struct insn_template): Move cpu_flags field past
 588         opcode_modifier one.
 589         * i386-tbl.h: Re-generate.
 590
 591 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 592
 593         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 594         * i386-opc.h (OpcodeSpace): New enumerator.
 595         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 596         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 597         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 598         (struct i386_opcode_modifier): New field opcodespace. Shrink
 599         opcodeprefix field.
 600         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 601         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 602         OpcodePrefix uses.
 603         * i386-tbl.h: Re-generate.
 604
 605 2021-03-22  Martin Liska  <mliska@suse.cz>
 606
 607         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 608         * arc-dis.c (parse_option): Likewise.
 609         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 610         * cris-dis.c (print_with_operands): Likewise.
 611         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 612         * i386-dis.c (print_insn): Likewise.
 613         * ia64-gen.c (fetch_insn_class): Likewise.
 614         (parse_resource_users): Likewise.
 615         (in_iclass): Likewise.
 616         (lookup_specifier): Likewise.
 617         (insert_opcode_dependencies): Likewise.
 618         * mips-dis.c (parse_mips_ase_option): Likewise.
 619         (parse_mips_dis_option): Likewise.
 620         * s390-dis.c (disassemble_init_s390): Likewise.
 621         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 622
 623 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 624
 625         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 626
 627 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 628
 629         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 630         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 631
 632 2021-03-12  Alan Modra  <amodra@gmail.com>
 633
 634         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 635
 636 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 637
 638         * i386-dis.c (OP_XMM): Re-order checks.
 639
 640 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 641
 642         * i386-dis.c (putop): Drop need_vex check when also checking
 643         vex.evex.
 644         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 645         checking vex.b.
 646
 647 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 648
 649         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 650         checks. Move case label past broadcast check.
 651
 652 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 653
 654         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 655         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 656         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 657         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 658         EVEX_W_0F38C7_M_0_L_2): Delete.
 659         (REG_EVEX_0F38C7_M_0_L_2): New.
 660         (intel_operand_size): Handle VEX and EVEX the same for
 661         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 662         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 663         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 664         vex_vsib_q_w_d_mode uses.
 665         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 666         0F38A1, and 0F38A3 entries.
 667         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 668         entry.
 669         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 670         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 671         0F38A3 entries.
 672
 673 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 674
 675         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 676         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 677         MOD_VEX_0FXOP_09_12): Rename to ...
 678         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 679         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 680         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 681         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 682         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 683         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 684         (reg_table): Adjust comments.
 685         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 686         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 687         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 688         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 689         (vex_len_table): Adjust opcode 0A_12 entry.
 690         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 691         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 692         (rm_table): Move hreset entry.
 693
 694 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 695
 696         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 697         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 698         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 699         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 700         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 701         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 702         (get_valid_dis386): Also handle 512-bit vector length when
 703         vectoring into vex_len_table[].
 704         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 705         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 706         entries.
 707         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 708         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 709         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 710         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 711         entries.
 712
 713 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 714
 715         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 716         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 717         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 718         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 719         entries.
 720         * i386-dis-evex-len.h (evex_len_table): Likewise.
 721         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 722
 723 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 724
 725         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 726         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 727         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 728         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 729         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 730         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 731         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 732         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 733         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 734         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 735         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 736         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 737         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 738         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 739         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 740         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 741         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 742         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 743         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 744         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 745         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 746         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 747         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 748         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 749         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 750         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 751         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 752         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 753         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 754         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 755         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 756         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 757         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 758         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 759         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 760         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 761         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 762         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 763         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 764         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 765         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 766         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 767         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 768         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 769         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 770         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 771         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 772         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 773         EVEX_W_0F3A43_L_n): New.
 774         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 775         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 776         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 777         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 778         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 779         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 780         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 781         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 782         0F385B, 0F38C6, and 0F38C7 entries.
 783         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 784         0F38C6 and 0F38C7.
 785         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 786         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 787         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 788         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 789
 790 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 791
 792         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 793         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 794         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 795         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 796         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 797         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 798         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 799         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 800         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 801         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 802         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 803         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 804         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 805         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 806         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 807         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 808         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 809         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 810         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 811         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 812         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 813         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 814         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 815         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 816         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 817         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 818         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 819         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 820         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 821         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 822         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 823         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 824         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 825         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 826         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 827         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 828         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 829         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 830         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 831         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 832         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 833         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 834         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 835         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 836         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 837         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 838         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 839         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 840         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 841         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 842         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 843         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 844         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 845         VEX_W_0F99_P_2_LEN_0): Delete.
 846         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 847         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 848         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 849         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 850         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 851         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 852         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 853         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 854         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 855         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 856         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 857         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 858         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 859         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 860         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 861         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 862         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 863         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 864         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 865         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 866         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 867         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 868         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 869         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 870         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 871         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 872         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 873         (prefix_table): No longer link to vex_len_table[] for opcodes
 874         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 875         0F92, 0F93, 0F98, and 0F99.
 876         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 877         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 878         0F98, and 0F99.
 879         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 880         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 881         0F98, and 0F99.
 882         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 883         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 884         0F98, and 0F99.
 885         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 886         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 887         0F98, and 0F99.
 888
 889 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 890
 891         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 892         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 893         REG_VEX_0F73_M_0 respectively.
 894         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 895         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 896         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 897         MOD_VEX_0F73_REG_7): Delete.
 898         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 899         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 900         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 901         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 902         PREFIX_VEX_0F3AF0_L_0 respectively.
 903         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 904         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 905         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 906         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 907         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 908         VEX_LEN_0F38F7): New.
 909         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 910         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 911         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 912         0F38F3.
 913         (prefix_table): No longer link to vex_len_table[] for opcodes
 914         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 915         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 916         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 917         0F38F6, 0F38F7, and 0F3AF0.
 918         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 919         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 920         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 921         0F73.
 922
 923 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 924
 925         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 926         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 927         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 928         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 929         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 930         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 931         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 932         73.
 933         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 934         0F72, and 0F73.
 935         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 936         0F73.
 937
 938 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 939
 940         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 941         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 942         (reg_table): Don't link to mod_table[] where not needed. Add
 943         PREFIX_IGNORED to nop entries.
 944         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 945         (mod_table): Add nop entries next to prefetch ones. Drop
 946         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 947         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 948         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 949         PREFIX_OPCODE from endbr* entries.
 950         (get_valid_dis386): Also consider entry's name when zapping
 951         vindex.
 952         (print_insn): Handle PREFIX_IGNORED.
 953
 954 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 955
 956         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 957         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 958         element.
 959         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 960         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 961         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 962         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 963         (struct i386_opcode_modifier): Delete notrackprefixok,
 964         islockable, hleprefixok, and repprefixok fields. Add prefixok
 965         field.
 966         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 967         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 968         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 969         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 970         Replace HLEPrefixOk.
 971         * opcodes/i386-tbl.h: Re-generate.
 972
 973 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 974
 975         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 976         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 977         64-bit form.
 978         * opcodes/i386-tbl.h: Re-generate.
 979
 980 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 981
 982         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 983         for {} instead of {0}. Don't look for '0'.
 984         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 985         size specifiers.
 986
 987 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 988
 989         PR 27158
 990         * riscv-dis.c (print_insn_args): Updated encoding macros.
 991         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 992         (match_c_addi16sp): Updated encoding macros.
 993         (match_c_lui): Likewise.
 994         (match_c_lui_with_hint): Likewise.
 995         (match_c_addi4spn): Likewise.
 996         (match_c_slli): Likewise.
 997         (match_slli_as_c_slli): Likewise.
 998         (match_c_slli64): Likewise.
 999         (match_srxi_as_c_srxi): Likewise.
1000         (riscv_insn_types): Added .insn css/cl/cs.
1001
1002 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
1003
1004         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1005         (default_priv_spec): Updated type to riscv_spec_class.
1006         (parse_riscv_dis_option): Updated.
1007         * riscv-opc.c: Moved stuff and make the file tidy.
1008
1009 2021-02-17  Alan Modra  <amodra@gmail.com>
1010
1011         * wasm32-dis.c: Include limits.h.
1012         (CHAR_BIT): Provide backup define.
1013         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1014         Correct signed overflow checking.
1015
1016 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1017
1018         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1019         * i386-tbl.h: Re-generate.
1020
1021 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1022
1023         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1024         Oword.
1025         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1026
1027 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
1028
1029         * s390-mkopc.c (main): Accept arch14 as cpu string.
1030         * s390-opc.txt: Add new arch14 instructions.
1031
1032 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
1033
1034         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1035         favour of LIBINTL.
1036         * configure: Regenerated.
1037
1038 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
1039
1040         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1041         * tic54x-opc.c (regs): Rename to ...
1042         (tic54x_regs): ... this.
1043         (mmregs): Rename to ...
1044         (tic54x_mmregs): ... this.
1045         (condition_codes): Rename to ...
1046         (tic54x_condition_codes): ... this.
1047         (cc2_codes): Rename to ...
1048         (tic54x_cc2_codes): ... this.
1049         (cc3_codes): Rename to ...
1050         (tic54x_cc3_codes): ... this.
1051         (status_bits): Rename to ...
1052         (tic54x_status_bits): ... this.
1053         (misc_symbols): Rename to ...
1054         (tic54x_misc_symbols): ... this.
1055
1056 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
1057
1058         * riscv-opc.c (MASK_RVB_IMM): Removed.
1059         (riscv_opcodes): Removed zb* instructions.
1060         (riscv_ext_version_table): Removed versions for zb*.
1061
1062 2021-01-26  Alan Modra  <amodra@gmail.com>
1063
1064         * i386-gen.c (parse_template): Ensure entire template_instance
1065         is initialised.
1066
1067 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1068
1069         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1070         (riscv_fpr_names_abi): Likewise.
1071         (riscv_opcodes): Likewise.
1072         (riscv_insn_types): Likewise.
1073
1074 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1075
1076         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1077
1078 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1079
1080         * riscv-dis.c: Comments tidy and improvement.
1081         * riscv-opc.c: Likewise.
1082
1083 2021-01-13  Alan Modra  <amodra@gmail.com>
1084
1085         * Makefile.in: Regenerate.
1086
1087 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
1088
1089         PR binutils/26792
1090         * configure.ac: Use GNU_MAKE_JOBSERVER.
1091         * aclocal.m4: Regenerated.
1092         * configure: Likewise.
1093
1094 2021-01-12  Nick Clifton  <nickc@redhat.com>
1095
1096         * po/sr.po: Updated Serbian translation.
1097
1098 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
1099
1100         PR ld/27173
1101         * configure: Regenerated.
1102
1103 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1104
1105         * aarch64-asm-2.c: Regenerate.
1106         * aarch64-dis-2.c: Likewise.
1107         * aarch64-opc-2.c: Likewise.
1108         * aarch64-opc.c (aarch64_print_operand):
1109         Delete handling of AARCH64_OPND_CSRE_CSR.
1110         * aarch64-tbl.h (aarch64_feature_csre): Delete.
1111         (CSRE): Likewise.
1112         (_CSRE_INSN): Likewise.
1113         (aarch64_opcode_table): Delete csr.
1114
1115 2021-01-11  Nick Clifton  <nickc@redhat.com>
1116
1117         * po/de.po: Updated German translation.
1118         * po/fr.po: Updated French translation.
1119         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1120         * po/sv.po: Updated Swedish translation.
1121         * po/uk.po: Updated Ukranian translation.
1122
1123 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
1124
1125         * configure: Regenerated.
1126
1127 2021-01-09  Nick Clifton  <nickc@redhat.com>
1128
1129         * configure: Regenerate.
1130         * po/opcodes.pot: Regenerate.
1131
1132 2021-01-09  Nick Clifton  <nickc@redhat.com>
1133
1134         * 2.36 release branch crated.
1135
1136 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
1137
1138         * ppc-opc.c (insert_dw, (extract_dw): New functions.
1139         (DW, (XRC_MASK): Define.
1140         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1141
1142 2021-01-09  Alan Modra  <amodra@gmail.com>
1143
1144         * configure: Regenerate.
1145
1146 2021-01-08  Nick Clifton  <nickc@redhat.com>
1147
1148         * po/sv.po: Updated Swedish translation.
1149
1150 2021-01-08  Nick Clifton  <nickc@redhat.com>
1151
1152         PR 27129
1153         * aarch64-dis.c (determine_disassembling_preference): Move call to
1154         aarch64_match_operands_constraint outside of the assertion.
1155         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1156         Replace with a return of FALSE.
1157
1158         PR 27139
1159         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1160         core system register.
1161
1162 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
1163
1164         * configure: Regenerate.
1165
1166 2021-01-07  Nick Clifton  <nickc@redhat.com>
1167
1168         * po/fr.po: Updated French translation.
1169
1170 2021-01-07  Fredrik Noring  <noring@nocrew.org>
1171
1172         * m68k-opc.c (chkl): Change minimum architecture requirement to
1173         m68020.
1174
1175 2021-01-07  Philipp Tomsich  <prt@gnu.org>
1176
1177         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1178
1179 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
1180             Jim Wilson  <jimw@sifive.com>
1181             Andrew Waterman  <andrew@sifive.com>
1182             Maxim Blinov  <maxim.blinov@embecosm.com>
1183             Kito Cheng  <kito.cheng@sifive.com>
1184             Nelson Chu  <nelson.chu@sifive.com>
1185
1186         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1187         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1188
1189 2021-01-01  Alan Modra  <amodra@gmail.com>
1190
1191         Update year range in copyright notice of all files.
1192
1193 For older changes see ChangeLog-2020
1194 \f
1195 Copyright (C) 2021 Free Software Foundation, Inc.
1196
1197 Copying and distribution of this file, with or without modification,
1198 are permitted in any medium without royalty provided the copyright
1199 notice and this notice are preserved.
1200
1201 Local Variables:
1202 mode: change-log
1203 left-margin: 8
1204 fill-column: 74
1205 version-control: never
1206 End: