opcodes/ChangeLog

   1 2015-09-22  Anton Blanchard  <anton@samba.org>
   2
   3         * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
   4
   5 2015-08-25  Jose E. Marchesi  <jose.marchesi@oracle.com>
   6
   7         * sparc-dis.c (print_insn_sparc): Handle the privileged register
   8         %pmcdper.
   9
  10 2015-08-24  Jan Stancek  <jstancek@redhat.com>
  11
  12         * i386-dis.c (print_insn): Fix decoding of three byte operands.
  13
  14 2015-08-21  Alexander Fomin  <alexander.fomin@intel.com>
  15
  16         PR binutils/18257
  17         * i386-dis.c: Use MOD_TABLE for most of mask instructions.
  18         (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
  19         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
  20         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
  21         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
  22         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
  23         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
  24         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
  25         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
  26         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
  27         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
  28         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
  29         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
  30         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
  31         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
  32         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
  33         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
  34         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
  35         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
  36         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
  37         MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
  38         MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
  39         MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
  40         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
  41         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
  42         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
  43         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
  44         MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
  45         MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
  46         MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
  47         MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
  48         (vex_w_table): Replace terminals with MOD_TABLE entries for
  49         most of mask instructions.
  50
  51 2015-08-17  Alan Modra  <amodra@gmail.com>
  52
  53         * cgen.sh: Trim trailing space from cgen output.
  54         * ia64-gen.c (print_dependency_table): Don't generate trailing space.
  55         (print_dis_table): Likewise.
  56         * opc2c.c (dump_lines): Likewise.
  57         (orig_filename): Warning fix.
  58         * ia64-asmtab.c: Regenerate.
  59
  60 2015-08-13  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  61
  62         * arm-dis.c (print_insn_arm): Disassembling for all targets V6
  63         and higher with ARM instruction set will now mark the 26-bit
  64         versions of teq,tst,cmn and cmp as UNPREDICTABLE.
  65         (arm_opcodes): Fix for unpredictable nop being recognized as a
  66         teq.
  67
  68 2015-08-12  Simon Dardis  <simon.dardis@imgtec.com>
  69
  70         * micromips-opc.c (micromips_opcodes): Re-order table so that move
  71         based on 'or' is first.
  72         * mips-opc.c (mips_builtin_opcodes): Ditto.
  73
  74 2015-08-11  Nick Clifton  <nickc@redhat.com>
  75
  76         PR 18800
  77         * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
  78         instruction.
  79
  80 2015-08-10  Robert Suchanek  <robert.suchanek@imgtec.com>
  81
  82         * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
  83
  84 2015-08-07  Amit Pawar <Amit.Pawar@amd.com>
  85
  86         * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
  87         * i386-init.h: Regenerated.
  88
  89 2015-07-30  H.J. Lu  <hongjiu.lu@intel.com>
  90
  91         PR binutils/13571
  92         * i386-dis.c (MOD_0FC3): New.
  93         (PREFIX_0FC3): Renamed to ...
  94         (PREFIX_MOD_0_0FC3): This.
  95         (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
  96         (prefix_table): Replace Ma with Ev on movntiS.
  97         (mod_table): Add MOD_0FC3.
  98
  99 2015-07-27  H.J. Lu  <hongjiu.lu@intel.com>
 100
 101         * configure: Regenerated.
 102
 103 2015-07-23  Alan Modra  <amodra@gmail.com>
 104
 105         PR 18708
 106         * i386-dis.c (get64): Avoid signed integer overflow.
 107
 108 2015-07-22  Alexander Fomin  <alexander.fomin@intel.com>
 109
 110         PR binutils/18631
 111         * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
 112         "EXEvexHalfBcstXmmq" for the second operand.
 113         (EVEX_W_0F79_P_2): Likewise.
 114         (EVEX_W_0F7A_P_2): Likewise.
 115         (EVEX_W_0F7B_P_2): Likewise.
 116
 117 2015-07-16  Alessandro Marzocchi  <alessandro.marzocchi@gmail.com>
 118
 119         * arm-dis.c (print_insn_coprocessor): Added support for quarter
 120         float bitfield format.
 121         (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
 122         quarter float bitfield format.
 123
 124 2015-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 125
 126         * configure: Regenerated.
 127
 128 2015-07-03  Alan Modra  <amodra@gmail.com>
 129
 130         * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
 131         * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries.  Add
 132         PPC_OPCODE_7450 to 7450 entry.  Add PPC_OPCODE_750 to 750cl entry.
 133
 134 2015-07-01  Sandra Loosemore  <sandra@codesourcery.com>
 135             Cesar Philippidis  <cesar@codesourcery.com>
 136
 137         * nios2-dis.c (nios2_extract_opcode): New.
 138         (nios2_disassembler_state): New.
 139         (nios2_find_opcode_hash): Use mach parameter to select correct
 140         disassembler state.
 141         (nios2_print_insn_arg): Extend to support new R2 argument letters
 142         and formats.
 143         (print_insn_nios2): Check for 16-bit instruction at end of memory.
 144         * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
 145         (NIOS2_NUM_OPCODES): Rename to...
 146         (NIOS2_NUM_R1_OPCODES): This.
 147         (nios2_r2_opcodes): New.
 148         (NIOS2_NUM_R2_OPCODES): New.
 149         (nios2_num_r2_opcodes): New.
 150         (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
 151         (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
 152         (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
 153         (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
 154         (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
 155
 156 2015-06-30  Amit Pawar  <Amit.Pawar@amd.com>
 157
 158         * i386-dis.c (OP_Mwaitx): New.
 159         (rm_table): Add monitorx/mwaitx.
 160         * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
 161         and CPU_ZNVER1_FLAGS.  Add CPU_MWAITX_FLAGS.
 162         (operand_type_init): Add CpuMWAITX.
 163         * i386-opc.h (CpuMWAITX): New.
 164         (i386_cpu_flags): Add cpumwaitx.
 165         * i386-opc.tbl: Add monitorx and mwaitx.
 166         * i386-init.h: Regenerated.
 167         * i386-tbl.h: Likewise.
 168
 169 2015-06-22  Peter Bergner  <bergner@vnet.ibm.com>
 170
 171         * ppc-opc.c (insert_ls): Test for invalid LS operands.
 172         (insert_esync): New function.
 173         (LS, WC): Use insert_ls.
 174         (ESYNC): Use insert_esync.
 175
 176 2015-06-22  Nick Clifton  <nickc@redhat.com>
 177
 178         * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
 179         requested region lies beyond it.
 180         * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
 181         looking for 32-bit insns.
 182         * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
 183         data.
 184         * sh-dis.c (print_insn_sh): Likewise.
 185         * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
 186         blocks of instructions.
 187         * vax-dis.c (print_insn_vax): Check that the requested address
 188         does not clash with the stop_vma.
 189
 190 2015-06-19  Peter Bergner  <bergner@vnet.ibm.com>
 191
 192         * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
 193         * ppc-opc.c (FXM4): Add non-zero optional value.
 194         (TBR): Likewise.
 195         (SXL): Likewise.
 196         (insert_fxm): Handle new default operand value.
 197         (extract_fxm): Likewise.
 198         (insert_tbr): Likewise.
 199         (extract_tbr): Likewise.
 200
 201 2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
 202
 203         * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
 204
 205 2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 206
 207         * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
 208
 209 2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>
 210
 211         * ppc-opc.c: Add comment accidentally removed by old commit.
 212         (MTMSRD_L): Delete.
 213
 214 2015-06-04  Peter Bergner  <bergner@vnet.ibm.com>
 215
 216         * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
 217
 218 2015-06-04  Nick Clifton  <nickc@redhat.com>
 219
 220         PR 18474
 221         * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
 222
 223 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 224
 225         * arm-dis.c (arm_opcodes): Add "setpan".
 226         (thumb_opcodes): Add "setpan".
 227
 228 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 229
 230         * arm-dis.c (select_arm_features): Rework to avoid used of redefined
 231         macros.
 232
 233 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 234
 235         * aarch64-tbl.h (aarch64_feature_rdma): New.
 236         (RDMA): New.
 237         (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
 238         * aarch64-asm-2.c: Regenerate.
 239         * aarch64-dis-2.c: Regenerate.
 240         * aarch64-opc-2.c: Regenerate.
 241
 242 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 243
 244         * aarch64-tbl.h (aarch64_feature_lor): New.
 245         (LOR): New.
 246         (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
 247         "stllrb", "stllrh".
 248         * aarch64-asm-2.c: Regenerate.
 249         * aarch64-dis-2.c: Regenerate.
 250         * aarch64-opc-2.c: Regenerate.
 251
 252 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
 253
 254         * aarch64-opc.c (F_ARCHEXT): New.
 255         (aarch64_sys_regs): Add "pan".
 256         (aarch64_sys_reg_supported_p): New.
 257         (aarch64_pstatefields): Add "pan".
 258         (aarch64_pstatefield_supported_p): New.
 259
 260 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 261
 262         * i386-tbl.h: Regenerate.
 263
 264 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 265
 266         * i386-dis.c (print_insn): Swap rounding mode specifier and
 267         general purpose register in Intel mode.
 268
 269 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 270
 271         * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
 272         * i386-tbl.h: Regenerate.
 273
 274 2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
 275
 276         * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
 277         * i386-init.h: Regenerated.
 278
 279 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 280
 281         PR binutis/18386
 282         * i386-dis.c: Add comments for '@'.
 283         (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
 284         (enum x86_64_isa): New.
 285         (isa64): Likewise.
 286         (print_i386_disassembler_options): Add amd64 and intel64.
 287         (print_insn): Handle amd64 and intel64.
 288         (putop): Handle '@'.
 289         (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
 290         * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
 291         * i386-opc.h (AMD64): New.
 292         (CpuIntel64): Likewise.
 293         (i386_cpu_flags): Add cpuamd64 and cpuintel64.
 294         * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
 295         Mark direct call/jmp without Disp16|Disp32 as Intel64.
 296         * i386-init.h: Regenerated.
 297         * i386-tbl.h: Likewise.
 298
 299 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
 300
 301         * ppc-opc.c (IH) New define.
 302         (powerpc_opcodes) <wait>: Do not enable for POWER7.
 303         <tlbie>: Add RS operand for POWER7.
 304         <slbia>: Add IH operand for POWER6.
 305
 306 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 307
 308         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
 309         direct branch.
 310         (jmp): Likewise.
 311         * i386-tbl.h: Regenerated.
 312
 313 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 314
 315         * configure.ac: Support bfd_iamcu_arch.
 316         * disassemble.c (disassembler): Support bfd_iamcu_arch.
 317         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
 318         CPU_IAMCU_COMPAT_FLAGS.
 319         (cpu_flags): Add CpuIAMCU.
 320         * i386-opc.h (CpuIAMCU): New.
 321         (i386_cpu_flags): Add cpuiamcu.
 322         * configure: Regenerated.
 323         * i386-init.h: Likewise.
 324         * i386-tbl.h: Likewise.
 325
 326 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
 327
 328         PR binutis/18386
 329         * i386-dis.c (X86_64_E8): New.
 330         (X86_64_E9): Likewise.
 331         Update comments on 'T', 'U', 'V'.  Add comments for '^'.
 332         (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
 333         (x86_64_table): Add X86_64_E8 and X86_64_E9.
 334         (mod_table): Replace {T|} with ^ on Jcall/Jmp.
 335         (putop): Handle '^'.
 336         (OP_J): Ignore the operand size prefix in 64-bit.  Don't check
 337         REX_W.
 338
 339 2015-04-30  DJ Delorie  <dj@redhat.com>
 340
 341         * disassemble.c (disassembler): Choose suitable disassembler based
 342         on E_ABI.
 343         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
 344         it to decode mul/div insns.
 345         * rl78-decode.c: Regenerate.
 346         * rl78-dis.c (print_insn_rl78): Rename to...
 347         (print_insn_rl78_common): ...this, take ISA parameter.
 348         (print_insn_rl78): New.
 349         (print_insn_rl78_g10): New.
 350         (print_insn_rl78_g13): New.
 351         (print_insn_rl78_g14): New.
 352         (rl78_get_disassembler): New.
 353
 354 2015-04-29  Nick Clifton  <nickc@redhat.com>
 355
 356         * po/fr.po: Updated French translation.
 357
 358 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
 359
 360         * ppc-opc.c (DCBT_EO): New define.
 361         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
 362         <lharx>: Likewise.
 363         <stbcx.>: Likewise.
 364         <sthcx.>: Likewise.
 365         <waitrsv>: Do not enable for POWER7 and later.
 366         <waitimpl>: Likewise.
 367         <dcbt>: Default to the two operand form of the instruction for all
 368         "old" cpus.  For "new" cpus, use the operand ordering that matches
 369         whether the cpu is server or embedded.
 370         <dcbtst>: Likewise.
 371
 372 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 373
 374         * s390-opc.c: New instruction type VV0UU2.
 375         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
 376         and WFC.
 377
 378 2015-04-23  Jan Beulich  <jbeulich@suse.com>
 379
 380         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
 381         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
 382         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
 383         (vfpclasspd, vfpclassps): Add %XZ.
 384
 385 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 386
 387         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
 388         (PREFIX_UD_REPZ): Likewise.
 389         (PREFIX_UD_REPNZ): Likewise.
 390         (PREFIX_UD_DATA): Likewise.
 391         (PREFIX_UD_ADDR): Likewise.
 392         (PREFIX_UD_LOCK): Likewise.
 393
 394 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 395
 396         * i386-dis.c (prefix_requirement): Removed.
 397         (print_insn): Don't set prefix_requirement.  Check
 398         dp->prefix_requirement instead of prefix_requirement.
 399
 400 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 401
 402         PR binutils/17898
 403         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
 404         (PREFIX_MOD_0_0FC7_REG_6): This.
 405         (PREFIX_MOD_3_0FC7_REG_6): New.
 406         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
 407         (prefix_table): Replace PREFIX_0FC7_REG_6 with
 408         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
 409         PREFIX_MOD_3_0FC7_REG_7.
 410         (mod_table): Replace PREFIX_0FC7_REG_6 with
 411         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
 412         PREFIX_MOD_3_0FC7_REG_7.
 413
 414 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 415
 416         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
 417         (PREFIX_MANDATORY_REPNZ): Likewise.
 418         (PREFIX_MANDATORY_DATA): Likewise.
 419         (PREFIX_MANDATORY_ADDR): Likewise.
 420         (PREFIX_MANDATORY_LOCK): Likewise.
 421         (PREFIX_MANDATORY): Likewise.
 422         (PREFIX_UD_SHIFT): Set to 8
 423         (PREFIX_UD_REPZ): Updated.
 424         (PREFIX_UD_REPNZ): Likewise.
 425         (PREFIX_UD_DATA): Likewise.
 426         (PREFIX_UD_ADDR): Likewise.
 427         (PREFIX_UD_LOCK): Likewise.
 428         (PREFIX_IGNORED_SHIFT): New.
 429         (PREFIX_IGNORED_REPZ): Likewise.
 430         (PREFIX_IGNORED_REPNZ): Likewise.
 431         (PREFIX_IGNORED_DATA): Likewise.
 432         (PREFIX_IGNORED_ADDR): Likewise.
 433         (PREFIX_IGNORED_LOCK): Likewise.
 434         (PREFIX_OPCODE): Likewise.
 435         (PREFIX_IGNORED): Likewise.
 436         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 437         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 438         (three_byte_table): Likewise.
 439         (mod_table): Likewise.
 440         (mandatory_prefix): Renamed to ...
 441         (prefix_requirement): This.
 442         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 443         Update PREFIX_90 entry.
 444         (get_valid_dis386): Check prefix_requirement to see if a prefix
 445         should be ignored.
 446         (print_insn): Replace mandatory_prefix with prefix_requirement.
 447
 448 2015-04-15  Renlin Li  <renlin.li@arm.com>
 449
 450         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
 451         use it for ssat and ssat16.
 452         (print_insn_thumb32): Add handle case for 'D' control code.
 453
 454 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
 455             H.J. Lu  <hongjiu.lu@intel.com>
 456
 457         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
 458         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
 459         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
 460         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
 461         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
 462         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
 463         Fill prefix_requirement field.
 464         (struct dis386): Add prefix_requirement field.
 465         (dis386): Fill prefix_requirement field.
 466         (dis386_twobyte): Ditto.
 467         (twobyte_has_mandatory_prefix_: Remove.
 468         (reg_table): Fill prefix_requirement field.
 469         (prefix_table): Ditto.
 470         (x86_64_table): Ditto.
 471         (three_byte_table): Ditto.
 472         (xop_table): Ditto.
 473         (vex_table): Ditto.
 474         (vex_len_table): Ditto.
 475         (vex_w_table): Ditto.
 476         (mod_table): Ditto.
 477         (bad_opcode): Ditto.
 478         (print_insn): Use prefix_requirement.
 479         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
 480         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
 481         (float_reg): Ditto.
 482
 483 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
 484
 485         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
 486
 487 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 488
 489         * Makefile.in: Regenerated.
 490
 491 2015-03-25  Anton Blanchard  <anton@samba.org>
 492
 493         * ppc-dis.c (disassemble_init_powerpc): Only initialise
 494         powerpc_opcd_indices and vle_opcd_indices once.
 495
 496 2015-03-25  Anton Blanchard  <anton@samba.org>
 497
 498         * ppc-opc.c (powerpc_opcodes): Add slbfee.
 499
 500 2015-03-24  Terry Guo  <terry.guo@arm.com>
 501
 502         * arm-dis.c (opcode32): Updated to use new arm feature struct.
 503         (opcode16): Likewise.
 504         (coprocessor_opcodes): Replace bit with feature struct.
 505         (neon_opcodes): Likewise.
 506         (arm_opcodes): Likewise.
 507         (thumb_opcodes): Likewise.
 508         (thumb32_opcodes): Likewise.
 509         (print_insn_coprocessor): Likewise.
 510         (print_insn_arm): Likewise.
 511         (select_arm_features): Follow new feature struct.
 512
 513 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 514
 515         * i386-dis.c (rm_table): Add clzero.
 516         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
 517         Add CPU_CLZERO_FLAGS.
 518         (cpu_flags): Add CpuCLZERO.
 519         * i386-opc.h: Add CpuCLZERO.
 520         * i386-opc.tbl: Add clzero.
 521         * i386-init.h: Re-generated.
 522         * i386-tbl.h: Re-generated.
 523
 524 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 525
 526         * mips-opc.c (decode_mips_operand): Fix constraint issues
 527         with u and y operands.
 528
 529 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 530
 531         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
 532
 533 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 534
 535         * s390-opc.c: Add new IBM z13 instructions.
 536         * s390-opc.txt: Likewise.
 537
 538 2015-03-10  Renlin Li  <renlin.li@arm.com>
 539
 540         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
 541         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
 542         related alias.
 543         * aarch64-asm-2.c: Regenerate.
 544         * aarch64-dis-2.c: Likewise.
 545         * aarch64-opc-2.c: Likewise.
 546
 547 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
 548
 549         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
 550
 551 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
 552
 553         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
 554         arch_sh_up.
 555         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
 556         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
 557
 558 2015-02-23  Vinay  <Vinay.G@kpit.com>
 559
 560         * rl78-decode.opc (MOV): Added space between two operands for
 561         'mov' instruction in index addressing mode.
 562         * rl78-decode.c: Regenerate.
 563
 564 2015-02-19  Pedro Alves  <palves@redhat.com>
 565
 566         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
 567
 568 2015-02-10  Pedro Alves  <palves@redhat.com>
 569             Tom Tromey  <tromey@redhat.com>
 570
 571         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
 572         microblaze_and, microblaze_xor.
 573         * microblaze-opc.h (opcodes): Adjust.
 574
 575 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
 576
 577         * Makefile.am: Add FT32 files.
 578         * configure.ac: Handle FT32.
 579         * disassemble.c (disassembler): Call print_insn_ft32.
 580         * ft32-dis.c: New file.
 581         * ft32-opc.c: New file.
 582         * Makefile.in: Regenerate.
 583         * configure: Regenerate.
 584         * po/POTFILES.in: Regenerate.
 585
 586 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 587
 588         * nds32-asm.c (keyword_sr): Add new system registers.
 589
 590 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 591
 592         * s390-dis.c (s390_extract_operand): Support vector register
 593         operands.
 594         (s390_print_insn_with_opcode): Support new operands types and add
 595         new handling of optional operands.
 596         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
 597         and include opcode/s390.h instead.
 598         (struct op_struct): New field `flags'.
 599         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
 600         (dumpTable): Dump flags.
 601         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
 602         string.
 603         * s390-opc.c: Add new operands types, instruction formats, and
 604         instruction masks.
 605         (s390_opformats): Add new formats for .insn.
 606         * s390-opc.txt: Add new instructions.
 607
 608 2015-01-01  Alan Modra  <amodra@gmail.com>
 609
 610         Update year range in copyright notice of all files.
 611
 612 For older changes see ChangeLog-2014
 613 \f
 614 Copyright (C) 2015 Free Software Foundation, Inc.
 615
 616 Copying and distribution of this file, with or without modification,
 617 are permitted in any medium without royalty provided the copyright
 618 notice and this notice are preserved.
 619
 620 Local Variables:
 621 mode: change-log
 622 left-margin: 8
 623 fill-column: 74
 624 version-control: never
 625 End: