opcodes/ChangeLog

   1 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
   2
   3         * arm-dis.c: Update strht pattern.
   4
   5 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
   6
   7         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
   8         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
   9         trunc.w.s macro for EE.
  10
  11 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
  12             Andrew Jenner <andrew@codesourcery.com>
  13
  14         Based on patches from Altera Corporation.
  15
  16         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
  17         nios2-opc.c.
  18         * Makefile.in: Regenerated.
  19         * configure.in: Add case for bfd_nios2_arch.
  20         * configure: Regenerated.
  21         * disassemble.c (ARCH_nios2): Define.
  22         (disassembler): Add case for bfd_arch_nios2.
  23         * nios2-dis.c: New file.
  24         * nios2-opc.c: New file.
  25
  26 2013-02-04  Alan Modra  <amodra@gmail.com>
  27
  28         * po/POTFILES.in: Regenerate.
  29         * rl78-decode.c: Regenerate.
  30         * rx-decode.c: Regenerate.
  31
  32 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
  33
  34         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
  35         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
  36         * aarch64-asm.c (convert_xtl_to_shll): New function.
  37         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
  38         calling convert_xtl_to_shll.
  39         * aarch64-dis.c (convert_shll_to_xtl): New function.
  40         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
  41         calling convert_shll_to_xtl.
  42         * aarch64-gen.c: Update copyright year.
  43         * aarch64-asm-2.c: Re-generate.
  44         * aarch64-dis-2.c: Re-generate.
  45         * aarch64-opc-2.c: Re-generate.
  46
  47 2013-01-24  Nick Clifton  <nickc@redhat.com>
  48
  49         * v850-dis.c: Add support for e3v5 architecture.
  50         * v850-opc.c: Likewise.
  51
  52 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
  53
  54         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
  55         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
  56         * aarch64-opc.c (operand_general_constraint_met_p): For
  57         AARCH64_MOD_LSL, move the range check on the shift amount before the
  58         alignment check; change to call set_sft_amount_out_of_range_error
  59         instead of set_imm_out_of_range_error.
  60         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
  61         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
  62         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
  63         SIMD_IMM_SFT.
  64
  65 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
  66
  67         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
  68
  69         * i386-init.h: Regenerated.
  70         * i386-tbl.h: Likewise.
  71
  72 2013-01-15  Nick Clifton  <nickc@redhat.com>
  73
  74         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
  75         values.
  76         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
  77
  78 2013-01-14  Will Newton <will.newton@imgtec.com>
  79
  80         * metag-dis.c (REG_WIDTH): Increase to 64.
  81
  82 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
  83
  84         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
  85         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
  86         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
  87         (SH6): Update.
  88         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
  89         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
  90         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
  91         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
  92
  93 2013-01-10  Will Newton <will.newton@imgtec.com>
  94
  95         * Makefile.am: Add Meta.
  96         * configure.in: Add Meta.
  97         * disassemble.c: Add Meta support.
  98         * metag-dis.c: New file.
  99         * Makefile.in: Regenerate.
 100         * configure: Regenerate.
 101
 102 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 103
 104         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
 105         (match_opcode): Rename to cr16_match_opcode.
 106
 107 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
 108
 109         * mips-dis.c: Add names for CP0 registers of r5900.
 110         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
 111         instructions sq and lq.
 112         Add support for MIPS r5900 CPU.
 113         Add support for 128 bit MMI (Multimedia Instructions).
 114         Add support for EE instructions (Emotion Engine).
 115         Disable unsupported floating point instructions (64 bit and
 116         undefined compare operations).
 117         Enable instructions of MIPS ISA IV which are supported by r5900.
 118         Disable 64 bit co processor instructions.
 119         Disable 64 bit multiplication and division instructions.
 120         Disable instructions for co-processor 2 and 3, because these are
 121         not supported (preparation for later VU0 support (Vector Unit)).
 122         Disable cvt.w.s because this behaves like trunc.w.s and the
 123         correct execution can't be ensured on r5900.
 124         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
 125         will confuse less developers and compilers.
 126
 127 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 128
 129         * aarch64-opc.c (aarch64_print_operand): Change to print
 130         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
 131         in comment.
 132         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
 133         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
 134         OP_MOV_IMM_WIDE.
 135
 136 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 137
 138         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
 139         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
 140
 141 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
 142
 143         * i386-gen.c (process_copyright): Update copyright year to 2013.
 144
 145 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 146
 147         * cr16-dis.c (match_opcode,make_instruction): Remove static
 148         declaration.
 149         (dwordU,wordU): Moved typedefs to opcode/cr16.h
 150         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
 151
 152 For older changes see ChangeLog-2012
 153 \f
 154 Copyright (C) 2013 Free Software Foundation, Inc.
 155
 156 Copying and distribution of this file, with or without modification,
 157 are permitted in any medium without royalty provided the copyright
 158 notice and this notice are preserved.
 159
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