opcodes/ChangeLog

   1 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
   4         direct branch.
   5         (jmp): Likewise.
   6         * i386-tbl.h: Regenerated.
   7
   8 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
   9
  10         * configure.ac: Support bfd_iamcu_arch.
  11         * disassemble.c (disassembler): Support bfd_iamcu_arch.
  12         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
  13         CPU_IAMCU_COMPAT_FLAGS.
  14         (cpu_flags): Add CpuIAMCU.
  15         * i386-opc.h (CpuIAMCU): New.
  16         (i386_cpu_flags): Add cpuiamcu.
  17         * configure: Regenerated.
  18         * i386-init.h: Likewise.
  19         * i386-tbl.h: Likewise.
  20
  21 2015-04-30  DJ Delorie  <dj@redhat.com>
  22
  23         * disassemble.c (disassembler): Choose suitable disassembler based
  24         on E_ABI.
  25         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
  26         it to decode mul/div insns.
  27         * rl78-decode.c: Regenerate.
  28         * rl78-dis.c (print_insn_rl78): Rename to...
  29         (print_insn_rl78_common): ...this, take ISA parameter.
  30         (print_insn_rl78): New.
  31         (print_insn_rl78_g10): New.
  32         (print_insn_rl78_g13): New.
  33         (print_insn_rl78_g14): New.
  34         (rl78_get_disassembler): New.
  35
  36 2015-04-29  Nick Clifton  <nickc@redhat.com>
  37
  38         * po/fr.po: Updated French translation.
  39
  40 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
  41
  42         * ppc-opc.c (DCBT_EO): New define.
  43         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
  44         <lharx>: Likewise.
  45         <stbcx.>: Likewise.
  46         <sthcx.>: Likewise.
  47         <waitrsv>: Do not enable for POWER7 and later.
  48         <waitimpl>: Likewise.
  49         <dcbt>: Default to the two operand form of the instruction for all
  50         "old" cpus.  For "new" cpus, use the operand ordering that matches
  51         whether the cpu is server or embedded.
  52         <dcbtst>: Likewise.
  53
  54 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
  55
  56         * s390-opc.c: New instruction type VV0UU2.
  57         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
  58         and WFC.
  59
  60 2015-04-23  Jan Beulich  <jbeulich@suse.com>
  61
  62         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
  63         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
  64         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
  65         (vfpclasspd, vfpclassps): Add %XZ.
  66
  67 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
  68
  69         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
  70         (PREFIX_UD_REPZ): Likewise.
  71         (PREFIX_UD_REPNZ): Likewise.
  72         (PREFIX_UD_DATA): Likewise.
  73         (PREFIX_UD_ADDR): Likewise.
  74         (PREFIX_UD_LOCK): Likewise.
  75
  76 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
  77
  78         * i386-dis.c (prefix_requirement): Removed.
  79         (print_insn): Don't set prefix_requirement.  Check
  80         dp->prefix_requirement instead of prefix_requirement.
  81
  82 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
  83
  84         PR binutils/17898
  85         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
  86         (PREFIX_MOD_0_0FC7_REG_6): This.
  87         (PREFIX_MOD_3_0FC7_REG_6): New.
  88         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
  89         (prefix_table): Replace PREFIX_0FC7_REG_6 with
  90         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
  91         PREFIX_MOD_3_0FC7_REG_7.
  92         (mod_table): Replace PREFIX_0FC7_REG_6 with
  93         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
  94         PREFIX_MOD_3_0FC7_REG_7.
  95
  96 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
  97
  98         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
  99         (PREFIX_MANDATORY_REPNZ): Likewise.
 100         (PREFIX_MANDATORY_DATA): Likewise.
 101         (PREFIX_MANDATORY_ADDR): Likewise.
 102         (PREFIX_MANDATORY_LOCK): Likewise.
 103         (PREFIX_MANDATORY): Likewise.
 104         (PREFIX_UD_SHIFT): Set to 8
 105         (PREFIX_UD_REPZ): Updated.
 106         (PREFIX_UD_REPNZ): Likewise.
 107         (PREFIX_UD_DATA): Likewise.
 108         (PREFIX_UD_ADDR): Likewise.
 109         (PREFIX_UD_LOCK): Likewise.
 110         (PREFIX_IGNORED_SHIFT): New.
 111         (PREFIX_IGNORED_REPZ): Likewise.
 112         (PREFIX_IGNORED_REPNZ): Likewise.
 113         (PREFIX_IGNORED_DATA): Likewise.
 114         (PREFIX_IGNORED_ADDR): Likewise.
 115         (PREFIX_IGNORED_LOCK): Likewise.
 116         (PREFIX_OPCODE): Likewise.
 117         (PREFIX_IGNORED): Likewise.
 118         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 119         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 120         (three_byte_table): Likewise.
 121         (mod_table): Likewise.
 122         (mandatory_prefix): Renamed to ...
 123         (prefix_requirement): This.
 124         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 125         Update PREFIX_90 entry.
 126         (get_valid_dis386): Check prefix_requirement to see if a prefix
 127         should be ignored.
 128         (print_insn): Replace mandatory_prefix with prefix_requirement.
 129
 130 2015-04-15  Renlin Li  <renlin.li@arm.com>
 131
 132         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
 133         use it for ssat and ssat16.
 134         (print_insn_thumb32): Add handle case for 'D' control code.
 135
 136 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
 137             H.J. Lu  <hongjiu.lu@intel.com>
 138
 139         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
 140         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
 141         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
 142         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
 143         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
 144         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
 145         Fill prefix_requirement field.
 146         (struct dis386): Add prefix_requirement field.
 147         (dis386): Fill prefix_requirement field.
 148         (dis386_twobyte): Ditto.
 149         (twobyte_has_mandatory_prefix_: Remove.
 150         (reg_table): Fill prefix_requirement field.
 151         (prefix_table): Ditto.
 152         (x86_64_table): Ditto.
 153         (three_byte_table): Ditto.
 154         (xop_table): Ditto.
 155         (vex_table): Ditto.
 156         (vex_len_table): Ditto.
 157         (vex_w_table): Ditto.
 158         (mod_table): Ditto.
 159         (bad_opcode): Ditto.
 160         (print_insn): Use prefix_requirement.
 161         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
 162         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
 163         (float_reg): Ditto.
 164
 165 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
 166
 167         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
 168
 169 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 170
 171         * Makefile.in: Regenerated.
 172
 173 2015-03-25  Anton Blanchard  <anton@samba.org>
 174
 175         * ppc-dis.c (disassemble_init_powerpc): Only initialise
 176         powerpc_opcd_indices and vle_opcd_indices once.
 177
 178 2015-03-25  Anton Blanchard  <anton@samba.org>
 179
 180         * ppc-opc.c (powerpc_opcodes): Add slbfee.
 181
 182 2015-03-24  Terry Guo  <terry.guo@arm.com>
 183
 184         * arm-dis.c (opcode32): Updated to use new arm feature struct.
 185         (opcode16): Likewise.
 186         (coprocessor_opcodes): Replace bit with feature struct.
 187         (neon_opcodes): Likewise.
 188         (arm_opcodes): Likewise.
 189         (thumb_opcodes): Likewise.
 190         (thumb32_opcodes): Likewise.
 191         (print_insn_coprocessor): Likewise.
 192         (print_insn_arm): Likewise.
 193         (select_arm_features): Follow new feature struct.
 194
 195 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 196
 197         * i386-dis.c (rm_table): Add clzero.
 198         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
 199         Add CPU_CLZERO_FLAGS.
 200         (cpu_flags): Add CpuCLZERO.
 201         * i386-opc.h: Add CpuCLZERO.
 202         * i386-opc.tbl: Add clzero.
 203         * i386-init.h: Re-generated.
 204         * i386-tbl.h: Re-generated.
 205
 206 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 207
 208         * mips-opc.c (decode_mips_operand): Fix constraint issues
 209         with u and y operands.
 210
 211 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 212
 213         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
 214
 215 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 216
 217         * s390-opc.c: Add new IBM z13 instructions.
 218         * s390-opc.txt: Likewise.
 219
 220 2015-03-10  Renlin Li  <renlin.li@arm.com>
 221
 222         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
 223         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
 224         related alias.
 225         * aarch64-asm-2.c: Regenerate.
 226         * aarch64-dis-2.c: Likewise.
 227         * aarch64-opc-2.c: Likewise.
 228
 229 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
 230
 231         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
 232
 233 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
 234
 235         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
 236         arch_sh_up.
 237         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
 238         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
 239
 240 2015-02-23  Vinay  <Vinay.G@kpit.com>
 241
 242         * rl78-decode.opc (MOV): Added space between two operands for
 243         'mov' instruction in index addressing mode.
 244         * rl78-decode.c: Regenerate.
 245
 246 2015-02-19  Pedro Alves  <palves@redhat.com>
 247
 248         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
 249
 250 2015-02-10  Pedro Alves  <palves@redhat.com>
 251             Tom Tromey  <tromey@redhat.com>
 252
 253         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
 254         microblaze_and, microblaze_xor.
 255         * microblaze-opc.h (opcodes): Adjust.
 256
 257 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
 258
 259         * Makefile.am: Add FT32 files.
 260         * configure.ac: Handle FT32.
 261         * disassemble.c (disassembler): Call print_insn_ft32.
 262         * ft32-dis.c: New file.
 263         * ft32-opc.c: New file.
 264         * Makefile.in: Regenerate.
 265         * configure: Regenerate.
 266         * po/POTFILES.in: Regenerate.
 267
 268 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 269
 270         * nds32-asm.c (keyword_sr): Add new system registers.
 271
 272 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 273
 274         * s390-dis.c (s390_extract_operand): Support vector register
 275         operands.
 276         (s390_print_insn_with_opcode): Support new operands types and add
 277         new handling of optional operands.
 278         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
 279         and include opcode/s390.h instead.
 280         (struct op_struct): New field `flags'.
 281         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
 282         (dumpTable): Dump flags.
 283         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
 284         string.
 285         * s390-opc.c: Add new operands types, instruction formats, and
 286         instruction masks.
 287         (s390_opformats): Add new formats for .insn.
 288         * s390-opc.txt: Add new instructions.
 289
 290 2015-01-01  Alan Modra  <amodra@gmail.com>
 291
 292         Update year range in copyright notice of all files.
 293
 294 For older changes see ChangeLog-2014
 295 \f
 296 Copyright (C) 2015 Free Software Foundation, Inc.
 297
 298 Copying and distribution of this file, with or without modification,
 299 are permitted in any medium without royalty provided the copyright
 300 notice and this notice are preserved.
 301
 302 Local Variables:
 303 mode: change-log
 304 left-margin: 8
 305 fill-column: 74
 306 version-control: never
 307 End: