opcodes/ChangeLog

   1 2017-03-06  Alan Modra  <amodra@gmail.com>
   2
   3         PR 21124
   4         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
   5         (extract_raq, extract_ras, extract_rbx): New functions.
   6         (powerpc_operands): Use opposite corresponding insert function.
   7         (Q_MASK): Define.
   8         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
   9         register restriction.
  10
  11 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
  12
  13         * disassemble.c Include "safe-ctype.h".
  14         (disassemble_init_for_target): Handle s390 init.
  15         (remove_whitespace_and_extra_commas): New function.
  16         (disassembler_options_cmp): Likewise.
  17         * arm-dis.c: Include "libiberty.h".
  18         (NUM_ELEM): Delete.
  19         (regnames): Use long disassembler style names.
  20         Add force-thumb and no-force-thumb options.
  21         (NUM_ARM_REGNAMES): Rename from this...
  22         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
  23         (get_arm_regname_num_options): Delete.
  24         (set_arm_regname_option): Likewise.
  25         (get_arm_regnames): Likewise.
  26         (parse_disassembler_options): Likewise.
  27         (parse_arm_disassembler_option): Rename from this...
  28         (parse_arm_disassembler_options): ...to this.  Make static.
  29         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
  30         (print_insn): Use parse_arm_disassembler_options.
  31         (disassembler_options_arm): New function.
  32         (print_arm_disassembler_options): Handle updated regnames.
  33         * ppc-dis.c: Include "libiberty.h".
  34         (ppc_opts): Add "32" and "64" entries.
  35         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
  36         (powerpc_init_dialect): Add break to switch statement.
  37         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
  38         (disassembler_options_powerpc): New function.
  39         (print_ppc_disassembler_options): Use ARRAY_SIZE.
  40         Remove printing of "32" and "64".
  41         * s390-dis.c: Include "libiberty.h".
  42         (init_flag): Remove unneeded variable.
  43         (struct s390_options_t): New structure type.
  44         (options): New structure.
  45         (init_disasm): Rename from this...
  46         (disassemble_init_s390): ...to this.  Add initializations for
  47         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
  48         (print_insn_s390): Delete call to init_disasm.
  49         (disassembler_options_s390): New function.
  50         (print_s390_disassembler_options): Print using information from
  51         struct 'options'.
  52         * po/opcodes.pot: Regenerate.
  53
  54 2017-02-28  Jan Beulich  <jbeulich@suse.com>
  55
  56         * i386-dis.c (PCMPESTR_Fixup): New.
  57         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
  58         (prefix_table): Use PCMPESTR_Fixup.
  59         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
  60         PCMPESTR_Fixup.
  61         (vex_w_table): Delete VPCMPESTR{I,M} entries.
  62         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
  63         Split 64-bit and non-64-bit variants.
  64         * opcodes/i386-tbl.h: Re-generate.
  65
  66 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
  67
  68         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
  69         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
  70         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
  71         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
  72         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
  73         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
  74         (OP_SVE_V_HSD): New macros.
  75         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
  76         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
  77         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
  78         (aarch64_opcode_table): Add new SVE instructions.
  79         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
  80         for rotation operands.  Add new SVE operands.
  81         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
  82         (ins_sve_quad_index): Likewise.
  83         (ins_imm_rotate): Split into...
  84         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
  85         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
  86         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
  87         functions.
  88         (aarch64_ins_sve_addr_ri_s4): New function.
  89         (aarch64_ins_sve_quad_index): Likewise.
  90         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
  91         * aarch64-asm-2.c: Regenerate.
  92         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
  93         (ext_sve_quad_index): Likewise.
  94         (ext_imm_rotate): Split into...
  95         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
  96         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
  97         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
  98         functions.
  99         (aarch64_ext_sve_addr_ri_s4): New function.
 100         (aarch64_ext_sve_quad_index): Likewise.
 101         (aarch64_ext_sve_index): Allow quad indices.
 102         (do_misc_decoding): Likewise.
 103         * aarch64-dis-2.c: Regenerate.
 104         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
 105         aarch64_field_kinds.
 106         (OPD_F_OD_MASK): Widen by one bit.
 107         (OPD_F_NO_ZR): Bump accordingly.
 108         (get_operand_field_width): New function.
 109         * aarch64-opc.c (fields): Add new SVE fields.
 110         (operand_general_constraint_met_p): Handle new SVE operands.
 111         (aarch64_print_operand): Likewise.
 112         * aarch64-opc-2.c: Regenerate.
 113
 114 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 115
 116         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
 117         (aarch64_feature_compnum): ...this.
 118         (SIMD_V8_3): Replace with...
 119         (COMPNUM): ...this.
 120         (CNUM_INSN): New macro.
 121         (aarch64_opcode_table): Use it for the complex number instructions.
 122
 123 2017-02-24  Jan Beulich  <jbeulich@suse.com>
 124
 125         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
 126
 127 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
 128
 129         Add support for associating SPARC ASIs with an architecture level.
 130         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
 131         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
 132         decoding of SPARC ASIs.
 133
 134 2017-02-23  Jan Beulich  <jbeulich@suse.com>
 135
 136         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
 137         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
 138
 139 2017-02-21  Jan Beulich  <jbeulich@suse.com>
 140
 141         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
 142         1 (instead of to itself). Correct typo.
 143
 144 2017-02-14  Andrew Waterman  <andrew@sifive.com>
 145
 146         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
 147         pseudoinstructions.
 148
 149 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
 150
 151         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
 152         (aarch64_sys_reg_supported_p): Handle them.
 153
 154 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
 155
 156         * arc-opc.c (UIMM6_20R): Define.
 157         (SIMM12_20): Use above.
 158         (SIMM12_20R): Define.
 159         (SIMM3_5_S): Use above.
 160         (UIMM7_A32_11R_S): Define.
 161         (UIMM7_9_S): Use above.
 162         (UIMM3_13R_S): Define.
 163         (SIMM11_A32_7_S): Use above.
 164         (SIMM9_8R): Define.
 165         (UIMM10_A32_8_S): Use above.
 166         (UIMM8_8R_S): Define.
 167         (W6): Use above.
 168         (arc_relax_opcodes): Use all above defines.
 169
 170 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
 171
 172         * arc-regs.h: Distinguish some of the registers different on
 173         ARC700 and HS38 cpus.
 174
 175 2017-02-14  Alan Modra  <amodra@gmail.com>
 176
 177         PR 21118
 178         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
 179         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
 180
 181 2017-02-11  Stafford Horne  <shorne@gmail.com>
 182             Alan Modra  <amodra@gmail.com>
 183
 184         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
 185         Use insn_bytes_value and insn_int_value directly instead.  Don't
 186         free allocated memory until function exit.
 187
 188 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
 189
 190         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
 191
 192 2017-02-03  Nick Clifton  <nickc@redhat.com>
 193
 194         PR 21096
 195         * aarch64-opc.c (print_register_list): Ensure that the register
 196         list index will fir into the tb buffer.
 197         (print_register_offset_address): Likewise.
 198         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
 199
 200 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
 201
 202         PR 21056
 203         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
 204         instructions when the previous fetch packet ends with a 32-bit
 205         instruction.
 206
 207 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
 208
 209         * pru-opc.c: Remove vague reference to a future GDB port.
 210
 211 2017-01-20  Nick Clifton  <nickc@redhat.com>
 212
 213         * po/ga.po: Updated Irish translation.
 214
 215 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 216
 217         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
 218
 219 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 220
 221         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
 222         if FETCH_DATA returns 0.
 223         (m68k_scan_mask): Likewise.
 224         (print_insn_m68k): Update code to handle -1 return value.
 225
 226 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 227
 228         * m68k-dis.c (enum print_insn_arg_error): New.
 229         (NEXTBYTE): Replace -3 with
 230         PRINT_INSN_ARG_MEMORY_ERROR.
 231         (NEXTULONG): Likewise.
 232         (NEXTSINGLE): Likewise.
 233         (NEXTDOUBLE): Likewise.
 234         (NEXTDOUBLE): Likewise.
 235         (NEXTPACKED): Likewise.
 236         (FETCH_ARG): Likewise.
 237         (FETCH_DATA): Update comments.
 238         (print_insn_arg): Update comments. Replace magic numbers with
 239         enum.
 240         (match_insn_m68k): Likewise.
 241
 242 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 243
 244         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
 245         * i386-dis-evex.h (evex_table): Updated.
 246         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
 247         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 248         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
 249         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
 250         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
 251         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
 252         * i386-init.h: Regenerate.
 253         * i386-tbl.h: Ditto.
 254
 255 2017-01-12  Yao Qi  <yao.qi@linaro.org>
 256
 257         * msp430-dis.c (msp430_singleoperand): Return -1 if
 258         msp430dis_opcode_signed returns false.
 259         (msp430_doubleoperand): Likewise.
 260         (msp430_branchinstr): Return -1 if
 261         msp430dis_opcode_unsigned returns false.
 262         (msp430x_calla_instr): Likewise.
 263         (print_insn_msp430): Likewise.
 264
 265 2017-01-05  Nick Clifton  <nickc@redhat.com>
 266
 267         PR 20946
 268         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
 269         could not be matched.
 270         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
 271         NULL.
 272
 273 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 274
 275         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
 276         (aarch64_opcode_table): Use RCPC_INSN.
 277
 278 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
 279
 280         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
 281         extension.
 282         * riscv-opcodes/all-opcodes: Likewise.
 283
 284 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
 285
 286         * riscv-dis.c (print_insn_args): Add fall through comment.
 287
 288 2017-01-03  Nick Clifton  <nickc@redhat.com>
 289
 290         * po/sr.po: New Serbian translation.
 291         * configure.ac (ALL_LINGUAS): Add sr.
 292         * configure: Regenerate.
 293
 294 2017-01-02  Alan Modra  <amodra@gmail.com>
 295
 296         * epiphany-desc.h: Regenerate.
 297         * epiphany-opc.h: Regenerate.
 298         * fr30-desc.h: Regenerate.
 299         * fr30-opc.h: Regenerate.
 300         * frv-desc.h: Regenerate.
 301         * frv-opc.h: Regenerate.
 302         * ip2k-desc.h: Regenerate.
 303         * ip2k-opc.h: Regenerate.
 304         * iq2000-desc.h: Regenerate.
 305         * iq2000-opc.h: Regenerate.
 306         * lm32-desc.h: Regenerate.
 307         * lm32-opc.h: Regenerate.
 308         * m32c-desc.h: Regenerate.
 309         * m32c-opc.h: Regenerate.
 310         * m32r-desc.h: Regenerate.
 311         * m32r-opc.h: Regenerate.
 312         * mep-desc.h: Regenerate.
 313         * mep-opc.h: Regenerate.
 314         * mt-desc.h: Regenerate.
 315         * mt-opc.h: Regenerate.
 316         * or1k-desc.h: Regenerate.
 317         * or1k-opc.h: Regenerate.
 318         * xc16x-desc.h: Regenerate.
 319         * xc16x-opc.h: Regenerate.
 320         * xstormy16-desc.h: Regenerate.
 321         * xstormy16-opc.h: Regenerate.
 322
 323 2017-01-02  Alan Modra  <amodra@gmail.com>
 324
 325         Update year range in copyright notice of all files.
 326
 327 For older changes see ChangeLog-2016
 328 \f
 329 Copyright (C) 2017 Free Software Foundation, Inc.
 330
 331 Copying and distribution of this file, with or without modification,
 332 are permitted in any medium without royalty provided the copyright
 333 notice and this notice are preserved.
 334
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 336 mode: change-log
 337 left-margin: 8
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