opcodes/ChangeLog

   1 2013-09-04  Roland McGrath  <mcgrathr@google.com>
   2
   3         PR gas/15914
   4         * arm-dis.c (arm_opcodes): Add udf.
   5         (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
   6         (thumb32_opcodes): Add udf.w.
   7         (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
   8
   9 2013-09-02  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  10
  11         * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
  12         For the load fp integer instructions only the suppression flag was
  13         new with z196 version.
  14
  15 2013-08-28  Nick Clifton  <nickc@redhat.com>
  16
  17         * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
  18         immediate is not suitable for the 32-bit ABI.
  19
  20 2013-08-23  Maciej W. Rozycki  <macro@codesourcery.com>
  21
  22         * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
  23         replacing NODS.
  24
  25 2013-08-23  Yuri Chornoivan  <yurchor@ukr.net>
  26
  27         PR binutils/15834
  28         * aarch64-asm.c: Fix typos.
  29         * aarch64-dis.c: Likewise.
  30         * msp430-dis.c: Likewise.
  31
  32 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
  33
  34         * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
  35         macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
  36         Use +H rather than +C for the real "dext".
  37         * mips-opc.c (mips_builtin_opcodes): Likewise.
  38
  39 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
  40
  41         * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
  42         * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
  43         and OPTIONAL_MAPPED_REG.
  44         * mips-opc.c (decode_mips_operand): Likewise.
  45         * mips16-opc.c (decode_mips16_operand): Likewise.
  46         * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
  47
  48 2013-08-19  H.J. Lu  <hongjiu.lu@intel.com>
  49
  50         * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
  51         (PREFIX_EVEX_0F3A3F): Likewise.
  52         * i386-dis-evex.h (evex_table): Updated.
  53
  54 2013-08-06  Jürgen Urban  <JuergenUrban@gmx.de>
  55
  56         * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
  57         VCLIPW.
  58
  59 2013-08-05  Eric Botcazou  <ebotcazou@adacore.com>
  60             Konrad Eisele  <konrad@gaisler.com>
  61
  62         * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
  63         bfd_mach_sparc.
  64         * sparc-opc.c (MASK_LEON): Define.
  65         (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
  66         (letandleon): New macro.
  67         (v9andleon): Likewise.
  68         (sparc_opc): Add leon.
  69         (umac): Enable for letandleon.
  70         (smac): Likewise.
  71         (casa): Enable for v9andleon.
  72         (cas): Likewise.
  73         (casl): Likewise.
  74
  75 2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
  76             Richard Sandiford  <rdsandiford@googlemail.com>
  77
  78         * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
  79         OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
  80         (print_vu0_channel): New function.
  81         (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
  82         (print_insn_args): Handle '#'.
  83         (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
  84         * mips-opc.c (mips_vu0_channel_mask): New constant.
  85         (decode_mips_operand): Handle new VU0 operand types.
  86         (VU0, VU0CH): New macros.
  87         (mips_builtin_opcodes): Add VU0 opcodes.  Use "+7" rather than "E"
  88         for LQC2 and SQC2.  Use "+9" rather than "G" for EE CFC2 and CTC2.
  89         Use "+6" rather than "G" for QMFC2 and QMTC2.
  90
  91 2013-08-03  Richard Sandiford  <rdsandiford@googlemail.com>
  92
  93         * mips-formats.h (PCREL): Reorder parameters and update the definition
  94         to match new mips_pcrel_operand layout.
  95         (JUMP, JALX, BRANCH): Update accordingly.
  96         * mips16-opc.c (decode_mips16_operand): Likewise.
  97
  98 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
  99
 100         * micromips-opc.c (WR_s): Delete.
 101
 102 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 103
 104         * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
 105         New macros.
 106         (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
 107         (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
 108         (mips_builtin_opcodes): Use the new position-based read-write flags
 109         instead of field-based ones.  Use UDI for "udi..." instructions.
 110         * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
 111         New macros.
 112         (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
 113         (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
 114         (WR_SP, RD_16): New macros.
 115         (RD_SP): Redefine as an INSN2_* flag.
 116         (MOD_SP): Redefine in terms of RD_SP and WR_SP.
 117         (mips16_opcodes): Use the new position-based read-write flags
 118         instead of field-based ones.  Use RD_16 for "nop".  Move RD_SP to
 119         pinfo2 field.
 120         * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
 121         New macros.
 122         (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
 123         (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
 124         (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
 125         (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
 126         (micromips_opcodes): Use the new position-based read-write flags
 127         instead of field-based ones.
 128         * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
 129         (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
 130         of field-based flags.
 131
 132 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 133
 134         * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
 135         (WR_SP): Replace with...
 136         (MOD_SP): ...this.
 137         (mips16_opcodes): Update accordingly.
 138         * mips-dis.c (print_insn_mips16): Likewise.
 139
 140 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 141
 142         * mips16-opc.c (mips16_opcodes): Reformat.
 143
 144 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 145
 146         * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
 147         for operands that are hard-coded to $0.
 148         * micromips-opc.c (micromips_opcodes): Likewise.
 149
 150 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 151
 152         * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
 153         for the single-operand forms of JALR and JALR.HB.
 154         * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
 155         and JALRS.HB.
 156
 157 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 158
 159         * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
 160         instructions.  Fix them to use WR_MACC instead of WR_CC and
 161         add missing RD_MACCs.
 162
 163 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 164
 165         * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
 166
 167 2013-07-29  Peter Bergner <bergner@vnet.ibm.com>
 168
 169         * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
 170
 171 2013-07-26  Sergey Guriev  <sergey.s.guriev@intel.com>
 172             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 173             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 174             Sergey Lega  <sergey.s.lega@intel.com>
 175             Anna Tikhonova  <anna.tikhonova@intel.com>
 176             Ilya Tocar  <ilya.tocar@intel.com>
 177             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 178             Ilya Verbin  <ilya.verbin@intel.com>
 179             Kirill Yukhin  <kirill.yukhin@intel.com>
 180             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 181
 182         * i386-dis-evex.h: New.
 183         * i386-dis.c (OP_Rounding): New.
 184         (VPCMP_Fixup): New.
 185         (OP_Mask): New.
 186         (Rdq): New.
 187         (XMxmmq): New.
 188         (EXdScalarS): New.
 189         (EXymm): New.
 190         (EXEvexHalfBcstXmmq): New.
 191         (EXxmm_mdq): New.
 192         (EXEvexXGscat): New.
 193         (EXEvexXNoBcst): New.
 194         (VPCMP): New.
 195         (EXxEVexR): New.
 196         (EXxEVexS): New.
 197         (XMask): New.
 198         (MaskG): New.
 199         (MaskE): New.
 200         (MaskR): New.
 201         (MaskVex): New.
 202         (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
 203         evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
 204         evex_rounding_mode, evex_sae_mode, mask_mode.
 205         (USE_EVEX_TABLE): New.
 206         (EVEX_TABLE): New.
 207         (EVEX enum): New.
 208         (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
 209         REG_EVEX_0F38C7.
 210         (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
 211         MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
 212         MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
 213         MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 214         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,  MOD_EVEX_0F38C7_REG_5,
 215         MOD_EVEX_0F38C7_REG_6.
 216         (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 217         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
 218         PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 219         PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
 220         PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
 221         PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
 222         PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
 223         PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
 224         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
 225         PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
 226         PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
 227         PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
 228         PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
 229         PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
 230         PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
 231         PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
 232         PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
 233         PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
 234         PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
 235         PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
 236         PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
 237         PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
 238         PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
 239         PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
 240         PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
 241         PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
 242         PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
 243         PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
 244         PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
 245         PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
 246         PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
 247         PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
 248         PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
 249         PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
 250         PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
 251         PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
 252         PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
 253         PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
 254         PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
 255         PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
 256         PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
 257         PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
 258         PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
 259         PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
 260         PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
 261         PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
 262         PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
 263         PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
 264         PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
 265         PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
 266         PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
 267         PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
 268         PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
 269         PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
 270         PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
 271         PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
 272         PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
 273         PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
 274         PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
 275         PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
 276         PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
 277         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
 278         PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
 279         PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
 280         PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
 281         PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
 282         PREFIX_EVEX_0F3A00,  PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
 283         PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
 284         PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
 285         PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
 286         PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
 287         PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
 288         PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
 289         PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
 290         PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
 291         PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
 292         PREFIX_EVEX_0F3A55.
 293         (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
 294         VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
 295         VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
 296         VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
 297         VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
 298         VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
 299         VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
 300         VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
 301         VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
 302         VEX_W_0F3A32_P_2_LEN_0.
 303         (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
 304         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
 305         EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
 306         EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
 307         EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
 308         EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 309         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
 310         EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
 311         EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 312         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
 313         EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 314         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
 315         EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
 316         EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
 317         EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
 318         EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
 319         EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
 320         EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
 321         EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
 322         EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
 323         EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
 324         EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
 325         EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
 326         EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
 327         EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
 328         EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
 329         EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
 330         EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
 331         EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
 332         EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
 333         EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
 334         EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
 335         EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
 336         EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
 337         EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
 338         EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
 339         EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
 340         EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
 341         EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
 342         EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
 343         EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
 344         EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
 345         EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
 346         EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
 347         EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
 348         EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
 349         EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
 350         EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
 351         EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
 352         EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
 353         EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
 354         EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
 355         EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
 356         EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
 357         (struct vex): Add fields evex, r, v, mask_register_specifier,
 358         zeroing, ll, b.
 359         (intel_names_xmm): Add upper 16 registers.
 360         (att_names_xmm): Ditto.
 361         (intel_names_ymm): Ditto.
 362         (att_names_ymm): Ditto.
 363         (names_zmm): New.
 364         (intel_names_zmm): Ditto.
 365         (att_names_zmm): Ditto.
 366         (names_mask): Ditto.
 367         (intel_names_mask): Ditto.
 368         (att_names_mask): Ditto.
 369         (names_rounding): Ditto.
 370         (names_broadcast): Ditto.
 371         (x86_64_table): Add escape to evex-table.
 372         (reg_table): Include reg_table evex-entries from
 373         i386-dis-evex.h.  Fix prefetchwt1 instruction.
 374         (prefix_table): Add entries for new instructions.
 375         (vex_table): Ditto.
 376         (vex_len_table): Ditto.
 377         (vex_w_table): Ditto.
 378         (mod_table): Ditto.
 379         (get_valid_dis386): Properly handle new instructions.
 380         (print_insn): Handle zmm and mask registers, print mask operand.
 381         (intel_operand_size): Support EVEX, new modes and sizes.
 382         (OP_E_register): Handle new modes.
 383         (OP_E_memory): Ditto.
 384         (OP_G): Ditto.
 385         (OP_XMM): Ditto.
 386         (OP_EX): Ditto.
 387         (OP_VEX): Ditto.
 388         * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
 389         CPU_ANY_AVX_FLAGS.  Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
 390         CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 391         (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
 392         CpuAVX512PF and CpuVREX.
 393         (operand_type_init): Add OPERAND_TYPE_REGZMM,
 394         OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
 395         (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
 396         StaticRounding, SAE, Disp8MemShift, NoDefMask.
 397         (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
 398         * i386-init.h: Regenerate.
 399         * i386-opc.h (CpuAVX512F): New.
 400         (CpuAVX512CD): New.
 401         (CpuAVX512ER): New.
 402         (CpuAVX512PF): New.
 403         (CpuVREX): New.
 404         (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
 405         cpuavx512pf and cpuvrex fields.
 406         (VecSIB): Add VecSIB512.
 407         (EVex): New.
 408         (Masking): New.
 409         (VecESize): New.
 410         (Broadcast): New.
 411         (StaticRounding): New.
 412         (SAE): New.
 413         (Disp8MemShift): New.
 414         (NoDefMask): New.
 415         (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
 416         staticrounding, sae, disp8memshift and nodefmask.
 417         (RegZMM): New.
 418         (Zmmword): Ditto.
 419         (Vec_Disp8): Ditto.
 420         (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
 421         fields.
 422         (RegVRex): New.
 423         * i386-opc.tbl: Add AVX512 instructions.
 424         * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
 425         registers, mask registers.
 426         * i386-tbl.h: Regenerate.
 427
 428 2013-07-25  Aaro Koskinen  <aaro.koskinen@iki.fi>
 429
 430         PR gas/15220
 431         * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
 432         Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
 433
 434 2013-07-25  Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 435
 436         * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
 437         PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
 438         PREFIX_0F3ACC.
 439         (prefix_table): Updated.
 440         (three_byte_table): Likewise.
 441         * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
 442         (cpu_flags): Add CpuSHA.
 443         (i386_cpu_flags): Add cpusha.
 444         * i386-init.h: Regenerate.
 445         * i386-opc.h (CpuSHA): New.
 446         (CpuUnused): Restored.
 447         (i386_cpu_flags): Add cpusha.
 448         * i386-opc.tbl: Add SHA instructions.
 449         * i386-tbl.h: Regenerate.
 450
 451 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
 452             Kirill Yukhin  <kirill.yukhin@intel.com>
 453             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 454
 455         * i386-dis.c (BND_Fixup): New.
 456         (Ebnd): New.
 457         (Ev_bnd): New.
 458         (Gbnd): New.
 459         (BND): New.
 460         (v_bnd_mode): New.
 461         (bnd_mode): New.
 462         (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
 463         MOD_0F1B_PREFIX_1.
 464         (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
 465         (dis tables): Replace XX with BND for near branch and call
 466         instructions.
 467         (prefix_table): Add new entries.
 468         (mod_table): Likewise.
 469         (names_bnd): New.
 470         (intel_names_bnd): New.
 471         (att_names_bnd): New.
 472         (BND_PREFIX): New.
 473         (prefix_name): Handle BND_PREFIX.
 474         (print_insn): Initialize names_bnd.
 475         (intel_operand_size): Handle new modes.
 476         (OP_E_register): Likewise.
 477         (OP_E_memory): Likewise.
 478         (OP_G): Likewise.
 479         * i386-gen.c (cpu_flag_init): Add CpuMPX.
 480         (cpu_flags): Add CpuMPX.
 481         (operand_type_init): Add RegBND.
 482         (opcode_modifiers): Add BNDPrefixOk.
 483         (operand_types): Add RegBND.
 484         * i386-init.h: Regenerate.
 485         * i386-opc.h (CpuMPX): New.
 486         (CpuUnused): Comment out.
 487         (i386_cpu_flags): Add cpumpx.
 488         (BNDPrefixOk): New.
 489         (i386_opcode_modifier): Add bndprefixok.
 490         (RegBND): New.
 491         (i386_operand_type): Add regbnd.
 492         * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
 493         Add MPX instructions and bnd prefix.
 494         * i386-reg.tbl: Add bnd0-bnd3 registers.
 495         * i386-tbl.h: Regenerate.
 496
 497 2013-07-17  Richard Sandiford  <rdsandiford@googlemail.com>
 498
 499         * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
 500         ATTRIBUTE_UNUSED.
 501
 502 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 503
 504         * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
 505         special rules.
 506         * Makefile.in: Regenerate.
 507         * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
 508         all fields.  Reformat.
 509
 510 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 511
 512         * mips16-opc.c: Include mips-formats.h.
 513         (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
 514         static arrays.
 515         (decode_mips16_operand): New function.
 516         * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
 517         (print_insn_arg): Handle OP_ENTRY_EXIT list.
 518         Abort for OP_SAVE_RESTORE_LIST.
 519         (print_mips16_insn_arg): Change interface.  Use mips_operand
 520         structures.  Delete GET_OP_S.  Move GET_OP definition to...
 521         (print_insn_mips16): ...here.  Call init_print_arg_state.
 522         Update the call to print_mips16_insn_arg.
 523
 524 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 525
 526         * mips-formats.h: New file.
 527         * mips-opc.c: Include mips-formats.h.
 528         (reg_0_map): New static array.
 529         (decode_mips_operand): New function.
 530         * micromips-opc.c: Remove <stdio.h> include.  Include mips-formats.h.
 531         (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
 532         (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
 533         (int_c_map): New static arrays.
 534         (decode_micromips_operand): New function.
 535         * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
 536         (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
 537         (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
 538         (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
 539         (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
 540         (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
 541         (micromips_imm_b_map, micromips_imm_c_map): Delete.
 542         (print_reg): New function.
 543         (mips_print_arg_state): New structure.
 544         (init_print_arg_state, print_insn_arg): New functions.
 545         (print_insn_args): Change interface and use mips_operand structures.
 546         Delete GET_OP_S.  Move GET_OP definition to...
 547         (print_insn_mips): ...here.  Update the call to print_insn_args.
 548         (print_insn_micromips): Use print_insn_args.
 549
 550 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 551
 552         * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
 553         in macros.
 554
 555 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 556
 557         * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
 558         ADDA.S, MULA.S and SUBA.S.
 559
 560 2013-07-08  H.J. Lu  <hongjiu.lu@intel.com>
 561
 562         PR gas/13572
 563         * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
 564         * i386-tbl.h: Regenerated.
 565
 566 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 567
 568         * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros.  Move LD
 569         and SD A(B) macros up.
 570         * micromips-opc.c (micromips_opcodes): Likewise.
 571
 572 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 573
 574         * mips16-opc.c: Add entries for argumentless "entry" and "exit"
 575         instructions.
 576
 577 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 578
 579         * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
 580         MDMX-like instructions.
 581         * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
 582         printing "Q" operands for INSN_5400 instructions.
 583
 584 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 585
 586         * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
 587         "+S" for "cins".
 588         * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
 589         Combine cases.
 590
 591 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 592
 593         * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
 594         "jalx".
 595         * mips16-opc.c (mips16_opcodes): Likewise.
 596         * micromips-opc.c (micromips_opcodes): Likewise.
 597         * mips-dis.c (print_insn_args, print_mips16_insn_arg)
 598         (print_insn_mips16): Handle "+i".
 599         (print_insn_micromips): Likewise.  Conditionally preserve the
 600         ISA bit for "a" but not for "+i".
 601
 602 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 603
 604         * micromips-opc.c (WR_mhi): Rename to..
 605         (WR_mh): ...this.
 606         (micromips_opcodes): Update "movep" entry accordingly.  Replace
 607         "mh,mi" with "mh".
 608         * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
 609         (micromips_to_32_reg_h_map1): ...this.
 610         (micromips_to_32_reg_i_map): Rename to...
 611         (micromips_to_32_reg_h_map2): ...this.
 612         (print_micromips_insn): Remove "mi" case.  Print both registers
 613         in the pair for "mh".
 614
 615 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 616
 617         * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
 618         * micromips-opc.c (micromips_opcodes): Likewise.
 619         * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
 620         and "+T" handling.  Check for a "0" suffix when deciding whether to
 621         use coprocessor 0 names.  In that case, also check for ",H" selectors.
 622
 623 2013-07-05  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 624
 625         * s390-opc.c (J12_12, J24_24): New macros.
 626         (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
 627         (MASK_MII_UPI): Rename to MASK_MII_UPP.
 628         * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
 629
 630 2013-07-04  Alan Modra  <amodra@gmail.com>
 631
 632         * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
 633
 634 2013-06-26  Nick Clifton  <nickc@redhat.com>
 635
 636         * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
 637         field when checking for type 2 nop.
 638         * rx-decode.c: Regenerate.
 639
 640 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
 641
 642         * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
 643         and "movep" macros.
 644
 645 2013-06-24  Maciej W. Rozycki  <macro@codesourcery.com>
 646
 647         * mips-dis.c (is_mips16_plt_tail): New function.
 648         (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
 649         word.
 650         (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
 651
 652 2013-06-21  DJ Delorie  <dj@redhat.com>
 653
 654         * msp430-decode.opc: New.
 655         * msp430-decode.c: New/generated.
 656         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
 657         (MAINTAINER_CLEANFILES): Likewise.
 658         Add rule to build msp430-decode.c frommsp430decode.opc
 659         using the opc2c program.
 660         * Makefile.in: Regenerate.
 661         * configure.in: Add msp430-decode.lo to msp430 architecture files.
 662         * configure: Regenerate.
 663
 664 2013-06-20  Yufeng Zhang  <yufeng.zhang@arm.com>
 665
 666         * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
 667         (SYMTAB_AVAILABLE): Removed.
 668         (#include "elf/aarch64.h): Ditto.
 669
 670 2013-06-17  Catherine Moore  <clm@codesourcery.com>
 671             Maciej W. Rozycki  <macro@codesourcery.com>
 672             Chao-Ying Fu  <fu@mips.com>
 673
 674         * micromips-opc.c (EVA): Define.
 675         (TLBINV): Define.
 676         (micromips_opcodes): Add EVA opcodes.
 677         * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
 678         (print_insn_args): Handle EVA offsets.
 679         (print_insn_micromips): Likewise.
 680         * mips-opc.c (EVA): Define.
 681         (TLBINV): Define.
 682         (mips_builtin_opcodes): Add EVA opcodes.
 683
 684 2013-06-17  Alan Modra  <amodra@gmail.com>
 685
 686         * Makefile.am (mips-opc.lo): Add rules to create automatic
 687         dependency files.  Pass archdefs.
 688         (micromips-opc.lo, mips16-opc.lo): Likewise.
 689         * Makefile.in: Regenerate.
 690
 691 2013-06-14  DJ Delorie  <dj@redhat.com>
 692
 693         * rx-decode.opc (rx_decode_opcode): Bit operations on
 694         registers are 32-bit operations, not 8-bit operations.
 695         * rx-decode.c: Regenerate.
 696
 697 2013-06-13  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 698
 699         * micromips-opc.c (IVIRT): New define.
 700         (IVIRT64): New define.
 701         (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 702         tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
 703
 704         * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
 705         dmtgc0 to print cp0 names.
 706
 707 2013-06-09  Sandra Loosemore  <sandra@codesourcery.com>
 708
 709         * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
 710         argument.
 711
 712 2013-06-08  Catherine Moore  <clm@codesourcery.com>
 713             Richard Sandiford  <rdsandiford@googlemail.com>
 714
 715         * micromips-opc.c (D32, D33, MC): Update definitions.
 716         (micromips_opcodes):  Initialize ase field.
 717         * mips-dis.c (mips_arch_choice): Add ase field.
 718         (mips_arch_choices): Initialize ase field.
 719         (set_default_mips_dis_options): Declare and setup mips_ase.
 720         * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
 721         MT32, MC): Update definitions.
 722         (mips_builtin_opcodes): Initialize ase field.
 723
 724 2013-05-24  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 725
 726         * s390-opc.txt (flogr): Require a register pair destination.
 727
 728 2013-05-23  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 729
 730         * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
 731         instruction format.
 732
 733 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 734
 735         * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
 736
 737 2013-05-20  Peter Bergner <bergner@vnet.ibm.com>
 738
 739         * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
 740         * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
 741         XLS_MASK, PPCVSX2): New defines.
 742         (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
 743         fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
 744         mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
 745         mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
 746         mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
 747         vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
 748         vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
 749         vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
 750         vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
 751         vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
 752         vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
 753         vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
 754         vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
 755         vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
 756         xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
 757         xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
 758         xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
 759         xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
 760         <lxvx, stxvx>: New extended mnemonics.
 761
 762 2013-05-17  Alan Modra  <amodra@gmail.com>
 763
 764         * ia64-raw.tbl: Replace non-ASCII char.
 765         * ia64-waw.tbl: Likewise.
 766         * ia64-asmtab.c: Regenerate.
 767
 768 2013-05-15  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 769
 770         * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
 771         * i386-init.h: Regenerated.
 772
 773 2013-05-13  Yufeng Zhang  <yufeng.zhang@arm.com>
 774
 775         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
 776         * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
 777         check from [0, 255] to [-128, 255].
 778
 779 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 780
 781         * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
 782         Add INSN_VIRT and INSN_VIRT64 to mips64r2.
 783         (parse_mips_dis_option): Handle the virt option.
 784         (print_insn_args): Handle "+J".
 785         (print_mips_disassembler_options): Print out message about virt64.
 786         * mips-opc.c (IVIRT): New define.
 787         (IVIRT64): New define.
 788         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 789         tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
 790         Move rfe to the bottom as it conflicts with tlbgp.
 791
 792 2013-05-09  Alan Modra  <amodra@gmail.com>
 793
 794         * ppc-opc.c (extract_vlesi): Properly sign extend.
 795         (extract_vlensi): Likewise.  Comment reason for setting invalid.
 796
 797 2013-05-02  Nick Clifton  <nickc@redhat.com>
 798
 799         * msp430-dis.c: Add support for MSP430X instructions.
 800
 801 2013-04-24  Sandra Loosemore  <sandra@codesourcery.com>
 802
 803         * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
 804         to "eccinj".
 805
 806 2013-04-17  Wei-chen Wang  <cole945@gmail.com>
 807
 808         PR binutils/15369
 809         * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
 810         of CGEN_CPU_ENDIAN.
 811         (hash_insns_list): Likewise.
 812
 813 2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>
 814
 815         * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
 816         warning workaround.
 817
 818 2013-04-08  Jan Beulich <jbeulich@suse.com>
 819
 820         * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
 821         * i386-tbl.h: Re-generate.
 822
 823 2013-04-06  David S. Miller  <davem@davemloft.net>
 824
 825         * sparc-dis.c (compare_opcodes): When encountering multiple aliases
 826         of an opcode, prefer the one with F_PREFERRED set.
 827         * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
 828         lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
 829         ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
 830         mark existing mnenomics as aliases.  Add "cc" suffix to edge
 831         instructions generating condition codes, mark existing mnenomics
 832         as aliases.  Add "fp" prefix to VIS compare instructions, mark
 833         existing mnenomics as aliases.
 834
 835 2013-04-03  Nick Clifton  <nickc@redhat.com>
 836
 837         * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
 838         destination address by subtracting the operand from the current
 839         address.
 840         * v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
 841         a positive value in the insn.
 842         (extract_u16_loop): Do not negate the returned value.
 843         (D16_LOOP): Add V850_INVERSE_PCREL flag.
 844
 845         (ceilf.sw): Remove duplicate entry.
 846         (cvtf.hs): New entry.
 847         (cvtf.sh): Likewise.
 848         (fmaf.s): Likewise.
 849         (fmsf.s): Likewise.
 850         (fnmaf.s): Likewise.
 851         (fnmsf.s): Likewise.
 852         (maddf.s): Restrict to E3V5 architectures.
 853         (msubf.s): Likewise.
 854         (nmaddf.s): Likewise.
 855         (nmsubf.s): Likewise.
 856
 857 2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>
 858
 859         * i386-dis.c (get_sib): Add the sizeflag argument.  Properly
 860         check address mode.
 861         (print_insn): Pass sizeflag to get_sib.
 862
 863 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 864
 865         PR binutils/15068
 866         * tic6x-dis.c: Add support for displaying 16-bit insns.
 867
 868 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 869
 870         PR gas/15095
 871         * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
 872         individual msb and lsb halves in src1 & src2 fields.  Discard the
 873         src1 (lsb) value and only use src2 (msb), discarding bit 0, to
 874         follow what Ti SDK does in that case as any value in the src1
 875         field yields the same output with SDK disassembler.
 876
 877 2013-03-12  Michael Eager <eager@eagercon.com>
 878
 879         * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
 880
 881 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 882
 883         * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
 884
 885 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 886
 887         * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
 888
 889 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 890
 891         * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
 892
 893 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 894
 895         * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
 896         (thumb32_opcodes): Likewise.
 897         (print_insn_thumb32): Handle 'S' control char.
 898
 899 2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
 900
 901         * lm32-desc.c: Regenerate.
 902
 903 2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 904
 905         * i386-reg.tbl (riz): Add RegRex64.
 906         * i386-tbl.h: Regenerated.
 907
 908 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 909
 910         * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
 911         (aarch64_feature_crc): New static.
 912         (CRC): New macro.
 913         (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
 914         crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
 915         * aarch64-asm-2.c: Re-generate.
 916         * aarch64-dis-2.c: Ditto.
 917         * aarch64-opc-2.c: Ditto.
 918
 919 2013-02-27  Alan Modra  <amodra@gmail.com>
 920
 921         * rl78-decode.opc (rl78_decode_opcode): Fix typo.
 922         * rl78-decode.c: Regenerate.
 923
 924 2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
 925
 926         * rl78-decode.opc: Fix encoding of DIVWU insn.
 927         * rl78-decode.c: Regenerate.
 928
 929 2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 930
 931         PR gas/15159
 932         * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
 933
 934         * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
 935         (cpu_flags): Add CpuSMAP.
 936
 937         * i386-opc.h (CpuSMAP): New.
 938         (i386_cpu_flags): Add cpusmap.
 939
 940         * i386-opc.tbl: Add clac and stac.
 941
 942         * i386-init.h: Regenerated.
 943         * i386-tbl.h: Likewise.
 944
 945 2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
 946
 947         * metag-dis.c: Initialize outf->bytes_per_chunk to 4
 948         which also makes the disassembler output be in little
 949         endian like it should be.
 950
 951 2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
 952
 953         * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
 954         fields to NULL.
 955         (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
 956
 957 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
 958
 959         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
 960         section disassembled.
 961
 962 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 963
 964         * arm-dis.c: Update strht pattern.
 965
 966 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
 967
 968         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
 969         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
 970         trunc.w.s macro for EE.
 971
 972 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
 973             Andrew Jenner <andrew@codesourcery.com>
 974
 975         Based on patches from Altera Corporation.
 976
 977         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
 978         nios2-opc.c.
 979         * Makefile.in: Regenerated.
 980         * configure.in: Add case for bfd_nios2_arch.
 981         * configure: Regenerated.
 982         * disassemble.c (ARCH_nios2): Define.
 983         (disassembler): Add case for bfd_arch_nios2.
 984         * nios2-dis.c: New file.
 985         * nios2-opc.c: New file.
 986
 987 2013-02-04  Alan Modra  <amodra@gmail.com>
 988
 989         * po/POTFILES.in: Regenerate.
 990         * rl78-decode.c: Regenerate.
 991         * rx-decode.c: Regenerate.
 992
 993 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
 994
 995         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
 996         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
 997         * aarch64-asm.c (convert_xtl_to_shll): New function.
 998         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 999         calling convert_xtl_to_shll.
1000         * aarch64-dis.c (convert_shll_to_xtl): New function.
1001         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1002         calling convert_shll_to_xtl.
1003         * aarch64-gen.c: Update copyright year.
1004         * aarch64-asm-2.c: Re-generate.
1005         * aarch64-dis-2.c: Re-generate.
1006         * aarch64-opc-2.c: Re-generate.
1007
1008 2013-01-24  Nick Clifton  <nickc@redhat.com>
1009
1010         * v850-dis.c: Add support for e3v5 architecture.
1011         * v850-opc.c: Likewise.
1012
1013 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
1014
1015         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
1016         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
1017         * aarch64-opc.c (operand_general_constraint_met_p): For
1018         AARCH64_MOD_LSL, move the range check on the shift amount before the
1019         alignment check; change to call set_sft_amount_out_of_range_error
1020         instead of set_imm_out_of_range_error.
1021         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
1022         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
1023         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
1024         SIMD_IMM_SFT.
1025
1026 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
1027
1028         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
1029
1030         * i386-init.h: Regenerated.
1031         * i386-tbl.h: Likewise.
1032
1033 2013-01-15  Nick Clifton  <nickc@redhat.com>
1034
1035         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
1036         values.
1037         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1038
1039 2013-01-14  Will Newton <will.newton@imgtec.com>
1040
1041         * metag-dis.c (REG_WIDTH): Increase to 64.
1042
1043 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
1044
1045         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1046         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1047         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1048         (SH6): Update.
1049         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1050         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1051         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1052         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1053
1054 2013-01-10  Will Newton <will.newton@imgtec.com>
1055
1056         * Makefile.am: Add Meta.
1057         * configure.in: Add Meta.
1058         * disassemble.c: Add Meta support.
1059         * metag-dis.c: New file.
1060         * Makefile.in: Regenerate.
1061         * configure: Regenerate.
1062
1063 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1064
1065         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1066         (match_opcode): Rename to cr16_match_opcode.
1067
1068 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
1069
1070         * mips-dis.c: Add names for CP0 registers of r5900.
1071         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1072         instructions sq and lq.
1073         Add support for MIPS r5900 CPU.
1074         Add support for 128 bit MMI (Multimedia Instructions).
1075         Add support for EE instructions (Emotion Engine).
1076         Disable unsupported floating point instructions (64 bit and
1077         undefined compare operations).
1078         Enable instructions of MIPS ISA IV which are supported by r5900.
1079         Disable 64 bit co processor instructions.
1080         Disable 64 bit multiplication and division instructions.
1081         Disable instructions for co-processor 2 and 3, because these are
1082         not supported (preparation for later VU0 support (Vector Unit)).
1083         Disable cvt.w.s because this behaves like trunc.w.s and the
1084         correct execution can't be ensured on r5900.
1085         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1086         will confuse less developers and compilers.
1087
1088 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1089
1090         * aarch64-opc.c (aarch64_print_operand): Change to print
1091         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1092         in comment.
1093         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1094         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1095         OP_MOV_IMM_WIDE.
1096
1097 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1098
1099         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1100         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
1101
1102 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
1103
1104         * i386-gen.c (process_copyright): Update copyright year to 2013.
1105
1106 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1107
1108         * cr16-dis.c (match_opcode,make_instruction): Remove static
1109         declaration.
1110         (dwordU,wordU): Moved typedefs to opcode/cr16.h
1111         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
1112
1113 For older changes see ChangeLog-2012
1114 \f
1115 Copyright (C) 2013 Free Software Foundation, Inc.
1116
1117 Copying and distribution of this file, with or without modification,
1118 are permitted in any medium without royalty provided the copyright
1119 notice and this notice are preserved.
1120
1121 Local Variables:
1122 mode: change-log
1123 left-margin: 8
1124 fill-column: 74
1125 version-control: never
1126 End: