opcodes/ChangeLog

   1 2013-10-10  Roland McGrath  <mcgrathr@google.com>
   2
   3         * v850-dis.c (v850_cacheop_codes, v850_prefop_codes):
   4         Remove duplicate const qualifier.
   5
   6 2013-10-08  Jan Beulich <jbeulich@suse.com>
   7
   8         * i386-opc.tbl (invlpg): Use Anysize instead of Unspecified.
   9         (clflush): Use Anysize instead of Byte|Unspecified.
  10         (prefetch*): Likewise.
  11         * i386-tbl.h: Re-generate.
  12
  13 2013-10-07  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
  14
  15         * micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0.
  16
  17 2013-09-30  H.J. Lu  <hongjiu.lu@intel.com>
  18
  19         * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.
  20         * i386-init.h: Regenerated.
  21
  22 2013-09-30  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
  23
  24         * i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS.
  25         * i386-init.h: Regenerated.
  26
  27 2013-09-20  Alan Modra  <amodra@gmail.com>
  28
  29         * configure: Regenerate.
  30
  31 2013-09-17  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
  32
  33         * s390-opc.txt (clih): Make the immediate unsigned.
  34
  35 2013-09-04  Roland McGrath  <mcgrathr@google.com>
  36
  37         PR gas/15914
  38         * arm-dis.c (arm_opcodes): Add udf.
  39         (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
  40         (thumb32_opcodes): Add udf.w.
  41         (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
  42
  43 2013-09-02  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  44
  45         * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
  46         For the load fp integer instructions only the suppression flag was
  47         new with z196 version.
  48
  49 2013-08-28  Nick Clifton  <nickc@redhat.com>
  50
  51         * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
  52         immediate is not suitable for the 32-bit ABI.
  53
  54 2013-08-23  Maciej W. Rozycki  <macro@codesourcery.com>
  55
  56         * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
  57         replacing NODS.
  58
  59 2013-08-23  Yuri Chornoivan  <yurchor@ukr.net>
  60
  61         PR binutils/15834
  62         * aarch64-asm.c: Fix typos.
  63         * aarch64-dis.c: Likewise.
  64         * msp430-dis.c: Likewise.
  65
  66 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
  67
  68         * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
  69         macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
  70         Use +H rather than +C for the real "dext".
  71         * mips-opc.c (mips_builtin_opcodes): Likewise.
  72
  73 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
  74
  75         * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
  76         * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
  77         and OPTIONAL_MAPPED_REG.
  78         * mips-opc.c (decode_mips_operand): Likewise.
  79         * mips16-opc.c (decode_mips16_operand): Likewise.
  80         * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
  81
  82 2013-08-19  H.J. Lu  <hongjiu.lu@intel.com>
  83
  84         * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
  85         (PREFIX_EVEX_0F3A3F): Likewise.
  86         * i386-dis-evex.h (evex_table): Updated.
  87
  88 2013-08-06  Jürgen Urban  <JuergenUrban@gmx.de>
  89
  90         * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
  91         VCLIPW.
  92
  93 2013-08-05  Eric Botcazou  <ebotcazou@adacore.com>
  94             Konrad Eisele  <konrad@gaisler.com>
  95
  96         * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
  97         bfd_mach_sparc.
  98         * sparc-opc.c (MASK_LEON): Define.
  99         (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
 100         (letandleon): New macro.
 101         (v9andleon): Likewise.
 102         (sparc_opc): Add leon.
 103         (umac): Enable for letandleon.
 104         (smac): Likewise.
 105         (casa): Enable for v9andleon.
 106         (cas): Likewise.
 107         (casl): Likewise.
 108
 109 2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
 110             Richard Sandiford  <rdsandiford@googlemail.com>
 111
 112         * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
 113         OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
 114         (print_vu0_channel): New function.
 115         (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
 116         (print_insn_args): Handle '#'.
 117         (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
 118         * mips-opc.c (mips_vu0_channel_mask): New constant.
 119         (decode_mips_operand): Handle new VU0 operand types.
 120         (VU0, VU0CH): New macros.
 121         (mips_builtin_opcodes): Add VU0 opcodes.  Use "+7" rather than "E"
 122         for LQC2 and SQC2.  Use "+9" rather than "G" for EE CFC2 and CTC2.
 123         Use "+6" rather than "G" for QMFC2 and QMTC2.
 124
 125 2013-08-03  Richard Sandiford  <rdsandiford@googlemail.com>
 126
 127         * mips-formats.h (PCREL): Reorder parameters and update the definition
 128         to match new mips_pcrel_operand layout.
 129         (JUMP, JALX, BRANCH): Update accordingly.
 130         * mips16-opc.c (decode_mips16_operand): Likewise.
 131
 132 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 133
 134         * micromips-opc.c (WR_s): Delete.
 135
 136 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 137
 138         * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
 139         New macros.
 140         (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
 141         (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
 142         (mips_builtin_opcodes): Use the new position-based read-write flags
 143         instead of field-based ones.  Use UDI for "udi..." instructions.
 144         * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
 145         New macros.
 146         (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
 147         (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
 148         (WR_SP, RD_16): New macros.
 149         (RD_SP): Redefine as an INSN2_* flag.
 150         (MOD_SP): Redefine in terms of RD_SP and WR_SP.
 151         (mips16_opcodes): Use the new position-based read-write flags
 152         instead of field-based ones.  Use RD_16 for "nop".  Move RD_SP to
 153         pinfo2 field.
 154         * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
 155         New macros.
 156         (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
 157         (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
 158         (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
 159         (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
 160         (micromips_opcodes): Use the new position-based read-write flags
 161         instead of field-based ones.
 162         * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
 163         (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
 164         of field-based flags.
 165
 166 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 167
 168         * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
 169         (WR_SP): Replace with...
 170         (MOD_SP): ...this.
 171         (mips16_opcodes): Update accordingly.
 172         * mips-dis.c (print_insn_mips16): Likewise.
 173
 174 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 175
 176         * mips16-opc.c (mips16_opcodes): Reformat.
 177
 178 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 179
 180         * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
 181         for operands that are hard-coded to $0.
 182         * micromips-opc.c (micromips_opcodes): Likewise.
 183
 184 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 185
 186         * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
 187         for the single-operand forms of JALR and JALR.HB.
 188         * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
 189         and JALRS.HB.
 190
 191 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 192
 193         * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
 194         instructions.  Fix them to use WR_MACC instead of WR_CC and
 195         add missing RD_MACCs.
 196
 197 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 198
 199         * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
 200
 201 2013-07-29  Peter Bergner <bergner@vnet.ibm.com>
 202
 203         * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
 204
 205 2013-07-26  Sergey Guriev  <sergey.s.guriev@intel.com>
 206             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 207             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 208             Sergey Lega  <sergey.s.lega@intel.com>
 209             Anna Tikhonova  <anna.tikhonova@intel.com>
 210             Ilya Tocar  <ilya.tocar@intel.com>
 211             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 212             Ilya Verbin  <ilya.verbin@intel.com>
 213             Kirill Yukhin  <kirill.yukhin@intel.com>
 214             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 215
 216         * i386-dis-evex.h: New.
 217         * i386-dis.c (OP_Rounding): New.
 218         (VPCMP_Fixup): New.
 219         (OP_Mask): New.
 220         (Rdq): New.
 221         (XMxmmq): New.
 222         (EXdScalarS): New.
 223         (EXymm): New.
 224         (EXEvexHalfBcstXmmq): New.
 225         (EXxmm_mdq): New.
 226         (EXEvexXGscat): New.
 227         (EXEvexXNoBcst): New.
 228         (VPCMP): New.
 229         (EXxEVexR): New.
 230         (EXxEVexS): New.
 231         (XMask): New.
 232         (MaskG): New.
 233         (MaskE): New.
 234         (MaskR): New.
 235         (MaskVex): New.
 236         (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
 237         evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
 238         evex_rounding_mode, evex_sae_mode, mask_mode.
 239         (USE_EVEX_TABLE): New.
 240         (EVEX_TABLE): New.
 241         (EVEX enum): New.
 242         (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
 243         REG_EVEX_0F38C7.
 244         (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
 245         MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
 246         MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
 247         MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 248         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,  MOD_EVEX_0F38C7_REG_5,
 249         MOD_EVEX_0F38C7_REG_6.
 250         (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 251         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
 252         PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 253         PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
 254         PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
 255         PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
 256         PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
 257         PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
 258         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
 259         PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
 260         PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
 261         PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
 262         PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
 263         PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
 264         PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
 265         PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
 266         PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
 267         PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
 268         PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
 269         PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
 270         PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
 271         PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
 272         PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
 273         PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
 274         PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
 275         PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
 276         PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
 277         PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
 278         PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
 279         PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
 280         PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
 281         PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
 282         PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
 283         PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
 284         PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
 285         PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
 286         PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
 287         PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
 288         PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
 289         PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
 290         PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
 291         PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
 292         PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
 293         PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
 294         PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
 295         PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
 296         PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
 297         PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
 298         PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
 299         PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
 300         PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
 301         PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
 302         PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
 303         PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
 304         PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
 305         PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
 306         PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
 307         PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
 308         PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
 309         PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
 310         PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
 311         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
 312         PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
 313         PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
 314         PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
 315         PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
 316         PREFIX_EVEX_0F3A00,  PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
 317         PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
 318         PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
 319         PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
 320         PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
 321         PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
 322         PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
 323         PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
 324         PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
 325         PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
 326         PREFIX_EVEX_0F3A55.
 327         (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
 328         VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
 329         VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
 330         VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
 331         VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
 332         VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
 333         VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
 334         VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
 335         VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
 336         VEX_W_0F3A32_P_2_LEN_0.
 337         (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
 338         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
 339         EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
 340         EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
 341         EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
 342         EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 343         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
 344         EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
 345         EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 346         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
 347         EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 348         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
 349         EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
 350         EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
 351         EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
 352         EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
 353         EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
 354         EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
 355         EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
 356         EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
 357         EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
 358         EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
 359         EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
 360         EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
 361         EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
 362         EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
 363         EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
 364         EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
 365         EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
 366         EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
 367         EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
 368         EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
 369         EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
 370         EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
 371         EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
 372         EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
 373         EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
 374         EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
 375         EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
 376         EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
 377         EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
 378         EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
 379         EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
 380         EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
 381         EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
 382         EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
 383         EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
 384         EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
 385         EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
 386         EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
 387         EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
 388         EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
 389         EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
 390         EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
 391         (struct vex): Add fields evex, r, v, mask_register_specifier,
 392         zeroing, ll, b.
 393         (intel_names_xmm): Add upper 16 registers.
 394         (att_names_xmm): Ditto.
 395         (intel_names_ymm): Ditto.
 396         (att_names_ymm): Ditto.
 397         (names_zmm): New.
 398         (intel_names_zmm): Ditto.
 399         (att_names_zmm): Ditto.
 400         (names_mask): Ditto.
 401         (intel_names_mask): Ditto.
 402         (att_names_mask): Ditto.
 403         (names_rounding): Ditto.
 404         (names_broadcast): Ditto.
 405         (x86_64_table): Add escape to evex-table.
 406         (reg_table): Include reg_table evex-entries from
 407         i386-dis-evex.h.  Fix prefetchwt1 instruction.
 408         (prefix_table): Add entries for new instructions.
 409         (vex_table): Ditto.
 410         (vex_len_table): Ditto.
 411         (vex_w_table): Ditto.
 412         (mod_table): Ditto.
 413         (get_valid_dis386): Properly handle new instructions.
 414         (print_insn): Handle zmm and mask registers, print mask operand.
 415         (intel_operand_size): Support EVEX, new modes and sizes.
 416         (OP_E_register): Handle new modes.
 417         (OP_E_memory): Ditto.
 418         (OP_G): Ditto.
 419         (OP_XMM): Ditto.
 420         (OP_EX): Ditto.
 421         (OP_VEX): Ditto.
 422         * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
 423         CPU_ANY_AVX_FLAGS.  Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
 424         CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 425         (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
 426         CpuAVX512PF and CpuVREX.
 427         (operand_type_init): Add OPERAND_TYPE_REGZMM,
 428         OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
 429         (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
 430         StaticRounding, SAE, Disp8MemShift, NoDefMask.
 431         (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
 432         * i386-init.h: Regenerate.
 433         * i386-opc.h (CpuAVX512F): New.
 434         (CpuAVX512CD): New.
 435         (CpuAVX512ER): New.
 436         (CpuAVX512PF): New.
 437         (CpuVREX): New.
 438         (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
 439         cpuavx512pf and cpuvrex fields.
 440         (VecSIB): Add VecSIB512.
 441         (EVex): New.
 442         (Masking): New.
 443         (VecESize): New.
 444         (Broadcast): New.
 445         (StaticRounding): New.
 446         (SAE): New.
 447         (Disp8MemShift): New.
 448         (NoDefMask): New.
 449         (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
 450         staticrounding, sae, disp8memshift and nodefmask.
 451         (RegZMM): New.
 452         (Zmmword): Ditto.
 453         (Vec_Disp8): Ditto.
 454         (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
 455         fields.
 456         (RegVRex): New.
 457         * i386-opc.tbl: Add AVX512 instructions.
 458         * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
 459         registers, mask registers.
 460         * i386-tbl.h: Regenerate.
 461
 462 2013-07-25  Aaro Koskinen  <aaro.koskinen@iki.fi>
 463
 464         PR gas/15220
 465         * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
 466         Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
 467
 468 2013-07-25  Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 469
 470         * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
 471         PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
 472         PREFIX_0F3ACC.
 473         (prefix_table): Updated.
 474         (three_byte_table): Likewise.
 475         * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
 476         (cpu_flags): Add CpuSHA.
 477         (i386_cpu_flags): Add cpusha.
 478         * i386-init.h: Regenerate.
 479         * i386-opc.h (CpuSHA): New.
 480         (CpuUnused): Restored.
 481         (i386_cpu_flags): Add cpusha.
 482         * i386-opc.tbl: Add SHA instructions.
 483         * i386-tbl.h: Regenerate.
 484
 485 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
 486             Kirill Yukhin  <kirill.yukhin@intel.com>
 487             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 488
 489         * i386-dis.c (BND_Fixup): New.
 490         (Ebnd): New.
 491         (Ev_bnd): New.
 492         (Gbnd): New.
 493         (BND): New.
 494         (v_bnd_mode): New.
 495         (bnd_mode): New.
 496         (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
 497         MOD_0F1B_PREFIX_1.
 498         (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
 499         (dis tables): Replace XX with BND for near branch and call
 500         instructions.
 501         (prefix_table): Add new entries.
 502         (mod_table): Likewise.
 503         (names_bnd): New.
 504         (intel_names_bnd): New.
 505         (att_names_bnd): New.
 506         (BND_PREFIX): New.
 507         (prefix_name): Handle BND_PREFIX.
 508         (print_insn): Initialize names_bnd.
 509         (intel_operand_size): Handle new modes.
 510         (OP_E_register): Likewise.
 511         (OP_E_memory): Likewise.
 512         (OP_G): Likewise.
 513         * i386-gen.c (cpu_flag_init): Add CpuMPX.
 514         (cpu_flags): Add CpuMPX.
 515         (operand_type_init): Add RegBND.
 516         (opcode_modifiers): Add BNDPrefixOk.
 517         (operand_types): Add RegBND.
 518         * i386-init.h: Regenerate.
 519         * i386-opc.h (CpuMPX): New.
 520         (CpuUnused): Comment out.
 521         (i386_cpu_flags): Add cpumpx.
 522         (BNDPrefixOk): New.
 523         (i386_opcode_modifier): Add bndprefixok.
 524         (RegBND): New.
 525         (i386_operand_type): Add regbnd.
 526         * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
 527         Add MPX instructions and bnd prefix.
 528         * i386-reg.tbl: Add bnd0-bnd3 registers.
 529         * i386-tbl.h: Regenerate.
 530
 531 2013-07-17  Richard Sandiford  <rdsandiford@googlemail.com>
 532
 533         * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
 534         ATTRIBUTE_UNUSED.
 535
 536 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 537
 538         * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
 539         special rules.
 540         * Makefile.in: Regenerate.
 541         * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
 542         all fields.  Reformat.
 543
 544 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 545
 546         * mips16-opc.c: Include mips-formats.h.
 547         (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
 548         static arrays.
 549         (decode_mips16_operand): New function.
 550         * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
 551         (print_insn_arg): Handle OP_ENTRY_EXIT list.
 552         Abort for OP_SAVE_RESTORE_LIST.
 553         (print_mips16_insn_arg): Change interface.  Use mips_operand
 554         structures.  Delete GET_OP_S.  Move GET_OP definition to...
 555         (print_insn_mips16): ...here.  Call init_print_arg_state.
 556         Update the call to print_mips16_insn_arg.
 557
 558 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 559
 560         * mips-formats.h: New file.
 561         * mips-opc.c: Include mips-formats.h.
 562         (reg_0_map): New static array.
 563         (decode_mips_operand): New function.
 564         * micromips-opc.c: Remove <stdio.h> include.  Include mips-formats.h.
 565         (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
 566         (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
 567         (int_c_map): New static arrays.
 568         (decode_micromips_operand): New function.
 569         * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
 570         (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
 571         (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
 572         (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
 573         (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
 574         (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
 575         (micromips_imm_b_map, micromips_imm_c_map): Delete.
 576         (print_reg): New function.
 577         (mips_print_arg_state): New structure.
 578         (init_print_arg_state, print_insn_arg): New functions.
 579         (print_insn_args): Change interface and use mips_operand structures.
 580         Delete GET_OP_S.  Move GET_OP definition to...
 581         (print_insn_mips): ...here.  Update the call to print_insn_args.
 582         (print_insn_micromips): Use print_insn_args.
 583
 584 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 585
 586         * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
 587         in macros.
 588
 589 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 590
 591         * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
 592         ADDA.S, MULA.S and SUBA.S.
 593
 594 2013-07-08  H.J. Lu  <hongjiu.lu@intel.com>
 595
 596         PR gas/13572
 597         * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
 598         * i386-tbl.h: Regenerated.
 599
 600 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 601
 602         * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros.  Move LD
 603         and SD A(B) macros up.
 604         * micromips-opc.c (micromips_opcodes): Likewise.
 605
 606 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 607
 608         * mips16-opc.c: Add entries for argumentless "entry" and "exit"
 609         instructions.
 610
 611 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 612
 613         * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
 614         MDMX-like instructions.
 615         * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
 616         printing "Q" operands for INSN_5400 instructions.
 617
 618 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 619
 620         * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
 621         "+S" for "cins".
 622         * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
 623         Combine cases.
 624
 625 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 626
 627         * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
 628         "jalx".
 629         * mips16-opc.c (mips16_opcodes): Likewise.
 630         * micromips-opc.c (micromips_opcodes): Likewise.
 631         * mips-dis.c (print_insn_args, print_mips16_insn_arg)
 632         (print_insn_mips16): Handle "+i".
 633         (print_insn_micromips): Likewise.  Conditionally preserve the
 634         ISA bit for "a" but not for "+i".
 635
 636 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 637
 638         * micromips-opc.c (WR_mhi): Rename to..
 639         (WR_mh): ...this.
 640         (micromips_opcodes): Update "movep" entry accordingly.  Replace
 641         "mh,mi" with "mh".
 642         * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
 643         (micromips_to_32_reg_h_map1): ...this.
 644         (micromips_to_32_reg_i_map): Rename to...
 645         (micromips_to_32_reg_h_map2): ...this.
 646         (print_micromips_insn): Remove "mi" case.  Print both registers
 647         in the pair for "mh".
 648
 649 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 650
 651         * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
 652         * micromips-opc.c (micromips_opcodes): Likewise.
 653         * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
 654         and "+T" handling.  Check for a "0" suffix when deciding whether to
 655         use coprocessor 0 names.  In that case, also check for ",H" selectors.
 656
 657 2013-07-05  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 658
 659         * s390-opc.c (J12_12, J24_24): New macros.
 660         (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
 661         (MASK_MII_UPI): Rename to MASK_MII_UPP.
 662         * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
 663
 664 2013-07-04  Alan Modra  <amodra@gmail.com>
 665
 666         * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
 667
 668 2013-06-26  Nick Clifton  <nickc@redhat.com>
 669
 670         * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
 671         field when checking for type 2 nop.
 672         * rx-decode.c: Regenerate.
 673
 674 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
 675
 676         * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
 677         and "movep" macros.
 678
 679 2013-06-24  Maciej W. Rozycki  <macro@codesourcery.com>
 680
 681         * mips-dis.c (is_mips16_plt_tail): New function.
 682         (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
 683         word.
 684         (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
 685
 686 2013-06-21  DJ Delorie  <dj@redhat.com>
 687
 688         * msp430-decode.opc: New.
 689         * msp430-decode.c: New/generated.
 690         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
 691         (MAINTAINER_CLEANFILES): Likewise.
 692         Add rule to build msp430-decode.c frommsp430decode.opc
 693         using the opc2c program.
 694         * Makefile.in: Regenerate.
 695         * configure.in: Add msp430-decode.lo to msp430 architecture files.
 696         * configure: Regenerate.
 697
 698 2013-06-20  Yufeng Zhang  <yufeng.zhang@arm.com>
 699
 700         * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
 701         (SYMTAB_AVAILABLE): Removed.
 702         (#include "elf/aarch64.h): Ditto.
 703
 704 2013-06-17  Catherine Moore  <clm@codesourcery.com>
 705             Maciej W. Rozycki  <macro@codesourcery.com>
 706             Chao-Ying Fu  <fu@mips.com>
 707
 708         * micromips-opc.c (EVA): Define.
 709         (TLBINV): Define.
 710         (micromips_opcodes): Add EVA opcodes.
 711         * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
 712         (print_insn_args): Handle EVA offsets.
 713         (print_insn_micromips): Likewise.
 714         * mips-opc.c (EVA): Define.
 715         (TLBINV): Define.
 716         (mips_builtin_opcodes): Add EVA opcodes.
 717
 718 2013-06-17  Alan Modra  <amodra@gmail.com>
 719
 720         * Makefile.am (mips-opc.lo): Add rules to create automatic
 721         dependency files.  Pass archdefs.
 722         (micromips-opc.lo, mips16-opc.lo): Likewise.
 723         * Makefile.in: Regenerate.
 724
 725 2013-06-14  DJ Delorie  <dj@redhat.com>
 726
 727         * rx-decode.opc (rx_decode_opcode): Bit operations on
 728         registers are 32-bit operations, not 8-bit operations.
 729         * rx-decode.c: Regenerate.
 730
 731 2013-06-13  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 732
 733         * micromips-opc.c (IVIRT): New define.
 734         (IVIRT64): New define.
 735         (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 736         tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
 737
 738         * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
 739         dmtgc0 to print cp0 names.
 740
 741 2013-06-09  Sandra Loosemore  <sandra@codesourcery.com>
 742
 743         * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
 744         argument.
 745
 746 2013-06-08  Catherine Moore  <clm@codesourcery.com>
 747             Richard Sandiford  <rdsandiford@googlemail.com>
 748
 749         * micromips-opc.c (D32, D33, MC): Update definitions.
 750         (micromips_opcodes):  Initialize ase field.
 751         * mips-dis.c (mips_arch_choice): Add ase field.
 752         (mips_arch_choices): Initialize ase field.
 753         (set_default_mips_dis_options): Declare and setup mips_ase.
 754         * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
 755         MT32, MC): Update definitions.
 756         (mips_builtin_opcodes): Initialize ase field.
 757
 758 2013-05-24  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 759
 760         * s390-opc.txt (flogr): Require a register pair destination.
 761
 762 2013-05-23  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 763
 764         * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
 765         instruction format.
 766
 767 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 768
 769         * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
 770
 771 2013-05-20  Peter Bergner <bergner@vnet.ibm.com>
 772
 773         * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
 774         * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
 775         XLS_MASK, PPCVSX2): New defines.
 776         (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
 777         fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
 778         mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
 779         mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
 780         mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
 781         vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
 782         vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
 783         vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
 784         vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
 785         vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
 786         vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
 787         vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
 788         vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
 789         vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
 790         xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
 791         xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
 792         xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
 793         xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
 794         <lxvx, stxvx>: New extended mnemonics.
 795
 796 2013-05-17  Alan Modra  <amodra@gmail.com>
 797
 798         * ia64-raw.tbl: Replace non-ASCII char.
 799         * ia64-waw.tbl: Likewise.
 800         * ia64-asmtab.c: Regenerate.
 801
 802 2013-05-15  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 803
 804         * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
 805         * i386-init.h: Regenerated.
 806
 807 2013-05-13  Yufeng Zhang  <yufeng.zhang@arm.com>
 808
 809         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
 810         * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
 811         check from [0, 255] to [-128, 255].
 812
 813 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 814
 815         * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
 816         Add INSN_VIRT and INSN_VIRT64 to mips64r2.
 817         (parse_mips_dis_option): Handle the virt option.
 818         (print_insn_args): Handle "+J".
 819         (print_mips_disassembler_options): Print out message about virt64.
 820         * mips-opc.c (IVIRT): New define.
 821         (IVIRT64): New define.
 822         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 823         tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
 824         Move rfe to the bottom as it conflicts with tlbgp.
 825
 826 2013-05-09  Alan Modra  <amodra@gmail.com>
 827
 828         * ppc-opc.c (extract_vlesi): Properly sign extend.
 829         (extract_vlensi): Likewise.  Comment reason for setting invalid.
 830
 831 2013-05-02  Nick Clifton  <nickc@redhat.com>
 832
 833         * msp430-dis.c: Add support for MSP430X instructions.
 834
 835 2013-04-24  Sandra Loosemore  <sandra@codesourcery.com>
 836
 837         * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
 838         to "eccinj".
 839
 840 2013-04-17  Wei-chen Wang  <cole945@gmail.com>
 841
 842         PR binutils/15369
 843         * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
 844         of CGEN_CPU_ENDIAN.
 845         (hash_insns_list): Likewise.
 846
 847 2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>
 848
 849         * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
 850         warning workaround.
 851
 852 2013-04-08  Jan Beulich <jbeulich@suse.com>
 853
 854         * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
 855         * i386-tbl.h: Re-generate.
 856
 857 2013-04-06  David S. Miller  <davem@davemloft.net>
 858
 859         * sparc-dis.c (compare_opcodes): When encountering multiple aliases
 860         of an opcode, prefer the one with F_PREFERRED set.
 861         * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
 862         lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
 863         ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
 864         mark existing mnenomics as aliases.  Add "cc" suffix to edge
 865         instructions generating condition codes, mark existing mnenomics
 866         as aliases.  Add "fp" prefix to VIS compare instructions, mark
 867         existing mnenomics as aliases.
 868
 869 2013-04-03  Nick Clifton  <nickc@redhat.com>
 870
 871         * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
 872         destination address by subtracting the operand from the current
 873         address.
 874         * v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
 875         a positive value in the insn.
 876         (extract_u16_loop): Do not negate the returned value.
 877         (D16_LOOP): Add V850_INVERSE_PCREL flag.
 878
 879         (ceilf.sw): Remove duplicate entry.
 880         (cvtf.hs): New entry.
 881         (cvtf.sh): Likewise.
 882         (fmaf.s): Likewise.
 883         (fmsf.s): Likewise.
 884         (fnmaf.s): Likewise.
 885         (fnmsf.s): Likewise.
 886         (maddf.s): Restrict to E3V5 architectures.
 887         (msubf.s): Likewise.
 888         (nmaddf.s): Likewise.
 889         (nmsubf.s): Likewise.
 890
 891 2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>
 892
 893         * i386-dis.c (get_sib): Add the sizeflag argument.  Properly
 894         check address mode.
 895         (print_insn): Pass sizeflag to get_sib.
 896
 897 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 898
 899         PR binutils/15068
 900         * tic6x-dis.c: Add support for displaying 16-bit insns.
 901
 902 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 903
 904         PR gas/15095
 905         * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
 906         individual msb and lsb halves in src1 & src2 fields.  Discard the
 907         src1 (lsb) value and only use src2 (msb), discarding bit 0, to
 908         follow what Ti SDK does in that case as any value in the src1
 909         field yields the same output with SDK disassembler.
 910
 911 2013-03-12  Michael Eager <eager@eagercon.com>
 912
 913         * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
 914
 915 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 916
 917         * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
 918
 919 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 920
 921         * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
 922
 923 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 924
 925         * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
 926
 927 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 928
 929         * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
 930         (thumb32_opcodes): Likewise.
 931         (print_insn_thumb32): Handle 'S' control char.
 932
 933 2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
 934
 935         * lm32-desc.c: Regenerate.
 936
 937 2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 938
 939         * i386-reg.tbl (riz): Add RegRex64.
 940         * i386-tbl.h: Regenerated.
 941
 942 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 943
 944         * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
 945         (aarch64_feature_crc): New static.
 946         (CRC): New macro.
 947         (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
 948         crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
 949         * aarch64-asm-2.c: Re-generate.
 950         * aarch64-dis-2.c: Ditto.
 951         * aarch64-opc-2.c: Ditto.
 952
 953 2013-02-27  Alan Modra  <amodra@gmail.com>
 954
 955         * rl78-decode.opc (rl78_decode_opcode): Fix typo.
 956         * rl78-decode.c: Regenerate.
 957
 958 2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
 959
 960         * rl78-decode.opc: Fix encoding of DIVWU insn.
 961         * rl78-decode.c: Regenerate.
 962
 963 2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 964
 965         PR gas/15159
 966         * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
 967
 968         * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
 969         (cpu_flags): Add CpuSMAP.
 970
 971         * i386-opc.h (CpuSMAP): New.
 972         (i386_cpu_flags): Add cpusmap.
 973
 974         * i386-opc.tbl: Add clac and stac.
 975
 976         * i386-init.h: Regenerated.
 977         * i386-tbl.h: Likewise.
 978
 979 2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
 980
 981         * metag-dis.c: Initialize outf->bytes_per_chunk to 4
 982         which also makes the disassembler output be in little
 983         endian like it should be.
 984
 985 2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
 986
 987         * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
 988         fields to NULL.
 989         (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
 990
 991 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
 992
 993         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
 994         section disassembled.
 995
 996 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 997
 998         * arm-dis.c: Update strht pattern.
 999
1000 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
1001
1002         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
1003         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
1004         trunc.w.s macro for EE.
1005
1006 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
1007             Andrew Jenner <andrew@codesourcery.com>
1008
1009         Based on patches from Altera Corporation.
1010
1011         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
1012         nios2-opc.c.
1013         * Makefile.in: Regenerated.
1014         * configure.in: Add case for bfd_nios2_arch.
1015         * configure: Regenerated.
1016         * disassemble.c (ARCH_nios2): Define.
1017         (disassembler): Add case for bfd_arch_nios2.
1018         * nios2-dis.c: New file.
1019         * nios2-opc.c: New file.
1020
1021 2013-02-04  Alan Modra  <amodra@gmail.com>
1022
1023         * po/POTFILES.in: Regenerate.
1024         * rl78-decode.c: Regenerate.
1025         * rx-decode.c: Regenerate.
1026
1027 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
1028
1029         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
1030         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
1031         * aarch64-asm.c (convert_xtl_to_shll): New function.
1032         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1033         calling convert_xtl_to_shll.
1034         * aarch64-dis.c (convert_shll_to_xtl): New function.
1035         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1036         calling convert_shll_to_xtl.
1037         * aarch64-gen.c: Update copyright year.
1038         * aarch64-asm-2.c: Re-generate.
1039         * aarch64-dis-2.c: Re-generate.
1040         * aarch64-opc-2.c: Re-generate.
1041
1042 2013-01-24  Nick Clifton  <nickc@redhat.com>
1043
1044         * v850-dis.c: Add support for e3v5 architecture.
1045         * v850-opc.c: Likewise.
1046
1047 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
1048
1049         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
1050         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
1051         * aarch64-opc.c (operand_general_constraint_met_p): For
1052         AARCH64_MOD_LSL, move the range check on the shift amount before the
1053         alignment check; change to call set_sft_amount_out_of_range_error
1054         instead of set_imm_out_of_range_error.
1055         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
1056         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
1057         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
1058         SIMD_IMM_SFT.
1059
1060 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
1061
1062         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
1063
1064         * i386-init.h: Regenerated.
1065         * i386-tbl.h: Likewise.
1066
1067 2013-01-15  Nick Clifton  <nickc@redhat.com>
1068
1069         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
1070         values.
1071         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1072
1073 2013-01-14  Will Newton <will.newton@imgtec.com>
1074
1075         * metag-dis.c (REG_WIDTH): Increase to 64.
1076
1077 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
1078
1079         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1080         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1081         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1082         (SH6): Update.
1083         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1084         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1085         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1086         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1087
1088 2013-01-10  Will Newton <will.newton@imgtec.com>
1089
1090         * Makefile.am: Add Meta.
1091         * configure.in: Add Meta.
1092         * disassemble.c: Add Meta support.
1093         * metag-dis.c: New file.
1094         * Makefile.in: Regenerate.
1095         * configure: Regenerate.
1096
1097 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1098
1099         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1100         (match_opcode): Rename to cr16_match_opcode.
1101
1102 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
1103
1104         * mips-dis.c: Add names for CP0 registers of r5900.
1105         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1106         instructions sq and lq.
1107         Add support for MIPS r5900 CPU.
1108         Add support for 128 bit MMI (Multimedia Instructions).
1109         Add support for EE instructions (Emotion Engine).
1110         Disable unsupported floating point instructions (64 bit and
1111         undefined compare operations).
1112         Enable instructions of MIPS ISA IV which are supported by r5900.
1113         Disable 64 bit co processor instructions.
1114         Disable 64 bit multiplication and division instructions.
1115         Disable instructions for co-processor 2 and 3, because these are
1116         not supported (preparation for later VU0 support (Vector Unit)).
1117         Disable cvt.w.s because this behaves like trunc.w.s and the
1118         correct execution can't be ensured on r5900.
1119         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1120         will confuse less developers and compilers.
1121
1122 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1123
1124         * aarch64-opc.c (aarch64_print_operand): Change to print
1125         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1126         in comment.
1127         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1128         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1129         OP_MOV_IMM_WIDE.
1130
1131 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1132
1133         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1134         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
1135
1136 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
1137
1138         * i386-gen.c (process_copyright): Update copyright year to 2013.
1139
1140 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1141
1142         * cr16-dis.c (match_opcode,make_instruction): Remove static
1143         declaration.
1144         (dwordU,wordU): Moved typedefs to opcode/cr16.h
1145         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
1146
1147 For older changes see ChangeLog-2012
1148 \f
1149 Copyright (C) 2013 Free Software Foundation, Inc.
1150
1151 Copying and distribution of this file, with or without modification,
1152 are permitted in any medium without royalty provided the copyright
1153 notice and this notice are preserved.
1154
1155 Local Variables:
1156 mode: change-log
1157 left-margin: 8
1158 fill-column: 74
1159 version-control: never
1160 End: