opcodes/ChangeLog

   1 2021-11-25  Nick Clifton  <nickc@redhat.com>
   2
   3         * po/fr.po; Updated French translation.
   4
   5 2021-10-27  Maciej W. Rozycki  <macro@embecosm.com>
   6
   7         * Makefile.am: Remove obsolete comment.
   8         * configure.ac: Refer `libbfd.la' to link shared BFD library
   9         except for Cygwin.
  10         * Makefile.in: Regenerate.
  11         * configure: Regenerate.
  12
  13 2021-09-27  Nick Alcock  <nick.alcock@oracle.com>
  14
  15         * configure: Regenerate.
  16
  17 2021-09-25  Peter Bergner  <bergner@linux.ibm.com>
  18
  19         * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
  20         on POWER5 and later.
  21
  22 2021-09-20  Andrew Burgess  <andrew.burgess@embecosm.com>
  23
  24         * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
  25         before an unknown instruction, '%d' is replaced with the
  26         instruction length.
  27
  28 2021-09-02  Nick Clifton  <nickc@redhat.com>
  29
  30         PR 28292
  31         * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
  32         of BFD_RELOC_16.
  33
  34 2021-08-17  Shahab Vahedi <shahab@synopsys.com>
  35
  36         * arc-regs.h (DEF): Fix the register numbers.
  37
  38 2021-08-10  Nick Clifton  <nickc@redhat.com>
  39
  40         * po/sr.po: Updated Serbian translation.
  41
  42 2021-07-26  Chenghua Xu  <xuchenghua@loongson.cn>
  43
  44         * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
  45
  46 2021-06-07  Andreas Krebbel  <krebbel@linux.ibm.com>
  47
  48         * s390-opc.txt: Add qpaci.
  49
  50 2021-07-03  Nick Clifton  <nickc@redhat.com>
  51
  52         * configure: Regenerate.
  53         * po/opcodes.pot: Regenerate.
  54
  55 2021-07-03  Nick Clifton  <nickc@redhat.com>
  56
  57         * 2.37 release branch created.
  58
  59 2021-07-02  Alan Modra  <amodra@gmail.com>
  60
  61         * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
  62         (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
  63         (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
  64         (nds32_opcodes, nds32_operand_fields, nds32_keywords),
  65         (nds32_keyword_gpr): Move declarations to..
  66         * nds32-asm.h: ..here, constifying to match definitions.
  67
  68 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  69
  70         * Makefile.am (GUILE): New variable.
  71         (CGEN): Use $(GUILE).
  72         * Makefile.in: Regenerate.
  73
  74 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  75
  76         * mep-asm.c (macros): Mark static & const.
  77         (lookup_macro): Change return & m to const.
  78         (expand_macro): Change mac to const.
  79         (expand_string): Change pmacro to const.
  80
  81 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  82
  83         * nds32-asm.c (operand_fields): Rename to ...
  84         (nds32_operand_fields): ... this.
  85         (keyword_gpr): Rename to ...
  86         (nds32_keyword_gpr): ... this.
  87         (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
  88         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
  89         keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
  90         keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
  91         keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
  92         Mark static.
  93         (keywords): Rename to ...
  94         (nds32_keywords): ... this.
  95         * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
  96         keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
  97
  98 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  99
 100         * z80-dis.c (opc_ed): Make const.
 101         (pref_ed): Make p const.
 102
 103 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 104
 105         * microblaze-dis.c (get_field_special): Make op const.
 106         (read_insn_microblaze): Make opr & op const.  Rename opcodes to
 107         microblaze_opcodes.
 108         (print_insn_microblaze): Make op & pop const.
 109         (get_insn_microblaze): Make op const.  Rename opcodes to
 110         microblaze_opcodes.
 111         (microblaze_get_target_address): Likewise.
 112         * microblaze-opc.h (struct op_code_struct): Make const.
 113         Rename opcodes to microblaze_opcodes.
 114
 115 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 116
 117         * aarch64-gen.c (aarch64_opcode_table): Add const.
 118         * aarch64-tbl.h (aarch64_opcode_table): Likewise.
 119
 120 2021-06-22  Andrew Burgess  <andrew.burgess@embecosm.com>
 121
 122         * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
 123         available.
 124
 125 2021-06-22  Alan Modra  <amodra@gmail.com>
 126
 127         * pj-dis.c (print_insn_pj): Don't print trailing tab.  Do
 128         print separator for pcrel insns.
 129
 130 2021-06-19  Alan Modra  <amodra@gmail.com>
 131
 132         * vax-dis.c (print_insn_vax): Avoid pointer overflow.
 133
 134 2021-06-19  Alan Modra  <amodra@gmail.com>
 135
 136         * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
 137         entire buffer.
 138
 139 2021-06-17  Alan Modra  <amodra@gmail.com>
 140
 141         * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
 142         in table.
 143
 144 2021-06-03  Alan Modra  <amodra@gmail.com>
 145
 146         PR 1202
 147         * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
 148         Use unsigned int for inst.
 149
 150 2021-06-02  Shahab Vahedi  <shahab@synopsys.com>
 151
 152         * arc-dis.c (arc_option_arg_t): New enumeration.
 153         (arc_options): New variable.
 154         (disassembler_options_arc): New function.
 155         (print_arc_disassembler_options): Reimplement in terms of
 156         "disassembler_options_arc".
 157
 158 2021-05-29  Alan Modra  <amodra@gmail.com>
 159
 160         * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
 161         Don't special case PPC_OPCODE_RAW.
 162         (lookup_prefix): Likewise.
 163         (lookup_vle, lookup_spe2): Similarly.  Add dialect parameter and..
 164         (print_insn_powerpc): ..update caller.
 165         * ppc-opc.c (EXT): Define.
 166         (powerpc_opcodes): Mark extended mnemonics with EXT.
 167         (prefix_opcodes, vle_opcodes): Likewise.
 168         (XISEL, XISEL_MASK): Add cr field and simplify.
 169         (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
 170         all isel variants to where the base mnemonic belongs.  Sort dstt,
 171         dststt and dssall.
 172
 173 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 174
 175         * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
 176         COP3 opcode instructions.
 177
 178 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 179
 180         * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
 181         "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
 182         "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
 183         "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
 184         "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
 185         "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
 186         "cop2", and "cop3" entries.
 187
 188 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 189
 190         * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
 191         entries and associated comments.
 192
 193 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 194
 195         * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
 196         of "c0".
 197
 198 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 199
 200         * mips-dis.c (mips_cp1_names_mips): New variable.
 201         (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
 202         for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
 203         "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
 204         "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
 205         "r12000", "r14000", "r16000", "mips5", "loongson2e", and
 206         "loongson2f".
 207
 208 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 209
 210         * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
 211         handling code over to...
 212         <OP_REG_CONTROL>: ... this new case.
 213         * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
 214         (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
 215         "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
 216         replacing the `G' operand code with `g'.  Update "cftc1" and
 217         "cftc2" entries replacing the `E' operand code with `y'.
 218         * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
 219         (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
 220         entries replacing the `G' operand code with `g'.
 221
 222 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 223
 224         * mips-dis.c (mips_cp0_names_r3900): New variable.
 225         (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
 226         for "r3900".
 227
 228 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 229
 230         * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
 231         and "mtthc2" to using the `G' rather than `g' operand code for
 232         the coprocessor control register referred.
 233
 234 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 235
 236         * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
 237         entries with each other.
 238
 239 2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
 240
 241         * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
 242
 243 2021-05-25  Alan Modra  <amodra@gmail.com>
 244
 245         * cris-desc.c: Regenerate.
 246         * cris-desc.h: Regenerate.
 247         * cris-opc.h: Regenerate.
 248         * po/POTFILES.in: Regenerate.
 249
 250 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
 251
 252         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
 253         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
 254         (CGEN_CPUS): Add cris.
 255         (CRIS_DEPS): Define.
 256         (stamp-cris): New rule.
 257         * cgen.sh: Handle desc action.
 258         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
 259         * Makefile.in, configure: Regenerate.
 260
 261 2021-05-18  Job Noorman  <mtvec@pm.me>
 262
 263         PR 27814
 264         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
 265         the elf objects.
 266
 267 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
 268
 269         * arm-dis.c (mve_opcodes): Fix disassembly of
 270         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
 271         (is_mve_encoding_conflict): MVE vector loads should not match
 272         when P = W = 0.
 273         (is_mve_unpredictable): It's not unpredictable to use the same
 274         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
 275
 276 2021-05-11  Nick Clifton  <nickc@redhat.com>
 277
 278         PR 27840
 279         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
 280         the end of the code buffer.
 281
 282 2021-05-06  Stafford Horne  <shorne@gmail.com>
 283
 284         PR 21464
 285         * or1k-asm.c: Regenerate.
 286
 287 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
 288
 289         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
 290         info->insn_info_valid.
 291
 292 2021-04-26  Jan Beulich  <jbeulich@suse.com>
 293
 294         * i386-opc.tbl (lea): Add Optimize.
 295         * opcodes/i386-tbl.h: Re-generate.
 296
 297 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 298
 299         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
 300         of l32r fetch and display referenced literal value.
 301
 302 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 303
 304         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
 305         to 4 for literal disassembly.
 306
 307 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 308
 309         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
 310         for TLBI instruction.
 311
 312 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 313
 314         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
 315         DC instruction.
 316
 317 2021-04-19  Jan Beulich  <jbeulich@suse.com>
 318
 319         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
 320         "qualifier".
 321         (convert_mov_to_movewide): Add initializer for "value".
 322
 323 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 324
 325         * aarch64-opc.c: Add RME system registers.
 326
 327 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
 328
 329         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
 330         "addi d,CV,z" to "c.mv d,CV".
 331
 332 2021-04-12  Alan Modra  <amodra@gmail.com>
 333
 334         * configure.ac (--enable-checking): Add support.
 335         * config.in: Regenerate.
 336         * configure: Regenerate.
 337
 338 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
 339
 340         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
 341         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 342
 343 2021-04-09  Alan Modra  <amodra@gmail.com>
 344
 345         * ppc-dis.c (struct dis_private): Add "special".
 346         (POWERPC_DIALECT): Delete.  Replace uses with..
 347         (private_data): ..this.  New inline function.
 348         (disassemble_init_powerpc): Init "special" names.
 349         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 350         field of prefix instructions.
 351         (bsearch_reloc, print_got_plt): New functions.
 352         (print_insn_powerpc): For pcrel instructions, print target address
 353         and symbol if known, and decode plt and got loads too.
 354
 355 2021-04-08  Alan Modra  <amodra@gmail.com>
 356
 357         PR 27684
 358         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 359
 360 2021-04-08  Alan Modra  <amodra@gmail.com>
 361
 362         PR 27676
 363         * ppc-opc.c (DCBT_EO): Move earlier.
 364         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 365         (powerpc_operands): Add THCT and THDS entries.
 366         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 367
 368 2021-04-06  Alan Modra  <amodra@gmail.com>
 369
 370         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 371         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 372         symbol_at_address_func.
 373
 374 2021-04-05  Alan Modra  <amodra@gmail.com>
 375
 376         * configure.ac: Don't check for limits.h, string.h, strings.h or
 377         stdlib.h.
 378         (AC_ISC_POSIX): Don't invoke.
 379         * sysdep.h: Include stdlib.h and string.h unconditionally.
 380         * i386-opc.h: Include limits.h unconditionally.
 381         * wasm32-dis.c: Likewise.
 382         * cgen-opc.c: Don't include alloca-conf.h.
 383         * config.in: Regenerate.
 384         * configure: Regenerate.
 385
 386 2021-04-01  Martin Liska  <mliska@suse.cz>
 387
 388         * arm-dis.c (strneq): Remove strneq and use startswith.
 389         * cr16-dis.c (print_insn_cr16): Likewise.
 390         * score-dis.c (streq): Likewise.
 391         (strneq): Likewise.
 392         * score7-dis.c (strneq): Likewise.
 393
 394 2021-04-01  Alan Modra  <amodra@gmail.com>
 395
 396         PR 27675
 397         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 398
 399 2021-03-31  Alan Modra  <amodra@gmail.com>
 400
 401         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 402         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 403         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 404         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 405         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 406         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 407         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 408         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 409         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 410         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 411         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 412         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 413         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 414         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 415         and TRUE with true throughout.
 416
 417 2021-03-31  Alan Modra  <amodra@gmail.com>
 418
 419         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 420         * aarch64-dis.h: Likewise.
 421         * aarch64-opc.c: Likewise.
 422         * avr-dis.c: Likewise.
 423         * csky-dis.c: Likewise.
 424         * nds32-asm.c: Likewise.
 425         * nds32-dis.c: Likewise.
 426         * nfp-dis.c: Likewise.
 427         * riscv-dis.c: Likewise.
 428         * s12z-dis.c: Likewise.
 429         * wasm32-dis.c: Likewise.
 430
 431 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 432
 433         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 434         (i386_seg_prefixes): New.
 435         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 436         (i386_seg_prefixes): Declare.
 437
 438 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 439
 440         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 441
 442 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 443
 444         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 445         * i386-reg.tbl (st): Move down.
 446         (st(0)): Delete. Extend comment.
 447         * i386-tbl.h: Re-generate.
 448
 449 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 450
 451         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 452         (cmpsd): Move next to cmps.
 453         (movsd): Move next to movs.
 454         (cmpxchg16b): Move to separate section.
 455         (fisttp, fisttpll): Likewise.
 456         (monitor, mwait): Likewise.
 457         * i386-tbl.h: Re-generate.
 458
 459 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 460
 461         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 462         (vpsadbw): Add C.
 463         * i386-tbl.h: Re-generate.
 464
 465 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 466
 467         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 468         pclmul, gfni): New templates. Use them wherever possible. Move
 469         SSE4.1 pextrw into respective section.
 470         * i386-tbl.h: Re-generate.
 471
 472 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 473
 474         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 475         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 476         "length".
 477         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 478         Convert all of their uses to representation in opcode.
 479
 480 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 481
 482         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 483         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 484         value of None. Shrink operands to 3 bits.
 485
 486 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 487
 488         * i386-gen.c (process_i386_opcode_modifier): New parameter
 489         "space".
 490         (output_i386_opcode): New local variable "space". Adjust
 491         process_i386_opcode_modifier() invocation.
 492         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 493         invocation.
 494         * i386-tbl.h: Re-generate.
 495
 496 2021-03-29  Alan Modra  <amodra@gmail.com>
 497
 498         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 499         (fp_qualifier_p, get_data_pattern): Likewise.
 500         (aarch64_get_operand_modifier_from_value): Likewise.
 501         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 502         (operand_variant_qualifier_p): Likewise.
 503         (qualifier_value_in_range_constraint_p): Likewise.
 504         (aarch64_get_qualifier_esize): Likewise.
 505         (aarch64_get_qualifier_nelem): Likewise.
 506         (aarch64_get_qualifier_standard_value): Likewise.
 507         (get_lower_bound, get_upper_bound): Likewise.
 508         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 509         (aarch64_print_operand): Likewise.
 510         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 511         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 512         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 513         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 514         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 515         (print_insn_tic6x): Likewise.
 516
 517 2021-03-29  Alan Modra  <amodra@gmail.com>
 518
 519         * arc-dis.c (extract_operand_value): Correct NULL cast.
 520         * frv-opc.h: Regenerate.
 521
 522 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 523
 524         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 525         MMX form.
 526         * i386-tbl.h: Re-generate.
 527
 528 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 529
 530         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 531         immediate in br.n instruction.
 532
 533 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 534
 535         * i386-dis.c (XMGatherD, VexGatherD): New.
 536         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 537         (print_insn): Check masking for S/G insns.
 538         (OP_E_memory): New local variable check_gather. Extend mandatory
 539         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 540         Extend check for disallowed 16-bit addressing.
 541         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 542         if()s to switch(). Check register conflicts for (VEX-encoded)
 543         gathers. Drop no longer reachable cases.
 544         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 545         vgatherdp*.
 546
 547 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 548
 549         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 550         zeroing-masking without masking.
 551
 552 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 553
 554         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 555         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 556         single-operand forms as deprecated.
 557         * i386-tbl.h: Re-generate.
 558
 559 2021-03-25  Alan Modra  <amodra@gmail.com>
 560
 561         PR 27647
 562         * ppc-opc.c (XLOCB_MASK): Delete.
 563         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 564         XLBH_MASK.
 565         (powerpc_opcodes): Accept a BH field on all extended forms of
 566         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 567
 568 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 569
 570         * i386-gen.c (output_i386_opcode): Drop processing of
 571         opcode_length. Calculate length from base_opcode. Adjust prefix
 572         encoding determination.
 573         (process_i386_opcodes): Drop output of fake opcode_length.
 574         * i386-opc.h (struct insn_template): Drop opcode_length field.
 575         * i386-opc.tbl: Drop opcode length field from all templates.
 576         * i386-tbl.h: Re-generate.
 577
 578 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 579
 580         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 581         parameter "prefix". Drop local variable "regular_encoding".
 582         Record prefix setting / check for consistency.
 583         (output_i386_opcode): Parse opcode_length and base_opcode
 584         earlier. Derive prefix encoding. Drop no longer applicable
 585         consistency checking. Adjust process_i386_opcode_modifier()
 586         invocation.
 587         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 588         invocation.
 589         * i386-tbl.h: Re-generate.
 590
 591 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 592
 593         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 594         check.
 595         * i386-opc.h (Prefix_*): Move #define-s.
 596         * i386-opc.tbl: Move pseudo prefix enumerator values to
 597         extension opcode field. Introduce pseudopfx template.
 598         * i386-tbl.h: Re-generate.
 599
 600 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 601
 602         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 603         comment.
 604         * i386-tbl.h: Re-generate.
 605
 606 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 607
 608         * i386-opc.h (struct insn_template): Move cpu_flags field past
 609         opcode_modifier one.
 610         * i386-tbl.h: Re-generate.
 611
 612 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 613
 614         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 615         * i386-opc.h (OpcodeSpace): New enumerator.
 616         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 617         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 618         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 619         (struct i386_opcode_modifier): New field opcodespace. Shrink
 620         opcodeprefix field.
 621         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 622         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 623         OpcodePrefix uses.
 624         * i386-tbl.h: Re-generate.
 625
 626 2021-03-22  Martin Liska  <mliska@suse.cz>
 627
 628         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 629         * arc-dis.c (parse_option): Likewise.
 630         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 631         * cris-dis.c (print_with_operands): Likewise.
 632         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 633         * i386-dis.c (print_insn): Likewise.
 634         * ia64-gen.c (fetch_insn_class): Likewise.
 635         (parse_resource_users): Likewise.
 636         (in_iclass): Likewise.
 637         (lookup_specifier): Likewise.
 638         (insert_opcode_dependencies): Likewise.
 639         * mips-dis.c (parse_mips_ase_option): Likewise.
 640         (parse_mips_dis_option): Likewise.
 641         * s390-dis.c (disassemble_init_s390): Likewise.
 642         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 643
 644 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 645
 646         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 647
 648 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 649
 650         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 651         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 652
 653 2021-03-12  Alan Modra  <amodra@gmail.com>
 654
 655         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 656
 657 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 658
 659         * i386-dis.c (OP_XMM): Re-order checks.
 660
 661 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 662
 663         * i386-dis.c (putop): Drop need_vex check when also checking
 664         vex.evex.
 665         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 666         checking vex.b.
 667
 668 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 669
 670         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 671         checks. Move case label past broadcast check.
 672
 673 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 674
 675         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 676         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 677         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 678         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 679         EVEX_W_0F38C7_M_0_L_2): Delete.
 680         (REG_EVEX_0F38C7_M_0_L_2): New.
 681         (intel_operand_size): Handle VEX and EVEX the same for
 682         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 683         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 684         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 685         vex_vsib_q_w_d_mode uses.
 686         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 687         0F38A1, and 0F38A3 entries.
 688         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 689         entry.
 690         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 691         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 692         0F38A3 entries.
 693
 694 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 695
 696         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 697         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 698         MOD_VEX_0FXOP_09_12): Rename to ...
 699         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 700         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 701         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 702         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 703         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 704         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 705         (reg_table): Adjust comments.
 706         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 707         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 708         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 709         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 710         (vex_len_table): Adjust opcode 0A_12 entry.
 711         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 712         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 713         (rm_table): Move hreset entry.
 714
 715 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 716
 717         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 718         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 719         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 720         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 721         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 722         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 723         (get_valid_dis386): Also handle 512-bit vector length when
 724         vectoring into vex_len_table[].
 725         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 726         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 727         entries.
 728         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 729         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 730         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 731         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 732         entries.
 733
 734 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 735
 736         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 737         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 738         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 739         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 740         entries.
 741         * i386-dis-evex-len.h (evex_len_table): Likewise.
 742         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 743
 744 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 745
 746         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 747         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 748         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 749         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 750         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 751         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 752         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 753         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 754         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 755         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 756         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 757         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 758         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 759         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 760         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 761         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 762         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 763         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 764         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 765         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 766         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 767         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 768         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 769         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 770         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 771         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 772         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 773         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 774         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 775         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 776         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 777         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 778         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 779         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 780         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 781         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 782         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 783         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 784         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 785         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 786         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 787         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 788         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 789         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 790         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 791         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 792         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 793         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 794         EVEX_W_0F3A43_L_n): New.
 795         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 796         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 797         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 798         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 799         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 800         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 801         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 802         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 803         0F385B, 0F38C6, and 0F38C7 entries.
 804         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 805         0F38C6 and 0F38C7.
 806         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 807         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 808         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 809         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 810
 811 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 812
 813         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 814         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 815         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 816         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 817         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 818         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 819         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 820         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 821         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 822         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 823         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 824         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 825         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 826         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 827         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 828         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 829         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 830         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 831         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 832         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 833         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 834         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 835         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 836         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 837         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 838         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 839         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 840         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 841         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 842         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 843         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 844         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 845         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 846         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 847         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 848         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 849         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 850         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 851         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 852         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 853         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 854         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 855         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 856         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 857         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 858         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 859         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 860         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 861         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 862         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 863         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 864         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 865         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 866         VEX_W_0F99_P_2_LEN_0): Delete.
 867         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 868         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 869         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 870         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 871         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 872         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 873         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 874         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 875         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 876         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 877         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 878         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 879         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 880         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 881         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 882         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 883         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 884         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 885         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 886         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 887         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 888         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 889         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 890         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 891         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 892         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 893         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 894         (prefix_table): No longer link to vex_len_table[] for opcodes
 895         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 896         0F92, 0F93, 0F98, and 0F99.
 897         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 898         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 899         0F98, and 0F99.
 900         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 901         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 902         0F98, and 0F99.
 903         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 904         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 905         0F98, and 0F99.
 906         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 907         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 908         0F98, and 0F99.
 909
 910 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 911
 912         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 913         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 914         REG_VEX_0F73_M_0 respectively.
 915         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 916         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 917         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 918         MOD_VEX_0F73_REG_7): Delete.
 919         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 920         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 921         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 922         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 923         PREFIX_VEX_0F3AF0_L_0 respectively.
 924         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 925         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 926         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 927         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 928         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 929         VEX_LEN_0F38F7): New.
 930         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 931         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 932         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 933         0F38F3.
 934         (prefix_table): No longer link to vex_len_table[] for opcodes
 935         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 936         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 937         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 938         0F38F6, 0F38F7, and 0F3AF0.
 939         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 940         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 941         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 942         0F73.
 943
 944 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 945
 946         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 947         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 948         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 949         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 950         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 951         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 952         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 953         73.
 954         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 955         0F72, and 0F73.
 956         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 957         0F73.
 958
 959 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 960
 961         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 962         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 963         (reg_table): Don't link to mod_table[] where not needed. Add
 964         PREFIX_IGNORED to nop entries.
 965         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 966         (mod_table): Add nop entries next to prefetch ones. Drop
 967         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 968         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 969         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 970         PREFIX_OPCODE from endbr* entries.
 971         (get_valid_dis386): Also consider entry's name when zapping
 972         vindex.
 973         (print_insn): Handle PREFIX_IGNORED.
 974
 975 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 976
 977         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 978         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 979         element.
 980         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 981         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 982         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 983         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 984         (struct i386_opcode_modifier): Delete notrackprefixok,
 985         islockable, hleprefixok, and repprefixok fields. Add prefixok
 986         field.
 987         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 988         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 989         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 990         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 991         Replace HLEPrefixOk.
 992         * opcodes/i386-tbl.h: Re-generate.
 993
 994 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 995
 996         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 997         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 998         64-bit form.
 999         * opcodes/i386-tbl.h: Re-generate.
1000
1001 2021-03-03  Jan Beulich  <jbeulich@suse.com>
1002
1003         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
1004         for {} instead of {0}. Don't look for '0'.
1005         * i386-opc.tbl: Drop operand count field. Drop redundant operand
1006         size specifiers.
1007
1008 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
1009
1010         PR 27158
1011         * riscv-dis.c (print_insn_args): Updated encoding macros.
1012         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
1013         (match_c_addi16sp): Updated encoding macros.
1014         (match_c_lui): Likewise.
1015         (match_c_lui_with_hint): Likewise.
1016         (match_c_addi4spn): Likewise.
1017         (match_c_slli): Likewise.
1018         (match_slli_as_c_slli): Likewise.
1019         (match_c_slli64): Likewise.
1020         (match_srxi_as_c_srxi): Likewise.
1021         (riscv_insn_types): Added .insn css/cl/cs.
1022
1023 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
1024
1025         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1026         (default_priv_spec): Updated type to riscv_spec_class.
1027         (parse_riscv_dis_option): Updated.
1028         * riscv-opc.c: Moved stuff and make the file tidy.
1029
1030 2021-02-17  Alan Modra  <amodra@gmail.com>
1031
1032         * wasm32-dis.c: Include limits.h.
1033         (CHAR_BIT): Provide backup define.
1034         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1035         Correct signed overflow checking.
1036
1037 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1038
1039         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1040         * i386-tbl.h: Re-generate.
1041
1042 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1043
1044         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1045         Oword.
1046         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1047
1048 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
1049
1050         * s390-mkopc.c (main): Accept arch14 as cpu string.
1051         * s390-opc.txt: Add new arch14 instructions.
1052
1053 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
1054
1055         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1056         favour of LIBINTL.
1057         * configure: Regenerated.
1058
1059 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
1060
1061         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1062         * tic54x-opc.c (regs): Rename to ...
1063         (tic54x_regs): ... this.
1064         (mmregs): Rename to ...
1065         (tic54x_mmregs): ... this.
1066         (condition_codes): Rename to ...
1067         (tic54x_condition_codes): ... this.
1068         (cc2_codes): Rename to ...
1069         (tic54x_cc2_codes): ... this.
1070         (cc3_codes): Rename to ...
1071         (tic54x_cc3_codes): ... this.
1072         (status_bits): Rename to ...
1073         (tic54x_status_bits): ... this.
1074         (misc_symbols): Rename to ...
1075         (tic54x_misc_symbols): ... this.
1076
1077 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
1078
1079         * riscv-opc.c (MASK_RVB_IMM): Removed.
1080         (riscv_opcodes): Removed zb* instructions.
1081         (riscv_ext_version_table): Removed versions for zb*.
1082
1083 2021-01-26  Alan Modra  <amodra@gmail.com>
1084
1085         * i386-gen.c (parse_template): Ensure entire template_instance
1086         is initialised.
1087
1088 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1089
1090         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1091         (riscv_fpr_names_abi): Likewise.
1092         (riscv_opcodes): Likewise.
1093         (riscv_insn_types): Likewise.
1094
1095 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1096
1097         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1098
1099 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1100
1101         * riscv-dis.c: Comments tidy and improvement.
1102         * riscv-opc.c: Likewise.
1103
1104 2021-01-13  Alan Modra  <amodra@gmail.com>
1105
1106         * Makefile.in: Regenerate.
1107
1108 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
1109
1110         PR binutils/26792
1111         * configure.ac: Use GNU_MAKE_JOBSERVER.
1112         * aclocal.m4: Regenerated.
1113         * configure: Likewise.
1114
1115 2021-01-12  Nick Clifton  <nickc@redhat.com>
1116
1117         * po/sr.po: Updated Serbian translation.
1118
1119 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
1120
1121         PR ld/27173
1122         * configure: Regenerated.
1123
1124 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1125
1126         * aarch64-asm-2.c: Regenerate.
1127         * aarch64-dis-2.c: Likewise.
1128         * aarch64-opc-2.c: Likewise.
1129         * aarch64-opc.c (aarch64_print_operand):
1130         Delete handling of AARCH64_OPND_CSRE_CSR.
1131         * aarch64-tbl.h (aarch64_feature_csre): Delete.
1132         (CSRE): Likewise.
1133         (_CSRE_INSN): Likewise.
1134         (aarch64_opcode_table): Delete csr.
1135
1136 2021-01-11  Nick Clifton  <nickc@redhat.com>
1137
1138         * po/de.po: Updated German translation.
1139         * po/fr.po: Updated French translation.
1140         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1141         * po/sv.po: Updated Swedish translation.
1142         * po/uk.po: Updated Ukranian translation.
1143
1144 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
1145
1146         * configure: Regenerated.
1147
1148 2021-01-09  Nick Clifton  <nickc@redhat.com>
1149
1150         * configure: Regenerate.
1151         * po/opcodes.pot: Regenerate.
1152
1153 2021-01-09  Nick Clifton  <nickc@redhat.com>
1154
1155         * 2.36 release branch crated.
1156
1157 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
1158
1159         * ppc-opc.c (insert_dw, (extract_dw): New functions.
1160         (DW, (XRC_MASK): Define.
1161         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1162
1163 2021-01-09  Alan Modra  <amodra@gmail.com>
1164
1165         * configure: Regenerate.
1166
1167 2021-01-08  Nick Clifton  <nickc@redhat.com>
1168
1169         * po/sv.po: Updated Swedish translation.
1170
1171 2021-01-08  Nick Clifton  <nickc@redhat.com>
1172
1173         PR 27129
1174         * aarch64-dis.c (determine_disassembling_preference): Move call to
1175         aarch64_match_operands_constraint outside of the assertion.
1176         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1177         Replace with a return of FALSE.
1178
1179         PR 27139
1180         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1181         core system register.
1182
1183 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
1184
1185         * configure: Regenerate.
1186
1187 2021-01-07  Nick Clifton  <nickc@redhat.com>
1188
1189         * po/fr.po: Updated French translation.
1190
1191 2021-01-07  Fredrik Noring  <noring@nocrew.org>
1192
1193         * m68k-opc.c (chkl): Change minimum architecture requirement to
1194         m68020.
1195
1196 2021-01-07  Philipp Tomsich  <prt@gnu.org>
1197
1198         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1199
1200 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
1201             Jim Wilson  <jimw@sifive.com>
1202             Andrew Waterman  <andrew@sifive.com>
1203             Maxim Blinov  <maxim.blinov@embecosm.com>
1204             Kito Cheng  <kito.cheng@sifive.com>
1205             Nelson Chu  <nelson.chu@sifive.com>
1206
1207         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1208         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1209
1210 2021-01-01  Alan Modra  <amodra@gmail.com>
1211
1212         Update year range in copyright notice of all files.
1213
1214 For older changes see ChangeLog-2020
1215 \f
1216 Copyright (C) 2021 Free Software Foundation, Inc.
1217
1218 Copying and distribution of this file, with or without modification,
1219 are permitted in any medium without royalty provided the copyright
1220 notice and this notice are preserved.
1221
1222 Local Variables:
1223 mode: change-log
1224 left-margin: 8
1225 fill-column: 74
1226 version-control: never
1227 End: