1 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
3 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
4 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
5 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
7 * aarch64-asm-2.c: Regenerate.
8 * aarch64-dis-2.c: Regenerate.
10 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
12 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
14 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
17 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
18 * i386-dis.c (EdqwS): Removed.
19 (dqw_swap_mode): Likewise.
20 (intel_operand_size): Don't check dqw_swap_mode.
21 (OP_E_register): Likewise.
22 (OP_E_memory): Likewise.
25 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
26 * i386-tbl.h: Regerated.
28 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
30 * i386-opc.tbl: Merge AVX512F vmovq.
31 * i386-tbl.h: Regerated.
33 2016-11-08 H.J. Lu <hongjiu.lu@intel.com>
36 * i386-dis.c (THREE_BYTE_0F7A): Removed.
37 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
38 (three_byte_table): Remove THREE_BYTE_0F7A.
40 2016-11-07 H.J. Lu <hongjiu.lu@intel.com>
43 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
44 (FGRPd9_4): Replace 1 with 2.
45 (FGRPd9_5): Replace 2 with 3.
46 (FGRPd9_6): Replace 3 with 4.
47 (FGRPd9_7): Replace 4 with 5.
48 (FGRPda_5): Replace 5 with 6.
49 (FGRPdb_4): Replace 6 with 7.
50 (FGRPde_3): Replace 7 with 8.
51 (FGRPdf_4): Replace 8 with 9.
52 (fgrps): Add an entry for Bad_Opcode.
54 2016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
56 * arc-opc.c (arc_flag_operands): Add F_DI14.
57 (arc_flag_classes): Add C_DI14.
58 * arc-nps400-tbl.h: Add new exc instructions.
60 2016-11-03 Graham Markall <graham.markall@embecosm.com>
62 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
64 * arc-nps-400-tbl.h: Add dcmac instruction.
65 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
66 (insert_nps_rbdouble_64): Added.
67 (extract_nps_rbdouble_64): Added.
68 (insert_nps_proto_size): Added.
69 (extract_nps_proto_size): Added.
71 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
73 * arc-dis.c (struct arc_operand_iterator): Remove all fields
74 relating to long instruction processing, add new limm field.
75 (OPCODE): Rename to...
76 (OPCODE_32BIT_INSN): ...this.
78 (skip_this_opcode): Handle different instruction lengths, update
80 (special_flag_p): Update parameter type.
81 (find_format_from_table): Update for more instruction lengths.
82 (find_format_long_instructions): Delete.
83 (find_format): Update for more instruction lengths.
84 (arc_insn_length): Likewise.
85 (extract_operand_value): Update for more instruction lengths.
86 (operand_iterator_next): Remove code relating to long
88 (arc_opcode_to_insn_type): New function.
89 (print_insn_arc):Update for more instructions lengths.
90 * arc-ext.c (extInstruction_t): Change argument type.
91 * arc-ext.h (extInstruction_t): Change argument type.
92 * arc-fxi.h: Change type unsigned to unsigned long long
93 extensively throughout.
94 * arc-nps400-tbl.h: Add long instructions taken from
95 arc_long_opcodes table in arc-opc.c.
96 * arc-opc.c: Update parameter types on insert/extract handlers.
97 (arc_long_opcodes): Delete.
98 (arc_num_long_opcodes): Delete.
99 (arc_opcode_len): Update for more instruction lengths.
101 2016-11-03 Graham Markall <graham.markall@embecosm.com>
103 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
105 2016-11-03 Graham Markall <graham.markall@embecosm.com>
107 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
109 (find_format_long_instructions): Likewise.
110 * arc-opc.c (arc_opcode_len): New function.
112 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
114 * arc-nps400-tbl.h: Fix some instruction masks.
116 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
118 * i386-dis.c (REG_82): Removed.
119 (X86_64_82_REG_0): Likewise.
120 (X86_64_82_REG_1): Likewise.
121 (X86_64_82_REG_2): Likewise.
122 (X86_64_82_REG_3): Likewise.
123 (X86_64_82_REG_4): Likewise.
124 (X86_64_82_REG_5): Likewise.
125 (X86_64_82_REG_6): Likewise.
126 (X86_64_82_REG_7): Likewise.
128 (dis386): Use X86_64_82 instead of REG_82.
129 (reg_table): Remove REG_82.
130 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
131 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
132 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
135 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
138 * i386-dis.c (REG_82): New.
139 (X86_64_82_REG_0): Likewise.
140 (X86_64_82_REG_1): Likewise.
141 (X86_64_82_REG_2): Likewise.
142 (X86_64_82_REG_3): Likewise.
143 (X86_64_82_REG_4): Likewise.
144 (X86_64_82_REG_5): Likewise.
145 (X86_64_82_REG_6): Likewise.
146 (X86_64_82_REG_7): Likewise.
147 (dis386): Use REG_82.
148 (reg_table): Add REG_82.
149 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
150 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
151 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
153 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
155 * i386-dis.c (REG_82): Renamed to ...
158 (reg_table): Likewise.
160 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
162 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
163 * i386-dis-evex.h (evex_table): Updated.
164 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
165 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
166 (cpu_flags): Add CpuAVX512_4VNNIW.
167 * i386-opc.h (enum): (AVX512_4VNNIW): New.
168 (i386_cpu_flags): Add cpuavx512_4vnniw.
169 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
170 * i386-init.h: Regenerate.
173 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
175 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
176 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
177 * i386-dis-evex.h (evex_table): Updated.
178 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
179 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
180 (cpu_flags): Add CpuAVX512_4FMAPS.
181 (opcode_modifiers): Add ImplicitQuadGroup modifier.
182 * i386-opc.h (AVX512_4FMAP): New.
183 (i386_cpu_flags): Add cpuavx512_4fmaps.
184 (ImplicitQuadGroup): New.
185 (i386_opcode_modifier): Add implicitquadgroup.
186 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
187 * i386-init.h: Regenerate.
190 2016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
191 Andrew Waterman <andrew@sifive.com>
193 Add support for RISC-V architecture.
194 * configure.ac: Add entry for bfd_riscv_arch.
195 * configure: Regenerate.
196 * disassemble.c (disassembler): Add support for riscv.
197 (disassembler_usage): Likewise.
198 * riscv-dis.c: New file.
199 * riscv-opc.c: New file.
201 2016-10-21 H.J. Lu <hongjiu.lu@intel.com>
203 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
204 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
205 (rm_table): Update the RM_0FAE_REG_7 entry.
206 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
207 (cpu_flags): Remove CpuPCOMMIT.
208 * i386-opc.h (CpuPCOMMIT): Removed.
209 (i386_cpu_flags): Remove cpupcommit.
210 * i386-opc.tbl: Remove pcommit.
211 * i386-init.h: Regenerated.
212 * i386-tbl.h: Likewise.
214 2016-10-20 H.J. Lu <hongjiu.lu@intel.com>
217 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
218 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
219 32-bit mode. Don't check vex.register_specifier in 32-bit
221 (OP_VEX): Check for invalid mask registers.
223 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
226 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
229 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
232 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
234 2016-10-18 Maciej W. Rozycki <macro@imgtec.com>
236 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
237 local variable to `index_regno'.
239 2016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
241 * arc-tbl.h: Removed any "inv.+" instructions from the table.
243 2016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
245 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
248 2016-10-11 Jiong Wang <jiong.wang@arm.com>
251 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
253 2016-10-07 Jiong Wang <jiong.wang@arm.com>
256 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
259 2016-10-07 Alan Modra <amodra@gmail.com>
261 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
263 2016-10-06 Alan Modra <amodra@gmail.com>
265 * aarch64-opc.c: Spell fall through comments consistently.
266 * i386-dis.c: Likewise.
267 * aarch64-dis.c: Add missing fall through comments.
268 * aarch64-opc.c: Likewise.
269 * arc-dis.c: Likewise.
270 * arm-dis.c: Likewise.
271 * i386-dis.c: Likewise.
272 * m68k-dis.c: Likewise.
273 * mep-asm.c: Likewise.
274 * ns32k-dis.c: Likewise.
275 * sh-dis.c: Likewise.
276 * tic4x-dis.c: Likewise.
277 * tic6x-dis.c: Likewise.
278 * vax-dis.c: Likewise.
280 2016-10-06 Alan Modra <amodra@gmail.com>
282 * arc-ext.c (create_map): Add missing break.
283 * msp430-decode.opc (encode_as): Likewise.
284 * msp430-decode.c: Regenerate.
286 2016-10-06 Alan Modra <amodra@gmail.com>
288 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
289 * crx-dis.c (print_insn_crx): Likewise.
291 2016-09-30 H.J. Lu <hongjiu.lu@intel.com>
294 * i386-dis.c (putop): Don't assign alt twice.
296 2016-09-29 Jiong Wang <jiong.wang@arm.com>
299 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
301 2016-09-29 Alan Modra <amodra@gmail.com>
303 * ppc-opc.c (L): Make compulsory.
304 (LOPT): New, optional form of L.
305 (HTM_R): Define as LOPT.
307 (L32OPT): New, optional for 32-bit L.
308 (L2OPT): New, 2-bit L for dcbf.
311 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
312 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
314 <tlbiel, tlbie>: Use LOPT.
315 <wclr, wclrall>: Use L2.
317 2016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
319 * Makefile.in: Regenerate.
320 * configure: Likewise.
322 2016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
324 * arc-ext-tbl.h (EXTINSN2OPF): Define.
325 (EXTINSN2OP): Use EXTINSN2OPF.
326 (bspeekm, bspop, modapp): New extension instructions.
327 * arc-opc.c (F_DNZ_ND): Define.
332 * arc-tbl.h (dbnz): New instruction.
333 (prealloc): Allow it for ARC EM.
336 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
338 * aarch64-opc.c (print_immediate_offset_address): Print spaces
339 after commas in addresses.
340 (aarch64_print_operand): Likewise.
342 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
344 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
345 rather than "should be" or "expected to be" in error messages.
347 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
349 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
350 (print_mnemonic_name): ...here.
351 (print_comment): New function.
352 (print_aarch64_insn): Call it.
353 * aarch64-opc.c (aarch64_conds): Add SVE names.
354 (aarch64_print_operand): Print alternative condition names in
357 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
359 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
360 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
361 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
362 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
363 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
364 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
365 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
366 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
367 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
368 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
369 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
370 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
371 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
372 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
373 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
374 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
375 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
376 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
377 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
378 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
379 (OP_SVE_XWU, OP_SVE_XXU): New macros.
380 (aarch64_feature_sve): New variable.
382 (_SVE_INSN): Likewise.
383 (aarch64_opcode_table): Add SVE instructions.
384 * aarch64-opc.h (extract_fields): Declare.
385 * aarch64-opc-2.c: Regenerate.
386 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
387 * aarch64-asm-2.c: Regenerate.
388 * aarch64-dis.c (extract_fields): Make global.
389 (do_misc_decoding): Handle the new SVE aarch64_ops.
390 * aarch64-dis-2.c: Regenerate.
392 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
394 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
395 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
397 * aarch64-opc.c (fields): Add corresponding entries.
398 * aarch64-asm.c (aarch64_get_variant): New function.
399 (aarch64_encode_variant_using_iclass): Likewise.
400 (aarch64_opcode_encode): Call it.
401 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
402 (aarch64_opcode_decode): Call it.
404 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
406 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
407 and FP register operands.
408 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
409 (FLD_SVE_Vn): New aarch64_field_kinds.
410 * aarch64-opc.c (fields): Add corresponding entries.
411 (aarch64_print_operand): Handle the new SVE core and FP register
413 * aarch64-opc-2.c: Regenerate.
414 * aarch64-asm-2.c: Likewise.
415 * aarch64-dis-2.c: Likewise.
417 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
419 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
421 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
422 * aarch64-opc.c (fields): Add corresponding entry.
423 (operand_general_constraint_met_p): Handle the new SVE FP immediate
425 (aarch64_print_operand): Likewise.
426 * aarch64-opc-2.c: Regenerate.
427 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
428 (ins_sve_float_zero_one): New inserters.
429 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
430 (aarch64_ins_sve_float_half_two): Likewise.
431 (aarch64_ins_sve_float_zero_one): Likewise.
432 * aarch64-asm-2.c: Regenerate.
433 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
434 (ext_sve_float_zero_one): New extractors.
435 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
436 (aarch64_ext_sve_float_half_two): Likewise.
437 (aarch64_ext_sve_float_zero_one): Likewise.
438 * aarch64-dis-2.c: Regenerate.
440 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
442 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
443 integer immediate operands.
444 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
445 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
446 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
447 * aarch64-opc.c (fields): Add corresponding entries.
448 (operand_general_constraint_met_p): Handle the new SVE integer
450 (aarch64_print_operand): Likewise.
451 (aarch64_sve_dupm_mov_immediate_p): New function.
452 * aarch64-opc-2.c: Regenerate.
453 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
454 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
455 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
456 (aarch64_ins_limm): ...here.
457 (aarch64_ins_inv_limm): New function.
458 (aarch64_ins_sve_aimm): Likewise.
459 (aarch64_ins_sve_asimm): Likewise.
460 (aarch64_ins_sve_limm_mov): Likewise.
461 (aarch64_ins_sve_shlimm): Likewise.
462 (aarch64_ins_sve_shrimm): Likewise.
463 * aarch64-asm-2.c: Regenerate.
464 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
465 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
466 * aarch64-dis.c (decode_limm): New function, split out from...
467 (aarch64_ext_limm): ...here.
468 (aarch64_ext_inv_limm): New function.
469 (decode_sve_aimm): Likewise.
470 (aarch64_ext_sve_aimm): Likewise.
471 (aarch64_ext_sve_asimm): Likewise.
472 (aarch64_ext_sve_limm_mov): Likewise.
473 (aarch64_top_bit): Likewise.
474 (aarch64_ext_sve_shlimm): Likewise.
475 (aarch64_ext_sve_shrimm): Likewise.
476 * aarch64-dis-2.c: Regenerate.
478 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
480 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
482 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
483 the AARCH64_MOD_MUL_VL entry.
484 (value_aligned_p): Cope with non-power-of-two alignments.
485 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
486 (print_immediate_offset_address): Likewise.
487 (aarch64_print_operand): Likewise.
488 * aarch64-opc-2.c: Regenerate.
489 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
490 (ins_sve_addr_ri_s9xvl): New inserters.
491 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
492 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
493 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
494 * aarch64-asm-2.c: Regenerate.
495 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
496 (ext_sve_addr_ri_s9xvl): New extractors.
497 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
498 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
499 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
500 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
501 * aarch64-dis-2.c: Regenerate.
503 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
505 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
507 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
508 (FLD_SVE_xs_22): New aarch64_field_kinds.
509 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
510 (get_operand_specific_data): New function.
511 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
512 FLD_SVE_xs_14 and FLD_SVE_xs_22.
513 (operand_general_constraint_met_p): Handle the new SVE address
515 (sve_reg): New array.
516 (get_addr_sve_reg_name): New function.
517 (aarch64_print_operand): Handle the new SVE address operands.
518 * aarch64-opc-2.c: Regenerate.
519 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
520 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
521 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
522 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
523 (aarch64_ins_sve_addr_rr_lsl): Likewise.
524 (aarch64_ins_sve_addr_rz_xtw): Likewise.
525 (aarch64_ins_sve_addr_zi_u5): Likewise.
526 (aarch64_ins_sve_addr_zz): Likewise.
527 (aarch64_ins_sve_addr_zz_lsl): Likewise.
528 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
529 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
530 * aarch64-asm-2.c: Regenerate.
531 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
532 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
533 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
534 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
535 (aarch64_ext_sve_addr_ri_u6): Likewise.
536 (aarch64_ext_sve_addr_rr_lsl): Likewise.
537 (aarch64_ext_sve_addr_rz_xtw): Likewise.
538 (aarch64_ext_sve_addr_zi_u5): Likewise.
539 (aarch64_ext_sve_addr_zz): Likewise.
540 (aarch64_ext_sve_addr_zz_lsl): Likewise.
541 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
542 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
543 * aarch64-dis-2.c: Regenerate.
545 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
547 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
548 AARCH64_OPND_SVE_PATTERN_SCALED.
549 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
550 * aarch64-opc.c (fields): Add a corresponding entry.
551 (set_multiplier_out_of_range_error): New function.
552 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
553 (operand_general_constraint_met_p): Handle
554 AARCH64_OPND_SVE_PATTERN_SCALED.
555 (print_register_offset_address): Use PRIi64 to print the
557 (aarch64_print_operand): Likewise. Handle
558 AARCH64_OPND_SVE_PATTERN_SCALED.
559 * aarch64-opc-2.c: Regenerate.
560 * aarch64-asm.h (ins_sve_scale): New inserter.
561 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
562 * aarch64-asm-2.c: Regenerate.
563 * aarch64-dis.h (ext_sve_scale): New inserter.
564 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
565 * aarch64-dis-2.c: Regenerate.
567 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
569 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
570 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
571 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
572 (FLD_SVE_prfop): Likewise.
573 * aarch64-opc.c: Include libiberty.h.
574 (aarch64_sve_pattern_array): New variable.
575 (aarch64_sve_prfop_array): Likewise.
576 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
577 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
578 AARCH64_OPND_SVE_PRFOP.
579 * aarch64-asm-2.c: Regenerate.
580 * aarch64-dis-2.c: Likewise.
581 * aarch64-opc-2.c: Likewise.
583 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
585 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
586 AARCH64_OPND_QLF_P_[ZM].
587 (aarch64_print_operand): Print /z and /m where appropriate.
589 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
591 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
592 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
593 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
594 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
595 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
596 * aarch64-opc.c (fields): Add corresponding entries here.
597 (operand_general_constraint_met_p): Check that SVE register lists
598 have the correct length. Check the ranges of SVE index registers.
599 Check for cases where p8-p15 are used in 3-bit predicate fields.
600 (aarch64_print_operand): Handle the new SVE operands.
601 * aarch64-opc-2.c: Regenerate.
602 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
603 * aarch64-asm.c (aarch64_ins_sve_index): New function.
604 (aarch64_ins_sve_reglist): Likewise.
605 * aarch64-asm-2.c: Regenerate.
606 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
607 * aarch64-dis.c (aarch64_ext_sve_index): New function.
608 (aarch64_ext_sve_reglist): Likewise.
609 * aarch64-dis-2.c: Regenerate.
611 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
613 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
614 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
615 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
616 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
619 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
621 * aarch64-opc.c (get_offset_int_reg_name): New function.
622 (print_immediate_offset_address): Likewise.
623 (print_register_offset_address): Take the base and offset
624 registers as parameters.
625 (aarch64_print_operand): Update caller accordingly. Use
626 print_immediate_offset_address.
628 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
630 * aarch64-opc.c (BANK): New macro.
631 (R32, R64): Take a register number as argument
634 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
636 * aarch64-opc.c (print_register_list): Add a prefix parameter.
637 (aarch64_print_operand): Update accordingly.
639 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
641 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
643 * aarch64-asm.h (ins_fpimm): New inserter.
644 * aarch64-asm.c (aarch64_ins_fpimm): New function.
645 * aarch64-asm-2.c: Regenerate.
646 * aarch64-dis.h (ext_fpimm): New extractor.
647 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
648 (aarch64_ext_fpimm): New function.
649 * aarch64-dis-2.c: Regenerate.
651 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
653 * aarch64-asm.c: Include libiberty.h.
654 (insert_fields): New function.
655 (aarch64_ins_imm): Use it.
656 * aarch64-dis.c (extract_fields): New function.
657 (aarch64_ext_imm): Use it.
659 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
661 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
662 with an esize parameter.
663 (operand_general_constraint_met_p): Update accordingly.
664 Fix misindented code.
665 * aarch64-asm.c (aarch64_ins_limm): Update call to
666 aarch64_logical_immediate_p.
668 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
670 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
672 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
674 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
676 2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
678 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
680 2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
682 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
683 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
684 xor3>: Delete mnemonics.
685 <cp_abort>: Rename mnemonic from ...
686 <cpabort>: ...to this.
687 <setb>: Change to a X form instruction.
688 <sync>: Change to 1 operand form.
689 <copy>: Delete mnemonic.
690 <copy_first>: Rename mnemonic from ...
692 <paste, paste.>: Delete mnemonics.
693 <paste_last>: Rename mnemonic from ...
694 <paste.>: ...to this.
696 2016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
698 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
700 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
702 * s390-mkopc.c (main): Support alternate arch strings.
704 2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
706 * s390-opc.txt: Fix kmctr instruction type.
708 2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
710 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
711 * i386-init.h: Regenerated.
713 2016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
715 * opcodes/arc-dis.c (print_insn_arc): Changed.
717 2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
719 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
722 2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
724 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
725 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
726 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
728 2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
730 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
731 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
732 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
733 PREFIX_MOD_3_0FAE_REG_4.
734 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
735 PREFIX_MOD_3_0FAE_REG_4.
736 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
737 (cpu_flags): Add CpuPTWRITE.
738 * i386-opc.h (CpuPTWRITE): New.
739 (i386_cpu_flags): Add cpuptwrite.
740 * i386-opc.tbl: Add ptwrite instruction.
741 * i386-init.h: Regenerated.
742 * i386-tbl.h: Likewise.
744 2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
746 * arc-dis.h: Wrap around in extern "C".
748 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
750 * aarch64-tbl.h (V8_2_INSN): New macro.
751 (aarch64_opcode_table): Use it.
753 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
755 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
756 CORE_INSN, __FP_INSN and SIMD_INSN.
758 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
760 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
761 (aarch64_opcode_table): Update uses accordingly.
763 2016-07-25 Andrew Jenner <andrew@codesourcery.com>
764 Kwok Cheung Yeung <kcy@codesourcery.com>
767 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
768 'e_cmplwi' to 'e_cmpli' instead.
769 (OPVUPRT, OPVUPRT_MASK): Define.
770 (powerpc_opcodes): Add E200Z4 insns.
771 (vle_opcodes): Add context save/restore insns.
773 2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
775 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
776 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
779 2016-07-27 Graham Markall <graham.markall@embecosm.com>
781 * arc-nps400-tbl.h: Change block comments to GNU format.
782 * arc-dis.c: Add new globals addrtypenames,
783 addrtypenames_max, and addtypeunknown.
784 (get_addrtype): New function.
785 (print_insn_arc): Print colons and address types when
787 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
788 define insert and extract functions for all address types.
789 (arc_operands): Add operands for colon and all address
791 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
792 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
793 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
794 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
795 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
796 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
798 2016-07-21 H.J. Lu <hongjiu.lu@intel.com>
800 * configure: Regenerated.
802 2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
804 * arc-dis.c (skipclass): New structure.
805 (decodelist): New variable.
806 (is_compatible_p): New function.
807 (new_element): Likewise.
808 (skip_class_p): Likewise.
809 (find_format_from_table): Use skip_class_p function.
810 (find_format): Decode first the extension instructions.
811 (print_insn_arc): Select either ARCEM or ARCHS based on elf
813 (parse_option): New function.
814 (parse_disassembler_options): Likewise.
815 (print_arc_disassembler_options): Likewise.
816 (print_insn_arc): Use parse_disassembler_options function. Proper
817 select ARCv2 cpu variant.
818 * disassemble.c (disassembler_usage): Add ARC disassembler
821 2016-07-13 Maciej W. Rozycki <macro@imgtec.com>
823 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
824 annotation from the "nal" entry and reorder it beyond "bltzal".
826 2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
828 * sparc-opc.c (ldtxa): New macro.
829 (sparc_opcodes): Use the macro defined above to add entries for
830 the LDTXA instructions.
831 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
834 2016-07-07 James Bowman <james.bowman@ftdichip.com>
836 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
839 2016-07-01 Jan Beulich <jbeulich@suse.com>
841 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
842 (movzb): Adjust to cover all permitted suffixes.
844 * i386-tbl.h: Re-generate.
846 2016-07-01 Jan Beulich <jbeulich@suse.com>
848 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
849 (lgdt): Remove Tbyte from non-64-bit variant.
850 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
851 xsaves64, xsavec64): Remove Disp16.
852 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
853 Remove Disp32S from non-64-bit variants. Remove Disp16 from
855 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
856 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
857 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
859 * i386-tbl.h: Re-generate.
861 2016-07-01 Jan Beulich <jbeulich@suse.com>
863 * i386-opc.tbl (xlat): Remove RepPrefixOk.
864 * i386-tbl.h: Re-generate.
866 2016-06-30 Yao Qi <yao.qi@linaro.org>
868 * arm-dis.c (print_insn): Fix typo in comment.
870 2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
872 * aarch64-opc.c (operand_general_constraint_met_p): Check the
873 range of ldst_elemlist operands.
874 (print_register_list): Use PRIi64 to print the index.
875 (aarch64_print_operand): Likewise.
877 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
879 * mcore-opc.h: Remove sentinal.
880 * mcore-dis.c (print_insn_mcore): Adjust.
882 2016-06-23 Graham Markall <graham.markall@embecosm.com>
884 * arc-opc.c: Correct description of availability of NPS400
887 2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
889 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
890 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
891 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
892 xor3>: New mnemonics.
893 <setb>: Change to a VX form instruction.
894 (insert_sh6): Add support for rldixor.
895 (extract_sh6): Likewise.
897 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
899 * arc-ext.h: Wrap in extern C.
901 2016-06-21 Graham Markall <graham.markall@embecosm.com>
903 * arc-dis.c (arc_insn_length): Add comment on instruction length.
904 Use same method for determining instruction length on ARC700 and
906 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
907 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
908 with the NPS400 subclass.
909 * arc-opc.c: Likewise.
911 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
913 * sparc-opc.c (rdasr): New macro.
919 (sparc_opcodes): Use the macros above to fix and expand the
920 definition of read/write instructions from/to
921 asr/privileged/hyperprivileged instructions.
922 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
923 %hva_mask_nz. Prefer softint_set and softint_clear over
924 set_softint and clear_softint.
925 (print_insn_sparc): Support %ver in Rd.
927 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
929 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
930 architecture according to the hardware capabilities they require.
932 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
934 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
935 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
936 bfd_mach_sparc_v9{c,d,e,v,m}.
937 * sparc-opc.c (MASK_V9C): Define.
938 (MASK_V9D): Likewise.
939 (MASK_V9E): Likewise.
940 (MASK_V9V): Likewise.
941 (MASK_V9M): Likewise.
942 (v6): Add MASK_V9{C,D,E,V,M}.
943 (v6notlet): Likewise.
947 (v9andleon): Likewise.
955 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
957 2016-06-15 Nick Clifton <nickc@redhat.com>
959 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
960 constants to match expected behaviour.
961 (nds32_parse_opcode): Likewise. Also for whitespace.
963 2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
965 * arc-opc.c (extract_rhv1): Extract value from insn.
967 2016-06-14 Graham Markall <graham.markall@embecosm.com>
969 * arc-nps400-tbl.h: Add ldbit instruction.
970 * arc-opc.c: Add flag classes required for ldbit.
972 2016-06-14 Graham Markall <graham.markall@embecosm.com>
974 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
975 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
976 support the above instructions.
978 2016-06-14 Graham Markall <graham.markall@embecosm.com>
980 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
981 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
982 csma, cbba, zncv, and hofs.
983 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
984 support the above instructions.
986 2016-06-06 Graham Markall <graham.markall@embecosm.com>
988 * arc-nps400-tbl.h: Add andab and orab instructions.
990 2016-06-06 Graham Markall <graham.markall@embecosm.com>
992 * arc-nps400-tbl.h: Add addl-like instructions.
994 2016-06-06 Graham Markall <graham.markall@embecosm.com>
996 * arc-nps400-tbl.h: Add mxb and imxb instructions.
998 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1000 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1003 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1005 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1007 (init_disasm): Handle new command line option "insnlength".
1008 (print_s390_disassembler_options): Mention new option in help
1010 (print_insn_s390): Use the encoded insn length when dumping
1011 unknown instructions.
1013 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1015 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1016 to the address and set as symbol address for LDS/ STS immediate operands.
1018 2016-06-07 Alan Modra <amodra@gmail.com>
1020 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1021 cpu for "vle" to e500.
1022 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1023 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1024 (PPCNONE): Delete, substitute throughout.
1025 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1026 except for major opcode 4 and 31.
1027 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1029 2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1031 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1032 ARM_EXT_RAS in relevant entries.
1034 2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1037 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1040 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1043 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1044 (indir_v_mode): New.
1045 Add comments for '&'.
1046 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1047 (putop): Handle '&'.
1048 (intel_operand_size): Handle indir_v_mode.
1049 (OP_E_register): Likewise.
1050 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1051 64-bit indirect call/jmp for AMD64.
1052 * i386-tbl.h: Regenerated
1054 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1056 * arc-dis.c (struct arc_operand_iterator): New structure.
1057 (find_format_from_table): All the old content from find_format,
1058 with some minor adjustments, and parameter renaming.
1059 (find_format_long_instructions): New function.
1060 (find_format): Rewritten.
1061 (arc_insn_length): Add LSB parameter.
1062 (extract_operand_value): New function.
1063 (operand_iterator_next): New function.
1064 (print_insn_arc): Use new functions to find opcode, and iterator
1066 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1067 (extract_nps_3bit_dst_short): New function.
1068 (insert_nps_3bit_src2_short): New function.
1069 (extract_nps_3bit_src2_short): New function.
1070 (insert_nps_bitop1_size): New function.
1071 (extract_nps_bitop1_size): New function.
1072 (insert_nps_bitop2_size): New function.
1073 (extract_nps_bitop2_size): New function.
1074 (insert_nps_bitop_mod4_msb): New function.
1075 (extract_nps_bitop_mod4_msb): New function.
1076 (insert_nps_bitop_mod4_lsb): New function.
1077 (extract_nps_bitop_mod4_lsb): New function.
1078 (insert_nps_bitop_dst_pos3_pos4): New function.
1079 (extract_nps_bitop_dst_pos3_pos4): New function.
1080 (insert_nps_bitop_ins_ext): New function.
1081 (extract_nps_bitop_ins_ext): New function.
1082 (arc_operands): Add new operands.
1083 (arc_long_opcodes): New global array.
1084 (arc_num_long_opcodes): New global.
1085 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1087 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1089 * nds32-asm.h: Add extern "C".
1090 * sh-opc.h: Likewise.
1092 2016-06-01 Graham Markall <graham.markall@embecosm.com>
1094 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1095 0,b,limm to the rflt instruction.
1097 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1099 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1102 2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1105 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1106 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1107 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1108 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1109 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1110 * i386-init.h: Regenerated.
1112 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1115 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1116 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1117 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1118 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1119 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1120 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1121 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1122 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1123 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1124 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1125 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1126 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1127 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1128 CpuRegMask for AVX512.
1129 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1131 (set_bitfield_from_cpu_flag_init): New function.
1132 (set_bitfield): Remove const on f. Call
1133 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1134 * i386-opc.h (CpuRegMMX): New.
1135 (CpuRegXMM): Likewise.
1136 (CpuRegYMM): Likewise.
1137 (CpuRegZMM): Likewise.
1138 (CpuRegMask): Likewise.
1139 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1141 * i386-init.h: Regenerated.
1142 * i386-tbl.h: Likewise.
1144 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1147 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1148 (opcode_modifiers): Add AMD64 and Intel64.
1149 (main): Properly verify CpuMax.
1150 * i386-opc.h (CpuAMD64): Removed.
1151 (CpuIntel64): Likewise.
1152 (CpuMax): Set to CpuNo64.
1153 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1155 (Intel64): Likewise.
1156 (i386_opcode_modifier): Add amd64 and intel64.
1157 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1159 * i386-init.h: Regenerated.
1160 * i386-tbl.h: Likewise.
1162 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1165 * i386-gen.c (main): Fail if CpuMax is incorrect.
1166 * i386-opc.h (CpuMax): Set to CpuIntel64.
1167 * i386-tbl.h: Regenerated.
1169 2016-05-27 Nick Clifton <nickc@redhat.com>
1172 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1173 (msp430dis_opcode_unsigned): New function.
1174 (msp430dis_opcode_signed): New function.
1175 (msp430_singleoperand): Use the new opcode reading functions.
1176 Only disassenmble bytes if they were successfully read.
1177 (msp430_doubleoperand): Likewise.
1178 (msp430_branchinstr): Likewise.
1179 (msp430x_callx_instr): Likewise.
1180 (print_insn_msp430): Check that it is safe to read bytes before
1181 attempting disassembly. Use the new opcode reading functions.
1183 2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1185 * ppc-opc.c (CY): New define. Document it.
1186 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1188 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1190 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1191 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1192 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1193 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1195 * i386-init.h: Regenerated.
1197 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1200 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1201 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1202 * i386-init.h: Regenerated.
1204 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1206 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1207 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1208 * i386-init.h: Regenerated.
1210 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1212 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1214 (print_insn_arc): Set insn_type information.
1215 * arc-opc.c (C_CC): Add F_CLASS_COND.
1216 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1217 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1218 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1219 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1220 (brne, brne_s, jeq_s, jne_s): Likewise.
1222 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1224 * arc-tbl.h (neg): New instruction variant.
1226 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1228 * arc-dis.c (find_format, find_format, get_auxreg)
1229 (print_insn_arc): Changed.
1230 * arc-ext.h (INSERT_XOP): Likewise.
1232 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1234 * tic54x-dis.c (sprint_mmr): Adjust.
1235 * tic54x-opc.c: Likewise.
1237 2016-05-19 Alan Modra <amodra@gmail.com>
1239 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1241 2016-05-19 Alan Modra <amodra@gmail.com>
1243 * ppc-opc.c: Formatting.
1244 (NSISIGNOPT): Define.
1245 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1247 2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1249 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1250 replacing references to `micromips_ase' throughout.
1251 (_print_insn_mips): Don't use file-level microMIPS annotation to
1252 determine the disassembly mode with the symbol table.
1254 2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1256 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1258 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1260 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1262 * mips-opc.c (D34): New macro.
1263 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1265 2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1267 * i386-dis.c (prefix_table): Add RDPID instruction.
1268 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1269 (cpu_flags): Add RDPID bitfield.
1270 * i386-opc.h (enum): Add RDPID element.
1271 (i386_cpu_flags): Add RDPID field.
1272 * i386-opc.tbl: Add RDPID instruction.
1273 * i386-init.h: Regenerate.
1274 * i386-tbl.h: Regenerate.
1276 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1278 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1279 branch type of a symbol.
1280 (print_insn): Likewise.
1282 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1284 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1285 Mainline Security Extensions instructions.
1286 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1287 Extensions instructions.
1288 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1290 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1293 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1295 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1297 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1299 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1300 (arcExtMap_genOpcode): Likewise.
1301 * arc-opc.c (arg_32bit_rc): Define new variable.
1302 (arg_32bit_u6): Likewise.
1303 (arg_32bit_limm): Likewise.
1305 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1307 * aarch64-gen.c (VERIFIER): Define.
1308 * aarch64-opc.c (VERIFIER): Define.
1309 (verify_ldpsw): Use static linkage.
1310 * aarch64-opc.h (verify_ldpsw): Remove.
1311 * aarch64-tbl.h: Use VERIFIER for verifiers.
1313 2016-04-28 Nick Clifton <nickc@redhat.com>
1316 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1317 * aarch64-opc.c (verify_ldpsw): New function.
1318 * aarch64-opc.h (verify_ldpsw): New prototype.
1319 * aarch64-tbl.h: Add initialiser for verifier field.
1320 (LDPSW): Set verifier to verify_ldpsw.
1322 2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1326 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1327 smaller than address size.
1329 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1331 * alpha-dis.c: Regenerate.
1332 * crx-dis.c: Likewise.
1333 * disassemble.c: Likewise.
1334 * epiphany-opc.c: Likewise.
1335 * fr30-opc.c: Likewise.
1336 * frv-opc.c: Likewise.
1337 * ip2k-opc.c: Likewise.
1338 * iq2000-opc.c: Likewise.
1339 * lm32-opc.c: Likewise.
1340 * lm32-opinst.c: Likewise.
1341 * m32c-opc.c: Likewise.
1342 * m32r-opc.c: Likewise.
1343 * m32r-opinst.c: Likewise.
1344 * mep-opc.c: Likewise.
1345 * mt-opc.c: Likewise.
1346 * or1k-opc.c: Likewise.
1347 * or1k-opinst.c: Likewise.
1348 * tic80-opc.c: Likewise.
1349 * xc16x-opc.c: Likewise.
1350 * xstormy16-opc.c: Likewise.
1352 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1354 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1355 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1356 calcsd, and calcxd instructions.
1357 * arc-opc.c (insert_nps_bitop_size): Delete.
1358 (extract_nps_bitop_size): Delete.
1359 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1360 (extract_nps_qcmp_m3): Define.
1361 (extract_nps_qcmp_m2): Define.
1362 (extract_nps_qcmp_m1): Define.
1363 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1364 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1365 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1366 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1367 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1370 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1372 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1374 2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1376 * Makefile.in: Regenerated with automake 1.11.6.
1377 * aclocal.m4: Likewise.
1379 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1381 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1383 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1384 (extract_nps_cmem_uimm16): New function.
1385 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1387 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1389 * arc-dis.c (arc_insn_length): New function.
1390 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1391 (find_format): Change insnLen parameter to unsigned.
1393 2016-04-13 Nick Clifton <nickc@redhat.com>
1396 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1397 the LD.B and LD.BU instructions.
1399 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1401 * arc-dis.c (find_format): Check for extension flags.
1402 (print_flags): New function.
1403 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1405 * arc-ext.c (arcExtMap_coreRegName): Use
1406 LAST_EXTENSION_CORE_REGISTER.
1407 (arcExtMap_coreReadWrite): Likewise.
1408 (dump_ARC_extmap): Update printing.
1409 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1410 (arc_aux_regs): Add cpu field.
1411 * arc-regs.h: Add cpu field, lower case name aux registers.
1413 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1415 * arc-tbl.h: Add rtsc, sleep with no arguments.
1417 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1419 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1421 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1422 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1423 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1424 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1425 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1426 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1427 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1428 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1429 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1430 (arc_opcode arc_opcodes): Null terminate the array.
1431 (arc_num_opcodes): Remove.
1432 * arc-ext.h (INSERT_XOP): Define.
1433 (extInstruction_t): Likewise.
1434 (arcExtMap_instName): Delete.
1435 (arcExtMap_insn): New function.
1436 (arcExtMap_genOpcode): Likewise.
1437 * arc-ext.c (ExtInstruction): Remove.
1438 (create_map): Zero initialize instruction fields.
1439 (arcExtMap_instName): Remove.
1440 (arcExtMap_insn): New function.
1441 (dump_ARC_extmap): More info while debuging.
1442 (arcExtMap_genOpcode): New function.
1443 * arc-dis.c (find_format): New function.
1444 (print_insn_arc): Use find_format.
1445 (arc_get_disassembler): Enable dump_ARC_extmap only when
1448 2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1450 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1451 instruction bits out.
1453 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1455 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1456 * arc-opc.c (arc_flag_operands): Add new flags.
1457 (arc_flag_classes): Add new classes.
1459 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1461 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1463 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1465 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1466 encode1, rflt, crc16, and crc32 instructions.
1467 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1468 (arc_flag_classes): Add C_NPS_R.
1469 (insert_nps_bitop_size_2b): New function.
1470 (extract_nps_bitop_size_2b): Likewise.
1471 (insert_nps_bitop_uimm8): Likewise.
1472 (extract_nps_bitop_uimm8): Likewise.
1473 (arc_operands): Add new operand entries.
1475 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1477 * arc-regs.h: Add a new subclass field. Add double assist
1478 accumulator register values.
1479 * arc-tbl.h: Use DPA subclass to mark the double assist
1480 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1481 * arc-opc.c (RSP): Define instead of SP.
1482 (arc_aux_regs): Add the subclass field.
1484 2016-04-05 Jiong Wang <jiong.wang@arm.com>
1486 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1488 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
1490 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1493 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1495 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1496 issues. No functional changes.
1498 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1500 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1501 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1502 (RTT): Remove duplicate.
1503 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1504 (PCT_CONFIG*): Remove.
1505 (D1L, D1H, D2H, D2L): Define.
1507 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1509 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1511 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1513 * arc-tbl.h (invld07): Remove.
1514 * arc-ext-tbl.h: New file.
1515 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1516 * arc-opc.c (arc_opcodes): Add ext-tbl include.
1518 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1520 Fix -Wstack-usage warnings.
1521 * aarch64-dis.c (print_operands): Substitute size.
1522 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1524 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1526 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1527 to get a proper diagnostic when an invalid ASR register is used.
1529 2016-03-22 Nick Clifton <nickc@redhat.com>
1531 * configure: Regenerate.
1533 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1535 * arc-nps400-tbl.h: New file.
1536 * arc-opc.c: Add top level comment.
1537 (insert_nps_3bit_dst): New function.
1538 (extract_nps_3bit_dst): New function.
1539 (insert_nps_3bit_src2): New function.
1540 (extract_nps_3bit_src2): New function.
1541 (insert_nps_bitop_size): New function.
1542 (extract_nps_bitop_size): New function.
1543 (arc_flag_operands): Add nps400 entries.
1544 (arc_flag_classes): Add nps400 entries.
1545 (arc_operands): Add nps400 entries.
1546 (arc_opcodes): Add nps400 include.
1548 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1550 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1551 the new class enum values.
1553 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1555 * arc-dis.c (print_insn_arc): Handle nps400.
1557 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1559 * arc-opc.c (BASE): Delete.
1561 2016-03-18 Nick Clifton <nickc@redhat.com>
1564 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1565 of MOV insn that aliases an ORR insn.
1567 2016-03-16 Jiong Wang <jiong.wang@arm.com>
1569 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1571 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1573 * mcore-opc.h: Add const qualifiers.
1574 * microblaze-opc.h (struct op_code_struct): Likewise.
1575 * sh-opc.h: Likewise.
1576 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1577 (tic4x_print_op): Likewise.
1579 2016-03-02 Alan Modra <amodra@gmail.com>
1581 * or1k-desc.h: Regenerate.
1582 * fr30-ibld.c: Regenerate.
1583 * rl78-decode.c: Regenerate.
1585 2016-03-01 Nick Clifton <nickc@redhat.com>
1588 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1590 2016-02-24 Renlin Li <renlin.li@arm.com>
1592 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1593 (print_insn_coprocessor): Support fp16 instructions.
1595 2016-02-24 Renlin Li <renlin.li@arm.com>
1597 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1598 vminnm, vrint(mpna).
1600 2016-02-24 Renlin Li <renlin.li@arm.com>
1602 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1603 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1605 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1607 * i386-dis.c (print_insn): Parenthesize expression to prevent
1608 truncated addresses.
1611 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1612 Janek van Oirschot <jvanoirs@synopsys.com>
1614 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1617 2016-02-04 Nick Clifton <nickc@redhat.com>
1620 * msp430-dis.c (print_insn_msp430): Add a special case for
1621 decoding an RRC instruction with the ZC bit set in the extension
1624 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1626 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1627 * epiphany-ibld.c: Regenerate.
1628 * fr30-ibld.c: Regenerate.
1629 * frv-ibld.c: Regenerate.
1630 * ip2k-ibld.c: Regenerate.
1631 * iq2000-ibld.c: Regenerate.
1632 * lm32-ibld.c: Regenerate.
1633 * m32c-ibld.c: Regenerate.
1634 * m32r-ibld.c: Regenerate.
1635 * mep-ibld.c: Regenerate.
1636 * mt-ibld.c: Regenerate.
1637 * or1k-ibld.c: Regenerate.
1638 * xc16x-ibld.c: Regenerate.
1639 * xstormy16-ibld.c: Regenerate.
1641 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1643 * epiphany-dis.c: Regenerated from latest cpu files.
1645 2016-02-01 Michael McConville <mmcco@mykolab.com>
1647 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1650 2016-01-25 Renlin Li <renlin.li@arm.com>
1652 * arm-dis.c (mapping_symbol_for_insn): New function.
1653 (find_ifthen_state): Call mapping_symbol_for_insn().
1655 2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1657 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1658 of MSR UAO immediate operand.
1660 2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1662 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1663 instruction support.
1665 2016-01-17 Alan Modra <amodra@gmail.com>
1667 * configure: Regenerate.
1669 2016-01-14 Nick Clifton <nickc@redhat.com>
1671 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1672 instructions that can support stack pointer operations.
1673 * rl78-decode.c: Regenerate.
1674 * rl78-dis.c: Fix display of stack pointer in MOVW based
1677 2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1679 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1680 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1681 erxtatus_el1 and erxaddr_el1.
1683 2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1685 * arm-dis.c (arm_opcodes): Add "esb".
1686 (thumb_opcodes): Likewise.
1688 2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1690 * ppc-opc.c <xscmpnedp>: Delete.
1691 <xvcmpnedp>: Likewise.
1692 <xvcmpnedp.>: Likewise.
1693 <xvcmpnesp>: Likewise.
1694 <xvcmpnesp.>: Likewise.
1696 2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1699 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1702 2016-01-01 Alan Modra <amodra@gmail.com>
1704 Update year range in copyright notice of all files.
1706 For older changes see ChangeLog-2015
1708 Copyright (C) 2016 Free Software Foundation, Inc.
1710 Copying and distribution of this file, with or without modification,
1711 are permitted in any medium without royalty provided the copyright
1712 notice and this notice are preserved.
1718 version-control: never