opcodes/ChangeLog

   1 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
   2
   3         * arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support.
   4         (thumb32_opcodes): Likewise.
   5         (banked_regname): New function.
   6         (print_insn_arm): Add Virtualization Extensions support.
   7         (print_insn_thumb32): Likewise.
   8
   9 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  10
  11         * arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in
  12         ARM state.
  13
  14 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  15
  16         * arm-dis.c (arm_opcodes): SMC implies Security Extensions.
  17         (thumb32_opcodes): Likewise.
  18
  19 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  20
  21         * arm-dis.c (arm_opcodes): Add support for pldw.
  22         (thumb32_opcodes): Likewise.
  23
  24 2010-09-22  Robin Getz  <robin.getz@analog.com>
  25
  26         * bfin-dis.c (fmtconst): Cast address to 32bits.
  27
  28 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
  29
  30         * bfin-dis.c (decode_REGMV_0): Rewrite valid combo checks.
  31
  32 2010-09-22  Robin Getz  <robin.getz@analog.com>
  33
  34         * bfin-dis.c (decode_ProgCtrl_0): Check for parallel insns.
  35         Reject P6/P7 to TESTSET.
  36         (decode_PushPopReg_0): Check for parallel insns.  Reject pushing
  37         SP onto the stack.
  38         (decode_PushPopMultiple_0): Check for parallel insns.  Make sure
  39         P/D fields match all the time.
  40         (decode_CCflag_0): Check for parallel insns.  Verify x/y fields
  41         are 0 for accumulator compares.
  42         (decode_CC2stat_0): Check for parallel insns.  Reject CC<op>CC.
  43         (decode_CaCTRL_0, decode_ccMV_0, decode_CC2dreg_0, decode_BRCC_0,
  44         decode_UJUMP_0, decode_LOGI2op_0, decode_COMPI2opD_0,
  45         decode_COMPI2opP_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
  46         decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
  47         decode_pseudoOChar_0, decode_pseudodbg_assert_0): Check for parallel
  48         insns.
  49         (decode_dagMODim_0): Verify br field for IREG ops.
  50         (decode_LDST_0): Reject preg load into same preg.
  51         (_print_insn_bfin): Handle returns for ILLEGAL decodes.
  52         (print_insn_bfin): Likewise.
  53
  54 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
  55
  56         * bfin-dis.c (decode_PushPopMultiple_0): Return 0 when pr > 5.
  57
  58 2010-09-22  Robin Getz  <robin.getz@analog.com>
  59
  60         * bfin-dis.c (decode_dsp32shiftimm_0): Add missing "S" flag.
  61
  62 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
  63
  64         * bfin-dis.c (decode_CC2stat_0): Decode all ASTAT bits.
  65
  66 2010-09-22  Robin Getz  <robin.getz@analog.com>
  67
  68         * bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject
  69         register values greater than 8.
  70         (IS_RESERVEDREG, allreg, mostreg): New helpers.
  71         (decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate.
  72         (decode_PushPopReg_0): Call mostreg/allreg as appropriate.
  73         (decode_CC2dreg_0): Check valid CC register number.
  74
  75 2010-09-22  Robin Getz  <robin.getz@analog.com>
  76
  77         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG.
  78
  79 2010-09-22  Robin Getz  <robin.getz@analog.com>
  80
  81         * bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD.
  82         (reg_names): Likewise.
  83         (decode_statbits): Likewise; while reformatting to make manageable.
  84
  85 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
  86
  87         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC.
  88         (decode_pseudoOChar_0): New function.
  89         (_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0.
  90
  91 2010-09-22  Robin Getz  <robin.getz@analog.com>
  92
  93         * bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as
  94         LSHIFT instead of SHIFT.
  95
  96 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
  97
  98         * bfin-dis.c (constant_formats): Constify the whole structure.
  99         (fmtconst): Add const to return value.
 100         (reg_names): Mark const.
 101         (decode_multfunc): Mark s0/s1 as const.
 102         (decode_macfunc): Mark a/sop as const.
 103
 104 2010-09-17  Tejas Belagod  <tejas.belagod@arm.com>
 105
 106         * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
 107
 108 2010-09-14  Maciej W. Rozycki  <macro@codesourcery.com>
 109
 110         * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
 111         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
 112
 113 2010-09-10  Pierre Muller  <muller@ics.u-strasbg.fr>
 114
 115         * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for
 116         dlx_insn_type array.
 117
 118 2010-08-31  H.J. Lu  <hongjiu.lu@intel.com>
 119
 120         PR binutils/11960
 121         * i386-dis.c (sIv): New.
 122         (dis386): Replace Iq with sIv on "pushT".
 123         (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT.
 124         (x86_64_table): Replace {T|}/{P|} with P.
 125         (putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
 126         (OP_sI): Update v_mode.  Remove w_mode.
 127
 128 2010-08-27  Nathan Froyd  <froydnj@codesourcery.com>
 129
 130         * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
 131         on E500 and E500MC.
 132
 133 2010-08-17  H.J. Lu  <hongjiu.lu@intel.com>
 134
 135         * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and
 136         prefetchw.
 137
 138 2010-08-06  Quentin Neill <quentin.neill@amd.com>
 139
 140         * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
 141         to processor flags for PENTIUMPRO processors and later.
 142         * i386-opc.h (enum): Add CpuNop.
 143         (i386_cpu_flags): Add cpunop bit.
 144         * i386-opc.tbl: Change nop cpu_flags.
 145         * i386-init.h: Regenerated.
 146         * i386-tbl.h: Likewise.
 147
 148 2010-08-06  Quentin Neill <quentin.neill@amd.com>
 149
 150         * i386-opc.h (enum): Fix typos in comments.
 151
 152 2010-08-06  Alan Modra  <amodra@gmail.com>
 153
 154         * disassemble.c: Formatting.
 155         (disassemble_init_for_target <ARCH_m32c>): Comment on endian.
 156
 157 2010-08-05  H.J. Lu  <hongjiu.lu@intel.com>
 158
 159         * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
 160         * i386-tbl.h: Regenerated.
 161
 162 2010-08-05  H.J. Lu  <hongjiu.lu@intel.com>
 163
 164         * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1.
 165
 166         * i386-opc.tbl: Add ud1.  Remove Cpu686 from ud2/ud2a/ud2b.
 167         * i386-tbl.h: Regenerated.
 168
 169 2010-07-29  DJ Delorie  <dj@redhat.com>
 170
 171         * rx-decode.opc (SRR): New.
 172         (rx_decode_opcode): Use it for movbi and movbir.  Decode NOP2 (mov
 173         r0,r0) and NOP3 (max r0,r0) special cases.
 174         * rx-decode.c: Regenerate.
 175
 176 2010-07-28  H.J. Lu  <hongjiu.lu@intel.com>
 177
 178         * i386-dis.c: Add 0F to VEX opcode enums.
 179
 180 2010-07-27  DJ Delorie  <dj@redhat.com>
 181
 182         * rx-decode.opc (store_flags): Remove, replace with F_* macros.
 183         (rx_decode_opcode): Likewise.
 184         * rx-decode.c: Regenerate.
 185
 186 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 187             Ina Pandit  <ina.pandit@kpitcummins.com>
 188
 189         * v850-dis.c (v850_sreg_names): Updated structure for system
 190         registers.
 191         (float_cc_names): new structure for condition codes.
 192         (print_value): Update the function that prints value.
 193         (get_operand_value): New function to get the operand value.
 194         (disassemble): Updated to handle the disassembly of instructions.
 195         (print_insn_v850): Updated function to print instruction for different
 196         families.
 197         * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
 198         extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
 199         extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
 200         insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
 201         extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
 202         extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
 203         extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
 204         insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
 205         (insert_d8_7, insert_d5_4, insert_i5div): Remove.
 206         (v850_operands): Update with the relocation name. Also update
 207         the instructions with specific set of processors.
 208
 209 2010-07-08 Tejas Belagod <tejas.belagod@arm.com>
 210
 211         * arm-dis.c (print_insn_arm): Add cases for printing more
 212         symbolic operands.
 213         (print_insn_thumb32): Likewise.
 214
 215 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 216
 217         * mips-dis.c (print_insn_mips): Correct branch instruction type
 218         determination.
 219
 220 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 221
 222         * mips-dis.c (print_mips16_insn_arg): Remove branch instruction
 223         type and delay slot determination.
 224         (print_insn_mips16): Extend branch instruction type and delay
 225         slot determination to cover all instructions.
 226         * mips16-opc.c (BR): Remove macro.
 227         (UBR, CBR): New macros.
 228         (mips16_opcodes): Update branch annotation for "b", "beqz",
 229         "bnez", "bteqz" and "btnez".  Add branch annotation for "jalrc"
 230         and "jrc".
 231
 232 2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>
 233
 234         AVX Programming Reference (June, 2010)
 235         * i386-dis.c (mod_table): Replace rdrnd with rdrand.
 236         * i386-opc.tbl: Likewise.
 237         * i386-tbl.h: Regenerated.
 238
 239 2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>
 240
 241         * i386-opc.h (CpuFSGSBase): Fix a typo in comments.
 242
 243 2010-07-03  Andreas Schwab  <schwab@linux-m68k.org>
 244
 245         * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
 246         ppc_cpu_t before inverting.
 247         (ppc_parse_cpu): Likewise.
 248         (print_insn_powerpc): Likewise.
 249
 250 2010-07-03  Alan Modra  <amodra@gmail.com>
 251
 252         * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
 253         * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
 254         (PPC64, MFDEC2): Update.
 255         (NON32, NO371): Define.
 256         (powerpc_opcode): Update to not use old opcode flags, and avoid
 257         -m601 duplicates.
 258
 259 2010-07-03  DJ Delorie  <dj@delorie.com>
 260
 261         * m32c-ibld.c: Regenerate.
 262
 263 2010-07-03  Alan Modra  <amodra@gmail.com>
 264
 265         * ppc-opc.c (PWR2COM): Define.
 266         (PPCPWR2): Add PPC_OPCODE_COMMON.
 267         (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
 268         "fcirz", "fcirz." to -mcom opcodes.  Remove "mfsri", "dclst",
 269         "rac" from -mcom.
 270
 271 2010-07-01  H.J. Lu  <hongjiu.lu@intel.com>
 272
 273         AVX Programming Reference (June, 2010)
 274         * i386-dis.c (PREFIX_0FAE_REG_0): New.
 275         (PREFIX_0FAE_REG_1): Likewise.
 276         (PREFIX_0FAE_REG_2): Likewise.
 277         (PREFIX_0FAE_REG_3): Likewise.
 278         (PREFIX_VEX_3813): Likewise.
 279         (PREFIX_VEX_3A1D): Likewise.
 280         (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
 281         PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
 282         PREFIX_VEX_3A1D.
 283         (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
 284         (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
 285         PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
 286
 287         * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
 288         CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
 289         (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
 290
 291         * i386-opc.h (CpuXsaveopt): New.
 292         (CpuFSGSBase): Likewise.
 293         (CpuRdRnd): Likewise.
 294         (CpuF16C): Likewise.
 295         (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
 296         cpuf16c.
 297
 298         * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
 299         wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
 300         * i386-init.h: Regenerated.
 301         * i386-tbl.h: Likewise.
 302
 303 2010-07-01  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 304
 305         * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf
 306         and mtocrf on EFS.
 307
 308 2010-06-29  Alan Modra  <amodra@gmail.com>
 309
 310         * maxq-dis.c: Delete file.
 311         * Makefile.am: Remove references to maxq.
 312         * configure.in: Likewise.
 313         * disassemble.c: Likewise.
 314         * Makefile.in: Regenerate.
 315         * configure: Regenerate.
 316         * po/POTFILES.in: Regenerate.
 317
 318 2010-06-29  Alan Modra  <amodra@gmail.com>
 319
 320         * mep-dis.c: Regenerate.
 321
 322 2010-06-28  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 323
 324         * arm-disc.c (parse_insn_neon):  Fix Neon alignment syntax.
 325
 326 2010-06-27  Alan Modra  <amodra@gmail.com>
 327
 328         * arc-dis.c (arc_sprintf): Delete set but unused variables.
 329         (decodeInstr): Likewise.
 330         * dlx-dis.c (print_insn_dlx): Likewise.
 331         * h8300-dis.c (bfd_h8_disassemble_init): Likewise.
 332         * maxq-dis.c (check_move, print_insn): Likewise.
 333         * mep-dis.c (mep_examine_ivc2_insns): Likewise.
 334         * msp430-dis.c (msp430_branchinstr): Likewise.
 335         * bfin-dis.c (_print_insn_bfin): Avoid set but unused warning.
 336         * cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise.
 337         * sparc-dis.c (print_insn_sparc): Likewise.
 338         * fr30-asm.c: Regenerate.
 339         * frv-asm.c: Regenerate.
 340         * ip2k-asm.c: Regenerate.
 341         * iq2000-asm.c: Regenerate.
 342         * lm32-asm.c: Regenerate.
 343         * m32c-asm.c: Regenerate.
 344         * m32r-asm.c: Regenerate.
 345         * mep-asm.c: Regenerate.
 346         * mt-asm.c: Regenerate.
 347         * openrisc-asm.c: Regenerate.
 348         * xc16x-asm.c: Regenerate.
 349         * xstormy16-asm.c: Regenerate.
 350
 351 2010-06-16  Vincent Rivière  <vincent.riviere@freesbee.fr>
 352
 353         PR gas/11673
 354         * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later.
 355
 356 2010-06-16  Vincent Rivière  <vincent.riviere@freesbee.fr>
 357
 358         PR binutils/11676
 359         * m68k-dis.c (print_insn_arg): Prefix float constants with #0e.
 360
 361 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 362
 363         * ppc-dis.c (ppc_opts):  Remove PPC_OPCODE_E500MC from e500 and
 364         e500x2.  Add PPC_OPCODE_E500 to e500 and e500x2
 365         * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
 366         touch floating point regs and are enabled by COM, PPC or PPCCOM.
 367         Treat sync as msync on e500.  Treat eieio as mbar 1 on e500.
 368         Treat lwsync as msync on e500.
 369
 370 2010-06-07  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 371
 372         * arm-dis.c (thumb-opcodes): Add disassembly for movs.
 373
 374 2010-05-28  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 375
 376         * arm-dis.c (print_insn_neon):  Ensure disassembly of Neon
 377         constants is the same on 32-bit and 64-bit hosts.
 378
 379 2010-05-27  Jason Duerstock  <jason.duerstock+binutils@gmail.com>
 380
 381         * m68k-dis.c (print_insn_m68k): Emit undefined instructions as
 382         .short directives so that they can be reassembled.
 383
 384 2010-05-26  Catherine Moore <clm@codesourcery.com>
 385             David Ung  <davidu@mips.com>
 386
 387         * mips-opc.c: Change membership to I1 for instructions ssnop and
 388         ehb.
 389
 390 2010-05-26  H.J. Lu  <hongjiu.lu@intel.com>
 391
 392         * i386-dis.c (sib): New.
 393         (get_sib): Likewise.
 394         (print_insn): Call get_sib.
 395         OP_E_memory): Use sib.
 396
 397 2010-05-26  Catherine Moore  <clm@codesoourcery.com>
 398
 399         * mips-dis.c (mips_arch): Remove INSN_MIPS16.
 400         * mips-opc.c (I16): Remove.
 401         (mips_builtin_op): Reclassify jalx.
 402
 403 2010-05-19  Alan Modra  <amodra@gmail.com>
 404
 405         * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
 406         divwe, divdeuo, divweuo, divdeo, divweo for A2.  Add icswepx.
 407
 408 2010-05-13  Alan Modra  <amodra@gmail.com>
 409
 410         * ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
 411
 412 2010-05-11  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 413
 414         * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
 415         format.
 416         (print_insn_thumb16): Add support for new %W format.
 417
 418 2010-05-07  Tristan Gingold  <gingold@adacore.com>
 419
 420         * Makefile.in: Regenerate with automake 1.11.1.
 421         * aclocal.m4: Ditto.
 422
 423 2010-05-05  Nick Clifton  <nickc@redhat.com>
 424
 425         * po/es.po: Updated Spanish translation.
 426
 427 2010-04-22  Nick Clifton  <nickc@redhat.com>
 428
 429         * po/opcodes.pot: Updated by the Translation project.
 430         * po/vi.po: Updated Vietnamese translation.
 431
 432 2010-04-16  H.J. Lu  <hongjiu.lu@intel.com>
 433
 434         * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown
 435         bits in opcode.
 436
 437 2010-04-09  Nick Clifton  <nickc@redhat.com>
 438
 439         * i386-dis.c (print_insn): Remove unused variable op.
 440         (OP_sI): Remove unused variable mask.
 441
 442 2010-04-07  Alan Modra  <amodra@gmail.com>
 443
 444         * configure: Regenerate.
 445
 446 2010-04-06  Peter Bergner  <bergner@vnet.ibm.com>
 447
 448         * ppc-opc.c (RBOPT): New define.
 449         ("dccci"): Enable for PPCA2.  Make operands optional.
 450         ("iccci"): Likewise.  Do not deprecate for PPC476.
 451
 452 2010-04-02  Masaki Muranaka  <monaka@monami-software.com>
 453
 454         * cr16-opc.c (cr16_instruction): Fix typo in comment.
 455
 456 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 457
 458         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
 459         * Makefile.in: Regenerate.
 460         * configure.in (bfd_tic6x_arch): New.
 461         * configure: Regenerate.
 462         * disassemble.c (ARCH_tic6x): Define if ARCH_all.
 463         (disassembler): Handle TI C6X.
 464         * tic6x-dis.c: New.
 465
 466 2010-03-24  Mike Frysinger  <vapier@gentoo.org>
 467
 468         * bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2.
 469
 470 2010-03-23  Joseph Myers  <joseph@codesourcery.com>
 471
 472         * dis-buf.c (buffer_read_memory): Give error for reading just
 473         before the start of memory.
 474
 475 2010-03-22  Sebastian Pop  <sebastian.pop@amd.com>
 476             Quentin Neill <quentin.neill@amd.com>
 477
 478         * i386-dis.c (OP_LWP_I): Removed.
 479         (reg_table): Do not use OP_LWP_I, use Iq.
 480         (OP_LWPCB_E): Remove use of names16.
 481         (OP_LWP_E): Same.
 482         * i386-opc.tbl: Removed 16bit LWP insns.  32bit LWP insns
 483         should not set the Vex.length bit.
 484         * i386-tbl.h: Regenerated.
 485
 486 2010-02-25  Edmar Wienskoski  <edmar@freescale.com>
 487
 488         * ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64".
 489
 490 2010-02-24  Nick Clifton  <nickc@redhat.com>
 491
 492         PR binutils/6773
 493         * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with
 494         <prefix>asx.  Replace <prefix>subaddx with <prefix>sax.
 495         (thumb32_opcodes): Likewise.
 496
 497 2010-02-15  Nick Clifton  <nickc@redhat.com>
 498
 499         * po/vi.po: Updated Vietnamese translation.
 500
 501 2010-02-12  Doug Evans  <dje@sebabeach.org>
 502
 503         * lm32-opinst.c: Regenerate.
 504
 505 2010-02-11  Doug Evans  <dje@sebabeach.org>
 506
 507         * cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL.
 508         (print_address): Delete CGEN_PRINT_ADDRESS.
 509         * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c,
 510         * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h,
 511         * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c,
 512         * xc16x-dis.c, * xstormy16-dis.c: Regenerate.
 513
 514         * fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
 515         * frv-desc.c, * frv-desc.h, * frv-opc.c,
 516         * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
 517         * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
 518         * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
 519         * m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
 520         * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
 521         * mep-desc.c, * mep-desc.h, * mep-opc.c,
 522         * mt-desc.c, * mt-desc.h, * mt-opc.c,
 523         * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
 524         * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
 525         * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
 526
 527 2010-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 528
 529         * i386-dis.c: Update copyright.
 530         * i386-gen.c: Likewise.
 531         * i386-opc.h: Likewise.
 532         * i386-opc.tbl: Likewise.
 533
 534 2010-02-10  Quentin Neill  <quentin.neill@amd.com>
 535             Sebastian Pop  <sebastian.pop@amd.com>
 536
 537         * i386-dis.c (OP_EX_VexImmW): Reintroduced
 538         function to handle 5th imm8 operand.
 539         (PREFIX_VEX_3A48): Added.
 540         (PREFIX_VEX_3A49): Added.
 541         (VEX_W_3A48_P_2): Added.
 542         (VEX_W_3A49_P_2): Added.
 543         (prefix table): Added entries for PREFIX_VEX_3A48
 544         and PREFIX_VEX_3A49.
 545         (vex table): Added entries for VEX_W_3A48_P_2 and
 546         and VEX_W_3A49_P_2.
 547         * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
 548         for Vec_Imm4 operands.
 549         * i386-opc.h (enum): Added Vec_Imm4.
 550         (i386_operand_type): Added vec_imm4.
 551         * i386-opc.tbl: Add entries for vpermilp[ds].
 552         * i386-init.h: Regenerated.
 553         * i386-tbl.h: Regenerated.
 554
 555 2010-02-10  Richard Sandiford  <r.sandiford@uk.ibm.com>
 556
 557         * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
 558         and "pwr7".  Move "a2" into alphabetical order.
 559
 560 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 561
 562         * ppc-dis.c (ppc_opts): Add titan entry.
 563         * ppc-opc.c (TITAN, MULHW): Define.
 564         (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
 565
 566 2010-02-03  Quentin Neill  <quentin.neill@amd.com>
 567
 568         * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
 569         to CPU_BDVER1_FLAGS
 570         * i386-init.h: Regenerated.
 571
 572 2010-02-03  Anthony Green  <green@moxielogic.com>
 573
 574         * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to
 575         0x0f, and make 0x00 an illegal instruction.
 576
 577 2010-01-29  Daniel Jacobowitz  <dan@codesourcery.com>
 578
 579         * opcodes/arm-dis.c (struct arm_private_data): New.
 580         (print_insn_coprocessor, print_insn_arm): Update to use struct
 581         arm_private_data.
 582         (is_mapping_symbol, get_map_sym_type): New functions.
 583         (get_sym_code_type): Check the symbol's section.  Do not check
 584         mapping symbols.
 585         (print_insn): Default to disassembling ARM mode code.  Check
 586         for mapping symbols separately from other symbols.  Use
 587         struct arm_private_data.
 588
 589 2010-01-28  H.J. Lu  <hongjiu.lu@intel.com>
 590
 591         * i386-dis.c (EXVexWdqScalar): New.
 592         (vex_scalar_w_dq_mode): Likewise.
 593         (prefix_table): Update entries for PREFIX_VEX_3899,
 594         PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
 595         PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
 596         PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
 597         PREFIX_VEX_38BD and PREFIX_VEX_38BF.
 598         (intel_operand_size): Handle vex_scalar_w_dq_mode.
 599         (OP_EX): Likewise.
 600
 601 2010-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 602
 603         * i386-dis.c (XMScalar): New.
 604         (EXdScalar): Likewise.
 605         (EXqScalar): Likewise.
 606         (EXqScalarS): Likewise.
 607         (VexScalar): Likewise.
 608         (EXdVexScalarS): Likewise.
 609         (EXqVexScalarS): Likewise.
 610         (XMVexScalar): Likewise.
 611         (scalar_mode): Likewise.
 612         (d_scalar_mode): Likewise.
 613         (d_scalar_swap_mode): Likewise.
 614         (q_scalar_mode): Likewise.
 615         (q_scalar_swap_mode): Likewise.
 616         (vex_scalar_mode): Likewise.
 617         (vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
 618         VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
 619         VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
 620         VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
 621         VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
 622         VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
 623         VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
 624         VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
 625         VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
 626         VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
 627         (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
 628         VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
 629         VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
 630         VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
 631         VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
 632         VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
 633         VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
 634         VEX_W_7E_P_1, VEX_W_D6_P_2  VEX_W_C2_P_1, VEX_W_C2_P_3,
 635         VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
 636         (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
 637         q_scalar_mode, q_scalar_swap_mode.
 638         (OP_XMM): Handle scalar_mode.
 639         (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
 640         and q_scalar_swap_mode.
 641         (OP_VEX): Handle vex_scalar_mode.
 642
 643 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 644
 645         * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
 646
 647 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 648
 649         * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.
 650
 651 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 652
 653         * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
 654
 655 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 656
 657         * i386-dis.c (Bad_Opcode): New.
 658         (bad_opcode): Likewise.
 659         (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }.
 660         (dis386_twobyte): Likewise.
 661         (reg_table): Likewise.
 662         (prefix_table): Likewise.
 663         (x86_64_table): Likewise.
 664         (vex_len_table): Likewise.
 665         (vex_w_table): Likewise.
 666         (mod_table): Likewise.
 667         (rm_table): Likewise.
 668         (float_reg): Likewise.
 669         (reg_table): Remove trailing "(bad)" entries.
 670         (prefix_table): Likewise.
 671         (x86_64_table): Likewise.
 672         (vex_len_table): Likewise.
 673         (vex_w_table): Likewise.
 674         (mod_table): Likewise.
 675         (rm_table): Likewise.
 676         (get_valid_dis386): Handle bytemode 0.
 677
 678 2010-01-23  H.J. Lu  <hongjiu.lu@intel.com>
 679
 680         * i386-opc.h (VEXScalar): New.
 681
 682         * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
 683         instructions.
 684         * i386-tbl.h: Regenerated.
 685
 686 2010-01-21  H.J. Lu  <hongjiu.lu@intel.com>
 687
 688         * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor.
 689
 690         * i386-opc.tbl: Add xsave64 and xrstor64.
 691         * i386-tbl.h: Regenerated.
 692
 693 2010-01-20  Nick Clifton  <nickc@redhat.com>
 694
 695         PR 11170
 696         * arm-dis.c (print_arm_address): Do not ignore negative bit in PC
 697         based post-indexed addressing.
 698
 699 2010-01-15  Sebastian Pop  <sebastian.pop@amd.com>
 700
 701         * i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
 702         * i386-tbl.h: Regenerated.
 703
 704 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 705
 706         * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in
 707         comments.
 708
 709 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 710
 711         * i386-dis.c (names_mm): New.
 712         (intel_names_mm): Likewise.
 713         (att_names_mm): Likewise.
 714         (names_xmm): Likewise.
 715         (intel_names_xmm): Likewise.
 716         (att_names_xmm): Likewise.
 717         (names_ymm): Likewise.
 718         (intel_names_ymm): Likewise.
 719         (att_names_ymm): Likewise.
 720         (print_insn): Set names_mm, names_xmm and names_ymm.
 721         (OP_MMX): Use names_mm, names_xmm and names_ymm.
 722         (OP_XMM): Likewise.
 723         (OP_EM): Likewise.
 724         (OP_EMC): Likewise.
 725         (OP_MXC): Likewise.
 726         (OP_EX): Likewise.
 727         (XMM_Fixup): Likewise.
 728         (OP_VEX): Likewise.
 729         (OP_EX_VexReg): Likewise.
 730         (OP_Vex_2src): Likewise.
 731         (OP_Vex_2src_1): Likewise.
 732         (OP_Vex_2src_2): Likewise.
 733         (OP_REG_VexI4): Likewise.
 734
 735 2010-01-13  H.J. Lu  <hongjiu.lu@intel.com>
 736
 737         * i386-dis.c (print_insn): Update comments.
 738
 739 2010-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 740
 741         * i386-dis.c (rex_original): Removed.
 742         (ckprefix): Remove rex_original.
 743         (print_insn): Update comments.
 744
 745 2010-01-09  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 746
 747         * Makefile.in: Regenerate.
 748         * configure: Regenerate.
 749
 750 2010-01-07  Doug Evans  <dje@sebabeach.org>
 751
 752         * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
 753         * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
 754         * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
 755         * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
 756         * xstormy16-ibld.c: Regenerate.
 757
 758 2010-01-06  Quentin Neill  <quentin.neill@amd.com>
 759
 760         * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
 761         * i386-init.h: Regenerated.
 762
 763 2010-01-06  Daniel Gutson  <dgutson@codesourcery.com>
 764
 765         * arm-dis.c (print_insn): Fixed search for next symbol and data
 766         dumping condition, and the initial mapping symbol state.
 767
 768 2010-01-05  Doug Evans  <dje@sebabeach.org>
 769
 770         * cgen-ibld.in: #include "cgen/basic-modes.h".
 771         * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
 772         * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
 773         * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
 774         * xstormy16-ibld.c: Regenerate.
 775
 776 2010-01-04  Nick Clifton  <nickc@redhat.com>
 777
 778         PR 11123
 779         * arm-dis.c (print_insn_coprocessor): Initialise value.
 780
 781 2010-01-04  Edmar Wienskoski  <edmar@freescale.com>
 782
 783         * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
 784
 785 2010-01-02  Doug Evans  <dje@sebabeach.org>
 786
 787         * cgen-asm.in: Update copyright year.
 788         * cgen-dis.in: Update copyright year.
 789         * cgen-ibld.in: Update copyright year.
 790         * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
 791         * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
 792         * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
 793         * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
 794         * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
 795         * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
 796         * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
 797         * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
 798         * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
 799         * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
 800         * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
 801         * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
 802         * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
 803         * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
 804         * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
 805         * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
 806         * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
 807         * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
 808         * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
 809         * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
 810         * xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
 811
 812 For older changes see ChangeLog-2009
 813 \f
 814 Local Variables:
 815 mode: change-log
 816 left-margin: 8
 817 fill-column: 74
 818 version-control: never
 819 End: