opcodes/ChangeLog

   1 2013-09-30  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.
   4         * i386-init.h: Regenerated.
   5
   6 2013-09-30  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
   7
   8         * i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS.
   9         * i386-init.h: Regenerated.
  10
  11 2013-09-20  Alan Modra  <amodra@gmail.com>
  12
  13         * configure: Regenerate.
  14
  15 2013-09-17  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
  16
  17         * s390-opc.txt (clih): Make the immediate unsigned.
  18
  19 2013-09-04  Roland McGrath  <mcgrathr@google.com>
  20
  21         PR gas/15914
  22         * arm-dis.c (arm_opcodes): Add udf.
  23         (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
  24         (thumb32_opcodes): Add udf.w.
  25         (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
  26
  27 2013-09-02  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  28
  29         * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
  30         For the load fp integer instructions only the suppression flag was
  31         new with z196 version.
  32
  33 2013-08-28  Nick Clifton  <nickc@redhat.com>
  34
  35         * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
  36         immediate is not suitable for the 32-bit ABI.
  37
  38 2013-08-23  Maciej W. Rozycki  <macro@codesourcery.com>
  39
  40         * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
  41         replacing NODS.
  42
  43 2013-08-23  Yuri Chornoivan  <yurchor@ukr.net>
  44
  45         PR binutils/15834
  46         * aarch64-asm.c: Fix typos.
  47         * aarch64-dis.c: Likewise.
  48         * msp430-dis.c: Likewise.
  49
  50 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
  51
  52         * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
  53         macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
  54         Use +H rather than +C for the real "dext".
  55         * mips-opc.c (mips_builtin_opcodes): Likewise.
  56
  57 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
  58
  59         * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
  60         * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
  61         and OPTIONAL_MAPPED_REG.
  62         * mips-opc.c (decode_mips_operand): Likewise.
  63         * mips16-opc.c (decode_mips16_operand): Likewise.
  64         * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
  65
  66 2013-08-19  H.J. Lu  <hongjiu.lu@intel.com>
  67
  68         * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
  69         (PREFIX_EVEX_0F3A3F): Likewise.
  70         * i386-dis-evex.h (evex_table): Updated.
  71
  72 2013-08-06  Jürgen Urban  <JuergenUrban@gmx.de>
  73
  74         * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
  75         VCLIPW.
  76
  77 2013-08-05  Eric Botcazou  <ebotcazou@adacore.com>
  78             Konrad Eisele  <konrad@gaisler.com>
  79
  80         * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
  81         bfd_mach_sparc.
  82         * sparc-opc.c (MASK_LEON): Define.
  83         (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
  84         (letandleon): New macro.
  85         (v9andleon): Likewise.
  86         (sparc_opc): Add leon.
  87         (umac): Enable for letandleon.
  88         (smac): Likewise.
  89         (casa): Enable for v9andleon.
  90         (cas): Likewise.
  91         (casl): Likewise.
  92
  93 2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
  94             Richard Sandiford  <rdsandiford@googlemail.com>
  95
  96         * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
  97         OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
  98         (print_vu0_channel): New function.
  99         (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
 100         (print_insn_args): Handle '#'.
 101         (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
 102         * mips-opc.c (mips_vu0_channel_mask): New constant.
 103         (decode_mips_operand): Handle new VU0 operand types.
 104         (VU0, VU0CH): New macros.
 105         (mips_builtin_opcodes): Add VU0 opcodes.  Use "+7" rather than "E"
 106         for LQC2 and SQC2.  Use "+9" rather than "G" for EE CFC2 and CTC2.
 107         Use "+6" rather than "G" for QMFC2 and QMTC2.
 108
 109 2013-08-03  Richard Sandiford  <rdsandiford@googlemail.com>
 110
 111         * mips-formats.h (PCREL): Reorder parameters and update the definition
 112         to match new mips_pcrel_operand layout.
 113         (JUMP, JALX, BRANCH): Update accordingly.
 114         * mips16-opc.c (decode_mips16_operand): Likewise.
 115
 116 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 117
 118         * micromips-opc.c (WR_s): Delete.
 119
 120 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 121
 122         * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
 123         New macros.
 124         (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
 125         (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
 126         (mips_builtin_opcodes): Use the new position-based read-write flags
 127         instead of field-based ones.  Use UDI for "udi..." instructions.
 128         * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
 129         New macros.
 130         (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
 131         (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
 132         (WR_SP, RD_16): New macros.
 133         (RD_SP): Redefine as an INSN2_* flag.
 134         (MOD_SP): Redefine in terms of RD_SP and WR_SP.
 135         (mips16_opcodes): Use the new position-based read-write flags
 136         instead of field-based ones.  Use RD_16 for "nop".  Move RD_SP to
 137         pinfo2 field.
 138         * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
 139         New macros.
 140         (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
 141         (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
 142         (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
 143         (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
 144         (micromips_opcodes): Use the new position-based read-write flags
 145         instead of field-based ones.
 146         * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
 147         (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
 148         of field-based flags.
 149
 150 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 151
 152         * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
 153         (WR_SP): Replace with...
 154         (MOD_SP): ...this.
 155         (mips16_opcodes): Update accordingly.
 156         * mips-dis.c (print_insn_mips16): Likewise.
 157
 158 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 159
 160         * mips16-opc.c (mips16_opcodes): Reformat.
 161
 162 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 163
 164         * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
 165         for operands that are hard-coded to $0.
 166         * micromips-opc.c (micromips_opcodes): Likewise.
 167
 168 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 169
 170         * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
 171         for the single-operand forms of JALR and JALR.HB.
 172         * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
 173         and JALRS.HB.
 174
 175 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 176
 177         * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
 178         instructions.  Fix them to use WR_MACC instead of WR_CC and
 179         add missing RD_MACCs.
 180
 181 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 182
 183         * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
 184
 185 2013-07-29  Peter Bergner <bergner@vnet.ibm.com>
 186
 187         * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
 188
 189 2013-07-26  Sergey Guriev  <sergey.s.guriev@intel.com>
 190             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 191             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 192             Sergey Lega  <sergey.s.lega@intel.com>
 193             Anna Tikhonova  <anna.tikhonova@intel.com>
 194             Ilya Tocar  <ilya.tocar@intel.com>
 195             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 196             Ilya Verbin  <ilya.verbin@intel.com>
 197             Kirill Yukhin  <kirill.yukhin@intel.com>
 198             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 199
 200         * i386-dis-evex.h: New.
 201         * i386-dis.c (OP_Rounding): New.
 202         (VPCMP_Fixup): New.
 203         (OP_Mask): New.
 204         (Rdq): New.
 205         (XMxmmq): New.
 206         (EXdScalarS): New.
 207         (EXymm): New.
 208         (EXEvexHalfBcstXmmq): New.
 209         (EXxmm_mdq): New.
 210         (EXEvexXGscat): New.
 211         (EXEvexXNoBcst): New.
 212         (VPCMP): New.
 213         (EXxEVexR): New.
 214         (EXxEVexS): New.
 215         (XMask): New.
 216         (MaskG): New.
 217         (MaskE): New.
 218         (MaskR): New.
 219         (MaskVex): New.
 220         (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
 221         evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
 222         evex_rounding_mode, evex_sae_mode, mask_mode.
 223         (USE_EVEX_TABLE): New.
 224         (EVEX_TABLE): New.
 225         (EVEX enum): New.
 226         (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
 227         REG_EVEX_0F38C7.
 228         (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
 229         MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
 230         MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
 231         MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 232         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,  MOD_EVEX_0F38C7_REG_5,
 233         MOD_EVEX_0F38C7_REG_6.
 234         (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 235         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
 236         PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 237         PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
 238         PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
 239         PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
 240         PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
 241         PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
 242         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
 243         PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
 244         PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
 245         PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
 246         PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
 247         PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
 248         PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
 249         PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
 250         PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
 251         PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
 252         PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
 253         PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
 254         PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
 255         PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
 256         PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
 257         PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
 258         PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
 259         PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
 260         PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
 261         PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
 262         PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
 263         PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
 264         PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
 265         PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
 266         PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
 267         PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
 268         PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
 269         PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
 270         PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
 271         PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
 272         PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
 273         PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
 274         PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
 275         PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
 276         PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
 277         PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
 278         PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
 279         PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
 280         PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
 281         PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
 282         PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
 283         PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
 284         PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
 285         PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
 286         PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
 287         PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
 288         PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
 289         PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
 290         PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
 291         PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
 292         PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
 293         PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
 294         PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
 295         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
 296         PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
 297         PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
 298         PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
 299         PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
 300         PREFIX_EVEX_0F3A00,  PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
 301         PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
 302         PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
 303         PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
 304         PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
 305         PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
 306         PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
 307         PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
 308         PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
 309         PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
 310         PREFIX_EVEX_0F3A55.
 311         (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
 312         VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
 313         VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
 314         VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
 315         VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
 316         VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
 317         VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
 318         VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
 319         VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
 320         VEX_W_0F3A32_P_2_LEN_0.
 321         (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
 322         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
 323         EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
 324         EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
 325         EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
 326         EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 327         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
 328         EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
 329         EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 330         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
 331         EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 332         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
 333         EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
 334         EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
 335         EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
 336         EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
 337         EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
 338         EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
 339         EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
 340         EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
 341         EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
 342         EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
 343         EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
 344         EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
 345         EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
 346         EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
 347         EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
 348         EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
 349         EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
 350         EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
 351         EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
 352         EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
 353         EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
 354         EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
 355         EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
 356         EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
 357         EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
 358         EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
 359         EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
 360         EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
 361         EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
 362         EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
 363         EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
 364         EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
 365         EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
 366         EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
 367         EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
 368         EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
 369         EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
 370         EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
 371         EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
 372         EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
 373         EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
 374         EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
 375         (struct vex): Add fields evex, r, v, mask_register_specifier,
 376         zeroing, ll, b.
 377         (intel_names_xmm): Add upper 16 registers.
 378         (att_names_xmm): Ditto.
 379         (intel_names_ymm): Ditto.
 380         (att_names_ymm): Ditto.
 381         (names_zmm): New.
 382         (intel_names_zmm): Ditto.
 383         (att_names_zmm): Ditto.
 384         (names_mask): Ditto.
 385         (intel_names_mask): Ditto.
 386         (att_names_mask): Ditto.
 387         (names_rounding): Ditto.
 388         (names_broadcast): Ditto.
 389         (x86_64_table): Add escape to evex-table.
 390         (reg_table): Include reg_table evex-entries from
 391         i386-dis-evex.h.  Fix prefetchwt1 instruction.
 392         (prefix_table): Add entries for new instructions.
 393         (vex_table): Ditto.
 394         (vex_len_table): Ditto.
 395         (vex_w_table): Ditto.
 396         (mod_table): Ditto.
 397         (get_valid_dis386): Properly handle new instructions.
 398         (print_insn): Handle zmm and mask registers, print mask operand.
 399         (intel_operand_size): Support EVEX, new modes and sizes.
 400         (OP_E_register): Handle new modes.
 401         (OP_E_memory): Ditto.
 402         (OP_G): Ditto.
 403         (OP_XMM): Ditto.
 404         (OP_EX): Ditto.
 405         (OP_VEX): Ditto.
 406         * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
 407         CPU_ANY_AVX_FLAGS.  Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
 408         CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 409         (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
 410         CpuAVX512PF and CpuVREX.
 411         (operand_type_init): Add OPERAND_TYPE_REGZMM,
 412         OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
 413         (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
 414         StaticRounding, SAE, Disp8MemShift, NoDefMask.
 415         (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
 416         * i386-init.h: Regenerate.
 417         * i386-opc.h (CpuAVX512F): New.
 418         (CpuAVX512CD): New.
 419         (CpuAVX512ER): New.
 420         (CpuAVX512PF): New.
 421         (CpuVREX): New.
 422         (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
 423         cpuavx512pf and cpuvrex fields.
 424         (VecSIB): Add VecSIB512.
 425         (EVex): New.
 426         (Masking): New.
 427         (VecESize): New.
 428         (Broadcast): New.
 429         (StaticRounding): New.
 430         (SAE): New.
 431         (Disp8MemShift): New.
 432         (NoDefMask): New.
 433         (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
 434         staticrounding, sae, disp8memshift and nodefmask.
 435         (RegZMM): New.
 436         (Zmmword): Ditto.
 437         (Vec_Disp8): Ditto.
 438         (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
 439         fields.
 440         (RegVRex): New.
 441         * i386-opc.tbl: Add AVX512 instructions.
 442         * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
 443         registers, mask registers.
 444         * i386-tbl.h: Regenerate.
 445
 446 2013-07-25  Aaro Koskinen  <aaro.koskinen@iki.fi>
 447
 448         PR gas/15220
 449         * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
 450         Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
 451
 452 2013-07-25  Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 453
 454         * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
 455         PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
 456         PREFIX_0F3ACC.
 457         (prefix_table): Updated.
 458         (three_byte_table): Likewise.
 459         * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
 460         (cpu_flags): Add CpuSHA.
 461         (i386_cpu_flags): Add cpusha.
 462         * i386-init.h: Regenerate.
 463         * i386-opc.h (CpuSHA): New.
 464         (CpuUnused): Restored.
 465         (i386_cpu_flags): Add cpusha.
 466         * i386-opc.tbl: Add SHA instructions.
 467         * i386-tbl.h: Regenerate.
 468
 469 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
 470             Kirill Yukhin  <kirill.yukhin@intel.com>
 471             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 472
 473         * i386-dis.c (BND_Fixup): New.
 474         (Ebnd): New.
 475         (Ev_bnd): New.
 476         (Gbnd): New.
 477         (BND): New.
 478         (v_bnd_mode): New.
 479         (bnd_mode): New.
 480         (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
 481         MOD_0F1B_PREFIX_1.
 482         (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
 483         (dis tables): Replace XX with BND for near branch and call
 484         instructions.
 485         (prefix_table): Add new entries.
 486         (mod_table): Likewise.
 487         (names_bnd): New.
 488         (intel_names_bnd): New.
 489         (att_names_bnd): New.
 490         (BND_PREFIX): New.
 491         (prefix_name): Handle BND_PREFIX.
 492         (print_insn): Initialize names_bnd.
 493         (intel_operand_size): Handle new modes.
 494         (OP_E_register): Likewise.
 495         (OP_E_memory): Likewise.
 496         (OP_G): Likewise.
 497         * i386-gen.c (cpu_flag_init): Add CpuMPX.
 498         (cpu_flags): Add CpuMPX.
 499         (operand_type_init): Add RegBND.
 500         (opcode_modifiers): Add BNDPrefixOk.
 501         (operand_types): Add RegBND.
 502         * i386-init.h: Regenerate.
 503         * i386-opc.h (CpuMPX): New.
 504         (CpuUnused): Comment out.
 505         (i386_cpu_flags): Add cpumpx.
 506         (BNDPrefixOk): New.
 507         (i386_opcode_modifier): Add bndprefixok.
 508         (RegBND): New.
 509         (i386_operand_type): Add regbnd.
 510         * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
 511         Add MPX instructions and bnd prefix.
 512         * i386-reg.tbl: Add bnd0-bnd3 registers.
 513         * i386-tbl.h: Regenerate.
 514
 515 2013-07-17  Richard Sandiford  <rdsandiford@googlemail.com>
 516
 517         * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
 518         ATTRIBUTE_UNUSED.
 519
 520 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 521
 522         * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
 523         special rules.
 524         * Makefile.in: Regenerate.
 525         * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
 526         all fields.  Reformat.
 527
 528 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 529
 530         * mips16-opc.c: Include mips-formats.h.
 531         (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
 532         static arrays.
 533         (decode_mips16_operand): New function.
 534         * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
 535         (print_insn_arg): Handle OP_ENTRY_EXIT list.
 536         Abort for OP_SAVE_RESTORE_LIST.
 537         (print_mips16_insn_arg): Change interface.  Use mips_operand
 538         structures.  Delete GET_OP_S.  Move GET_OP definition to...
 539         (print_insn_mips16): ...here.  Call init_print_arg_state.
 540         Update the call to print_mips16_insn_arg.
 541
 542 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 543
 544         * mips-formats.h: New file.
 545         * mips-opc.c: Include mips-formats.h.
 546         (reg_0_map): New static array.
 547         (decode_mips_operand): New function.
 548         * micromips-opc.c: Remove <stdio.h> include.  Include mips-formats.h.
 549         (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
 550         (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
 551         (int_c_map): New static arrays.
 552         (decode_micromips_operand): New function.
 553         * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
 554         (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
 555         (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
 556         (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
 557         (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
 558         (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
 559         (micromips_imm_b_map, micromips_imm_c_map): Delete.
 560         (print_reg): New function.
 561         (mips_print_arg_state): New structure.
 562         (init_print_arg_state, print_insn_arg): New functions.
 563         (print_insn_args): Change interface and use mips_operand structures.
 564         Delete GET_OP_S.  Move GET_OP definition to...
 565         (print_insn_mips): ...here.  Update the call to print_insn_args.
 566         (print_insn_micromips): Use print_insn_args.
 567
 568 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 569
 570         * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
 571         in macros.
 572
 573 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 574
 575         * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
 576         ADDA.S, MULA.S and SUBA.S.
 577
 578 2013-07-08  H.J. Lu  <hongjiu.lu@intel.com>
 579
 580         PR gas/13572
 581         * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
 582         * i386-tbl.h: Regenerated.
 583
 584 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 585
 586         * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros.  Move LD
 587         and SD A(B) macros up.
 588         * micromips-opc.c (micromips_opcodes): Likewise.
 589
 590 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 591
 592         * mips16-opc.c: Add entries for argumentless "entry" and "exit"
 593         instructions.
 594
 595 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 596
 597         * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
 598         MDMX-like instructions.
 599         * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
 600         printing "Q" operands for INSN_5400 instructions.
 601
 602 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 603
 604         * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
 605         "+S" for "cins".
 606         * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
 607         Combine cases.
 608
 609 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 610
 611         * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
 612         "jalx".
 613         * mips16-opc.c (mips16_opcodes): Likewise.
 614         * micromips-opc.c (micromips_opcodes): Likewise.
 615         * mips-dis.c (print_insn_args, print_mips16_insn_arg)
 616         (print_insn_mips16): Handle "+i".
 617         (print_insn_micromips): Likewise.  Conditionally preserve the
 618         ISA bit for "a" but not for "+i".
 619
 620 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 621
 622         * micromips-opc.c (WR_mhi): Rename to..
 623         (WR_mh): ...this.
 624         (micromips_opcodes): Update "movep" entry accordingly.  Replace
 625         "mh,mi" with "mh".
 626         * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
 627         (micromips_to_32_reg_h_map1): ...this.
 628         (micromips_to_32_reg_i_map): Rename to...
 629         (micromips_to_32_reg_h_map2): ...this.
 630         (print_micromips_insn): Remove "mi" case.  Print both registers
 631         in the pair for "mh".
 632
 633 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 634
 635         * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
 636         * micromips-opc.c (micromips_opcodes): Likewise.
 637         * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
 638         and "+T" handling.  Check for a "0" suffix when deciding whether to
 639         use coprocessor 0 names.  In that case, also check for ",H" selectors.
 640
 641 2013-07-05  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 642
 643         * s390-opc.c (J12_12, J24_24): New macros.
 644         (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
 645         (MASK_MII_UPI): Rename to MASK_MII_UPP.
 646         * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
 647
 648 2013-07-04  Alan Modra  <amodra@gmail.com>
 649
 650         * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
 651
 652 2013-06-26  Nick Clifton  <nickc@redhat.com>
 653
 654         * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
 655         field when checking for type 2 nop.
 656         * rx-decode.c: Regenerate.
 657
 658 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
 659
 660         * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
 661         and "movep" macros.
 662
 663 2013-06-24  Maciej W. Rozycki  <macro@codesourcery.com>
 664
 665         * mips-dis.c (is_mips16_plt_tail): New function.
 666         (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
 667         word.
 668         (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
 669
 670 2013-06-21  DJ Delorie  <dj@redhat.com>
 671
 672         * msp430-decode.opc: New.
 673         * msp430-decode.c: New/generated.
 674         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
 675         (MAINTAINER_CLEANFILES): Likewise.
 676         Add rule to build msp430-decode.c frommsp430decode.opc
 677         using the opc2c program.
 678         * Makefile.in: Regenerate.
 679         * configure.in: Add msp430-decode.lo to msp430 architecture files.
 680         * configure: Regenerate.
 681
 682 2013-06-20  Yufeng Zhang  <yufeng.zhang@arm.com>
 683
 684         * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
 685         (SYMTAB_AVAILABLE): Removed.
 686         (#include "elf/aarch64.h): Ditto.
 687
 688 2013-06-17  Catherine Moore  <clm@codesourcery.com>
 689             Maciej W. Rozycki  <macro@codesourcery.com>
 690             Chao-Ying Fu  <fu@mips.com>
 691
 692         * micromips-opc.c (EVA): Define.
 693         (TLBINV): Define.
 694         (micromips_opcodes): Add EVA opcodes.
 695         * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
 696         (print_insn_args): Handle EVA offsets.
 697         (print_insn_micromips): Likewise.
 698         * mips-opc.c (EVA): Define.
 699         (TLBINV): Define.
 700         (mips_builtin_opcodes): Add EVA opcodes.
 701
 702 2013-06-17  Alan Modra  <amodra@gmail.com>
 703
 704         * Makefile.am (mips-opc.lo): Add rules to create automatic
 705         dependency files.  Pass archdefs.
 706         (micromips-opc.lo, mips16-opc.lo): Likewise.
 707         * Makefile.in: Regenerate.
 708
 709 2013-06-14  DJ Delorie  <dj@redhat.com>
 710
 711         * rx-decode.opc (rx_decode_opcode): Bit operations on
 712         registers are 32-bit operations, not 8-bit operations.
 713         * rx-decode.c: Regenerate.
 714
 715 2013-06-13  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 716
 717         * micromips-opc.c (IVIRT): New define.
 718         (IVIRT64): New define.
 719         (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 720         tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
 721
 722         * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
 723         dmtgc0 to print cp0 names.
 724
 725 2013-06-09  Sandra Loosemore  <sandra@codesourcery.com>
 726
 727         * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
 728         argument.
 729
 730 2013-06-08  Catherine Moore  <clm@codesourcery.com>
 731             Richard Sandiford  <rdsandiford@googlemail.com>
 732
 733         * micromips-opc.c (D32, D33, MC): Update definitions.
 734         (micromips_opcodes):  Initialize ase field.
 735         * mips-dis.c (mips_arch_choice): Add ase field.
 736         (mips_arch_choices): Initialize ase field.
 737         (set_default_mips_dis_options): Declare and setup mips_ase.
 738         * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
 739         MT32, MC): Update definitions.
 740         (mips_builtin_opcodes): Initialize ase field.
 741
 742 2013-05-24  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 743
 744         * s390-opc.txt (flogr): Require a register pair destination.
 745
 746 2013-05-23  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 747
 748         * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
 749         instruction format.
 750
 751 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 752
 753         * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
 754
 755 2013-05-20  Peter Bergner <bergner@vnet.ibm.com>
 756
 757         * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
 758         * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
 759         XLS_MASK, PPCVSX2): New defines.
 760         (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
 761         fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
 762         mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
 763         mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
 764         mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
 765         vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
 766         vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
 767         vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
 768         vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
 769         vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
 770         vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
 771         vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
 772         vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
 773         vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
 774         xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
 775         xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
 776         xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
 777         xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
 778         <lxvx, stxvx>: New extended mnemonics.
 779
 780 2013-05-17  Alan Modra  <amodra@gmail.com>
 781
 782         * ia64-raw.tbl: Replace non-ASCII char.
 783         * ia64-waw.tbl: Likewise.
 784         * ia64-asmtab.c: Regenerate.
 785
 786 2013-05-15  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 787
 788         * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
 789         * i386-init.h: Regenerated.
 790
 791 2013-05-13  Yufeng Zhang  <yufeng.zhang@arm.com>
 792
 793         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
 794         * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
 795         check from [0, 255] to [-128, 255].
 796
 797 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 798
 799         * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
 800         Add INSN_VIRT and INSN_VIRT64 to mips64r2.
 801         (parse_mips_dis_option): Handle the virt option.
 802         (print_insn_args): Handle "+J".
 803         (print_mips_disassembler_options): Print out message about virt64.
 804         * mips-opc.c (IVIRT): New define.
 805         (IVIRT64): New define.
 806         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 807         tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
 808         Move rfe to the bottom as it conflicts with tlbgp.
 809
 810 2013-05-09  Alan Modra  <amodra@gmail.com>
 811
 812         * ppc-opc.c (extract_vlesi): Properly sign extend.
 813         (extract_vlensi): Likewise.  Comment reason for setting invalid.
 814
 815 2013-05-02  Nick Clifton  <nickc@redhat.com>
 816
 817         * msp430-dis.c: Add support for MSP430X instructions.
 818
 819 2013-04-24  Sandra Loosemore  <sandra@codesourcery.com>
 820
 821         * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
 822         to "eccinj".
 823
 824 2013-04-17  Wei-chen Wang  <cole945@gmail.com>
 825
 826         PR binutils/15369
 827         * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
 828         of CGEN_CPU_ENDIAN.
 829         (hash_insns_list): Likewise.
 830
 831 2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>
 832
 833         * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
 834         warning workaround.
 835
 836 2013-04-08  Jan Beulich <jbeulich@suse.com>
 837
 838         * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
 839         * i386-tbl.h: Re-generate.
 840
 841 2013-04-06  David S. Miller  <davem@davemloft.net>
 842
 843         * sparc-dis.c (compare_opcodes): When encountering multiple aliases
 844         of an opcode, prefer the one with F_PREFERRED set.
 845         * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
 846         lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
 847         ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
 848         mark existing mnenomics as aliases.  Add "cc" suffix to edge
 849         instructions generating condition codes, mark existing mnenomics
 850         as aliases.  Add "fp" prefix to VIS compare instructions, mark
 851         existing mnenomics as aliases.
 852
 853 2013-04-03  Nick Clifton  <nickc@redhat.com>
 854
 855         * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
 856         destination address by subtracting the operand from the current
 857         address.
 858         * v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
 859         a positive value in the insn.
 860         (extract_u16_loop): Do not negate the returned value.
 861         (D16_LOOP): Add V850_INVERSE_PCREL flag.
 862
 863         (ceilf.sw): Remove duplicate entry.
 864         (cvtf.hs): New entry.
 865         (cvtf.sh): Likewise.
 866         (fmaf.s): Likewise.
 867         (fmsf.s): Likewise.
 868         (fnmaf.s): Likewise.
 869         (fnmsf.s): Likewise.
 870         (maddf.s): Restrict to E3V5 architectures.
 871         (msubf.s): Likewise.
 872         (nmaddf.s): Likewise.
 873         (nmsubf.s): Likewise.
 874
 875 2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>
 876
 877         * i386-dis.c (get_sib): Add the sizeflag argument.  Properly
 878         check address mode.
 879         (print_insn): Pass sizeflag to get_sib.
 880
 881 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 882
 883         PR binutils/15068
 884         * tic6x-dis.c: Add support for displaying 16-bit insns.
 885
 886 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 887
 888         PR gas/15095
 889         * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
 890         individual msb and lsb halves in src1 & src2 fields.  Discard the
 891         src1 (lsb) value and only use src2 (msb), discarding bit 0, to
 892         follow what Ti SDK does in that case as any value in the src1
 893         field yields the same output with SDK disassembler.
 894
 895 2013-03-12  Michael Eager <eager@eagercon.com>
 896
 897         * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
 898
 899 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 900
 901         * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
 902
 903 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 904
 905         * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
 906
 907 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 908
 909         * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
 910
 911 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 912
 913         * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
 914         (thumb32_opcodes): Likewise.
 915         (print_insn_thumb32): Handle 'S' control char.
 916
 917 2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
 918
 919         * lm32-desc.c: Regenerate.
 920
 921 2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 922
 923         * i386-reg.tbl (riz): Add RegRex64.
 924         * i386-tbl.h: Regenerated.
 925
 926 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 927
 928         * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
 929         (aarch64_feature_crc): New static.
 930         (CRC): New macro.
 931         (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
 932         crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
 933         * aarch64-asm-2.c: Re-generate.
 934         * aarch64-dis-2.c: Ditto.
 935         * aarch64-opc-2.c: Ditto.
 936
 937 2013-02-27  Alan Modra  <amodra@gmail.com>
 938
 939         * rl78-decode.opc (rl78_decode_opcode): Fix typo.
 940         * rl78-decode.c: Regenerate.
 941
 942 2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
 943
 944         * rl78-decode.opc: Fix encoding of DIVWU insn.
 945         * rl78-decode.c: Regenerate.
 946
 947 2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 948
 949         PR gas/15159
 950         * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
 951
 952         * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
 953         (cpu_flags): Add CpuSMAP.
 954
 955         * i386-opc.h (CpuSMAP): New.
 956         (i386_cpu_flags): Add cpusmap.
 957
 958         * i386-opc.tbl: Add clac and stac.
 959
 960         * i386-init.h: Regenerated.
 961         * i386-tbl.h: Likewise.
 962
 963 2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
 964
 965         * metag-dis.c: Initialize outf->bytes_per_chunk to 4
 966         which also makes the disassembler output be in little
 967         endian like it should be.
 968
 969 2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
 970
 971         * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
 972         fields to NULL.
 973         (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
 974
 975 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
 976
 977         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
 978         section disassembled.
 979
 980 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 981
 982         * arm-dis.c: Update strht pattern.
 983
 984 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
 985
 986         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
 987         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
 988         trunc.w.s macro for EE.
 989
 990 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
 991             Andrew Jenner <andrew@codesourcery.com>
 992
 993         Based on patches from Altera Corporation.
 994
 995         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
 996         nios2-opc.c.
 997         * Makefile.in: Regenerated.
 998         * configure.in: Add case for bfd_nios2_arch.
 999         * configure: Regenerated.
1000         * disassemble.c (ARCH_nios2): Define.
1001         (disassembler): Add case for bfd_arch_nios2.
1002         * nios2-dis.c: New file.
1003         * nios2-opc.c: New file.
1004
1005 2013-02-04  Alan Modra  <amodra@gmail.com>
1006
1007         * po/POTFILES.in: Regenerate.
1008         * rl78-decode.c: Regenerate.
1009         * rx-decode.c: Regenerate.
1010
1011 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
1012
1013         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
1014         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
1015         * aarch64-asm.c (convert_xtl_to_shll): New function.
1016         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1017         calling convert_xtl_to_shll.
1018         * aarch64-dis.c (convert_shll_to_xtl): New function.
1019         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1020         calling convert_shll_to_xtl.
1021         * aarch64-gen.c: Update copyright year.
1022         * aarch64-asm-2.c: Re-generate.
1023         * aarch64-dis-2.c: Re-generate.
1024         * aarch64-opc-2.c: Re-generate.
1025
1026 2013-01-24  Nick Clifton  <nickc@redhat.com>
1027
1028         * v850-dis.c: Add support for e3v5 architecture.
1029         * v850-opc.c: Likewise.
1030
1031 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
1032
1033         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
1034         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
1035         * aarch64-opc.c (operand_general_constraint_met_p): For
1036         AARCH64_MOD_LSL, move the range check on the shift amount before the
1037         alignment check; change to call set_sft_amount_out_of_range_error
1038         instead of set_imm_out_of_range_error.
1039         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
1040         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
1041         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
1042         SIMD_IMM_SFT.
1043
1044 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
1045
1046         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
1047
1048         * i386-init.h: Regenerated.
1049         * i386-tbl.h: Likewise.
1050
1051 2013-01-15  Nick Clifton  <nickc@redhat.com>
1052
1053         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
1054         values.
1055         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1056
1057 2013-01-14  Will Newton <will.newton@imgtec.com>
1058
1059         * metag-dis.c (REG_WIDTH): Increase to 64.
1060
1061 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
1062
1063         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1064         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1065         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1066         (SH6): Update.
1067         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1068         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1069         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1070         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1071
1072 2013-01-10  Will Newton <will.newton@imgtec.com>
1073
1074         * Makefile.am: Add Meta.
1075         * configure.in: Add Meta.
1076         * disassemble.c: Add Meta support.
1077         * metag-dis.c: New file.
1078         * Makefile.in: Regenerate.
1079         * configure: Regenerate.
1080
1081 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1082
1083         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1084         (match_opcode): Rename to cr16_match_opcode.
1085
1086 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
1087
1088         * mips-dis.c: Add names for CP0 registers of r5900.
1089         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1090         instructions sq and lq.
1091         Add support for MIPS r5900 CPU.
1092         Add support for 128 bit MMI (Multimedia Instructions).
1093         Add support for EE instructions (Emotion Engine).
1094         Disable unsupported floating point instructions (64 bit and
1095         undefined compare operations).
1096         Enable instructions of MIPS ISA IV which are supported by r5900.
1097         Disable 64 bit co processor instructions.
1098         Disable 64 bit multiplication and division instructions.
1099         Disable instructions for co-processor 2 and 3, because these are
1100         not supported (preparation for later VU0 support (Vector Unit)).
1101         Disable cvt.w.s because this behaves like trunc.w.s and the
1102         correct execution can't be ensured on r5900.
1103         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1104         will confuse less developers and compilers.
1105
1106 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1107
1108         * aarch64-opc.c (aarch64_print_operand): Change to print
1109         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1110         in comment.
1111         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1112         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1113         OP_MOV_IMM_WIDE.
1114
1115 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1116
1117         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1118         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
1119
1120 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
1121
1122         * i386-gen.c (process_copyright): Update copyright year to 2013.
1123
1124 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1125
1126         * cr16-dis.c (match_opcode,make_instruction): Remove static
1127         declaration.
1128         (dwordU,wordU): Moved typedefs to opcode/cr16.h
1129         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
1130
1131 For older changes see ChangeLog-2012
1132 \f
1133 Copyright (C) 2013 Free Software Foundation, Inc.
1134
1135 Copying and distribution of this file, with or without modification,
1136 are permitted in any medium without royalty provided the copyright
1137 notice and this notice are preserved.
1138
1139 Local Variables:
1140 mode: change-log
1141 left-margin: 8
1142 fill-column: 74
1143 version-control: never
1144 End: