opcodes/ChangeLog

   1 2015-08-17  Alan Modra  <amodra@gmail.com>
   2
   3         * cgen.sh: Trim trailing space from cgen output.
   4         * ia64-gen.c (print_dependency_table): Don't generate trailing space.
   5         (print_dis_table): Likewise.
   6         * opc2c.c (dump_lines): Likewise.
   7         (orig_filename): Warning fix.
   8         * ia64-asmtab.c: Regenerate.
   9
  10 2015-08-13  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  11
  12         * arm-dis.c (print_insn_arm): Disassembling for all targets V6
  13         and higher with ARM instruction set will now mark the 26-bit
  14         versions of teq,tst,cmn and cmp as UNPREDICTABLE.
  15         (arm_opcodes): Fix for unpredictable nop being recognized as a
  16         teq.
  17
  18 2015-08-12  Simon Dardis  <simon.dardis@imgtec.com>
  19
  20         * micromips-opc.c (micromips_opcodes): Re-order table so that move
  21         based on 'or' is first.
  22         * mips-opc.c (mips_builtin_opcodes): Ditto.
  23
  24 2015-08-11  Nick Clifton  <nickc@redhat.com>
  25
  26         PR 18800
  27         * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
  28         instruction.
  29
  30 2015-08-10  Robert Suchanek  <robert.suchanek@imgtec.com>
  31
  32         * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
  33
  34 2015-08-07  Amit Pawar <Amit.Pawar@amd.com>
  35
  36         * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
  37         * i386-init.h: Regenerated.
  38
  39 2015-07-30  H.J. Lu  <hongjiu.lu@intel.com>
  40
  41         PR binutils/13571
  42         * i386-dis.c (MOD_0FC3): New.
  43         (PREFIX_0FC3): Renamed to ...
  44         (PREFIX_MOD_0_0FC3): This.
  45         (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
  46         (prefix_table): Replace Ma with Ev on movntiS.
  47         (mod_table): Add MOD_0FC3.
  48
  49 2015-07-27  H.J. Lu  <hongjiu.lu@intel.com>
  50
  51         * configure: Regenerated.
  52
  53 2015-07-23  Alan Modra  <amodra@gmail.com>
  54
  55         PR 18708
  56         * i386-dis.c (get64): Avoid signed integer overflow.
  57
  58 2015-07-22  Alexander Fomin  <alexander.fomin@intel.com>
  59
  60         PR binutils/18631
  61         * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
  62         "EXEvexHalfBcstXmmq" for the second operand.
  63         (EVEX_W_0F79_P_2): Likewise.
  64         (EVEX_W_0F7A_P_2): Likewise.
  65         (EVEX_W_0F7B_P_2): Likewise.
  66
  67 2015-07-16  Alessandro Marzocchi  <alessandro.marzocchi@gmail.com>
  68
  69         * arm-dis.c (print_insn_coprocessor): Added support for quarter
  70         float bitfield format.
  71         (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
  72         quarter float bitfield format.
  73
  74 2015-07-14  H.J. Lu  <hongjiu.lu@intel.com>
  75
  76         * configure: Regenerated.
  77
  78 2015-07-03  Alan Modra  <amodra@gmail.com>
  79
  80         * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
  81         * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries.  Add
  82         PPC_OPCODE_7450 to 7450 entry.  Add PPC_OPCODE_750 to 750cl entry.
  83
  84 2015-07-01  Sandra Loosemore  <sandra@codesourcery.com>
  85             Cesar Philippidis  <cesar@codesourcery.com>
  86
  87         * nios2-dis.c (nios2_extract_opcode): New.
  88         (nios2_disassembler_state): New.
  89         (nios2_find_opcode_hash): Use mach parameter to select correct
  90         disassembler state.
  91         (nios2_print_insn_arg): Extend to support new R2 argument letters
  92         and formats.
  93         (print_insn_nios2): Check for 16-bit instruction at end of memory.
  94         * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
  95         (NIOS2_NUM_OPCODES): Rename to...
  96         (NIOS2_NUM_R1_OPCODES): This.
  97         (nios2_r2_opcodes): New.
  98         (NIOS2_NUM_R2_OPCODES): New.
  99         (nios2_num_r2_opcodes): New.
 100         (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
 101         (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
 102         (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
 103         (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
 104         (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
 105
 106 2015-06-30  Amit Pawar  <Amit.Pawar@amd.com>
 107
 108         * i386-dis.c (OP_Mwaitx): New.
 109         (rm_table): Add monitorx/mwaitx.
 110         * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
 111         and CPU_ZNVER1_FLAGS.  Add CPU_MWAITX_FLAGS.
 112         (operand_type_init): Add CpuMWAITX.
 113         * i386-opc.h (CpuMWAITX): New.
 114         (i386_cpu_flags): Add cpumwaitx.
 115         * i386-opc.tbl: Add monitorx and mwaitx.
 116         * i386-init.h: Regenerated.
 117         * i386-tbl.h: Likewise.
 118
 119 2015-06-22  Peter Bergner  <bergner@vnet.ibm.com>
 120
 121         * ppc-opc.c (insert_ls): Test for invalid LS operands.
 122         (insert_esync): New function.
 123         (LS, WC): Use insert_ls.
 124         (ESYNC): Use insert_esync.
 125
 126 2015-06-22  Nick Clifton  <nickc@redhat.com>
 127
 128         * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
 129         requested region lies beyond it.
 130         * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
 131         looking for 32-bit insns.
 132         * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
 133         data.
 134         * sh-dis.c (print_insn_sh): Likewise.
 135         * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
 136         blocks of instructions.
 137         * vax-dis.c (print_insn_vax): Check that the requested address
 138         does not clash with the stop_vma.
 139
 140 2015-06-19  Peter Bergner  <bergner@vnet.ibm.com>
 141
 142         * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
 143         * ppc-opc.c (FXM4): Add non-zero optional value.
 144         (TBR): Likewise.
 145         (SXL): Likewise.
 146         (insert_fxm): Handle new default operand value.
 147         (extract_fxm): Likewise.
 148         (insert_tbr): Likewise.
 149         (extract_tbr): Likewise.
 150
 151 2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
 152
 153         * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
 154
 155 2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 156
 157         * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
 158
 159 2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>
 160
 161         * ppc-opc.c: Add comment accidentally removed by old commit.
 162         (MTMSRD_L): Delete.
 163
 164 2015-06-04  Peter Bergner  <bergner@vnet.ibm.com>
 165
 166         * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
 167
 168 2015-06-04  Nick Clifton  <nickc@redhat.com>
 169
 170         PR 18474
 171         * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
 172
 173 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 174
 175         * arm-dis.c (arm_opcodes): Add "setpan".
 176         (thumb_opcodes): Add "setpan".
 177
 178 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 179
 180         * arm-dis.c (select_arm_features): Rework to avoid used of redefined
 181         macros.
 182
 183 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 184
 185         * aarch64-tbl.h (aarch64_feature_rdma): New.
 186         (RDMA): New.
 187         (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
 188         * aarch64-asm-2.c: Regenerate.
 189         * aarch64-dis-2.c: Regenerate.
 190         * aarch64-opc-2.c: Regenerate.
 191
 192 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 193
 194         * aarch64-tbl.h (aarch64_feature_lor): New.
 195         (LOR): New.
 196         (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
 197         "stllrb", "stllrh".
 198         * aarch64-asm-2.c: Regenerate.
 199         * aarch64-dis-2.c: Regenerate.
 200         * aarch64-opc-2.c: Regenerate.
 201
 202 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
 203
 204         * aarch64-opc.c (F_ARCHEXT): New.
 205         (aarch64_sys_regs): Add "pan".
 206         (aarch64_sys_reg_supported_p): New.
 207         (aarch64_pstatefields): Add "pan".
 208         (aarch64_pstatefield_supported_p): New.
 209
 210 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 211
 212         * i386-tbl.h: Regenerate.
 213
 214 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 215
 216         * i386-dis.c (print_insn): Swap rounding mode specifier and
 217         general purpose register in Intel mode.
 218
 219 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 220
 221         * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
 222         * i386-tbl.h: Regenerate.
 223
 224 2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
 225
 226         * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
 227         * i386-init.h: Regenerated.
 228
 229 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 230
 231         PR binutis/18386
 232         * i386-dis.c: Add comments for '@'.
 233         (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
 234         (enum x86_64_isa): New.
 235         (isa64): Likewise.
 236         (print_i386_disassembler_options): Add amd64 and intel64.
 237         (print_insn): Handle amd64 and intel64.
 238         (putop): Handle '@'.
 239         (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
 240         * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
 241         * i386-opc.h (AMD64): New.
 242         (CpuIntel64): Likewise.
 243         (i386_cpu_flags): Add cpuamd64 and cpuintel64.
 244         * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
 245         Mark direct call/jmp without Disp16|Disp32 as Intel64.
 246         * i386-init.h: Regenerated.
 247         * i386-tbl.h: Likewise.
 248
 249 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
 250
 251         * ppc-opc.c (IH) New define.
 252         (powerpc_opcodes) <wait>: Do not enable for POWER7.
 253         <tlbie>: Add RS operand for POWER7.
 254         <slbia>: Add IH operand for POWER6.
 255
 256 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 257
 258         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
 259         direct branch.
 260         (jmp): Likewise.
 261         * i386-tbl.h: Regenerated.
 262
 263 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 264
 265         * configure.ac: Support bfd_iamcu_arch.
 266         * disassemble.c (disassembler): Support bfd_iamcu_arch.
 267         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
 268         CPU_IAMCU_COMPAT_FLAGS.
 269         (cpu_flags): Add CpuIAMCU.
 270         * i386-opc.h (CpuIAMCU): New.
 271         (i386_cpu_flags): Add cpuiamcu.
 272         * configure: Regenerated.
 273         * i386-init.h: Likewise.
 274         * i386-tbl.h: Likewise.
 275
 276 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
 277
 278         PR binutis/18386
 279         * i386-dis.c (X86_64_E8): New.
 280         (X86_64_E9): Likewise.
 281         Update comments on 'T', 'U', 'V'.  Add comments for '^'.
 282         (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
 283         (x86_64_table): Add X86_64_E8 and X86_64_E9.
 284         (mod_table): Replace {T|} with ^ on Jcall/Jmp.
 285         (putop): Handle '^'.
 286         (OP_J): Ignore the operand size prefix in 64-bit.  Don't check
 287         REX_W.
 288
 289 2015-04-30  DJ Delorie  <dj@redhat.com>
 290
 291         * disassemble.c (disassembler): Choose suitable disassembler based
 292         on E_ABI.
 293         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
 294         it to decode mul/div insns.
 295         * rl78-decode.c: Regenerate.
 296         * rl78-dis.c (print_insn_rl78): Rename to...
 297         (print_insn_rl78_common): ...this, take ISA parameter.
 298         (print_insn_rl78): New.
 299         (print_insn_rl78_g10): New.
 300         (print_insn_rl78_g13): New.
 301         (print_insn_rl78_g14): New.
 302         (rl78_get_disassembler): New.
 303
 304 2015-04-29  Nick Clifton  <nickc@redhat.com>
 305
 306         * po/fr.po: Updated French translation.
 307
 308 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
 309
 310         * ppc-opc.c (DCBT_EO): New define.
 311         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
 312         <lharx>: Likewise.
 313         <stbcx.>: Likewise.
 314         <sthcx.>: Likewise.
 315         <waitrsv>: Do not enable for POWER7 and later.
 316         <waitimpl>: Likewise.
 317         <dcbt>: Default to the two operand form of the instruction for all
 318         "old" cpus.  For "new" cpus, use the operand ordering that matches
 319         whether the cpu is server or embedded.
 320         <dcbtst>: Likewise.
 321
 322 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 323
 324         * s390-opc.c: New instruction type VV0UU2.
 325         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
 326         and WFC.
 327
 328 2015-04-23  Jan Beulich  <jbeulich@suse.com>
 329
 330         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
 331         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
 332         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
 333         (vfpclasspd, vfpclassps): Add %XZ.
 334
 335 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 336
 337         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
 338         (PREFIX_UD_REPZ): Likewise.
 339         (PREFIX_UD_REPNZ): Likewise.
 340         (PREFIX_UD_DATA): Likewise.
 341         (PREFIX_UD_ADDR): Likewise.
 342         (PREFIX_UD_LOCK): Likewise.
 343
 344 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 345
 346         * i386-dis.c (prefix_requirement): Removed.
 347         (print_insn): Don't set prefix_requirement.  Check
 348         dp->prefix_requirement instead of prefix_requirement.
 349
 350 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 351
 352         PR binutils/17898
 353         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
 354         (PREFIX_MOD_0_0FC7_REG_6): This.
 355         (PREFIX_MOD_3_0FC7_REG_6): New.
 356         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
 357         (prefix_table): Replace PREFIX_0FC7_REG_6 with
 358         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
 359         PREFIX_MOD_3_0FC7_REG_7.
 360         (mod_table): Replace PREFIX_0FC7_REG_6 with
 361         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
 362         PREFIX_MOD_3_0FC7_REG_7.
 363
 364 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 365
 366         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
 367         (PREFIX_MANDATORY_REPNZ): Likewise.
 368         (PREFIX_MANDATORY_DATA): Likewise.
 369         (PREFIX_MANDATORY_ADDR): Likewise.
 370         (PREFIX_MANDATORY_LOCK): Likewise.
 371         (PREFIX_MANDATORY): Likewise.
 372         (PREFIX_UD_SHIFT): Set to 8
 373         (PREFIX_UD_REPZ): Updated.
 374         (PREFIX_UD_REPNZ): Likewise.
 375         (PREFIX_UD_DATA): Likewise.
 376         (PREFIX_UD_ADDR): Likewise.
 377         (PREFIX_UD_LOCK): Likewise.
 378         (PREFIX_IGNORED_SHIFT): New.
 379         (PREFIX_IGNORED_REPZ): Likewise.
 380         (PREFIX_IGNORED_REPNZ): Likewise.
 381         (PREFIX_IGNORED_DATA): Likewise.
 382         (PREFIX_IGNORED_ADDR): Likewise.
 383         (PREFIX_IGNORED_LOCK): Likewise.
 384         (PREFIX_OPCODE): Likewise.
 385         (PREFIX_IGNORED): Likewise.
 386         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 387         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 388         (three_byte_table): Likewise.
 389         (mod_table): Likewise.
 390         (mandatory_prefix): Renamed to ...
 391         (prefix_requirement): This.
 392         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 393         Update PREFIX_90 entry.
 394         (get_valid_dis386): Check prefix_requirement to see if a prefix
 395         should be ignored.
 396         (print_insn): Replace mandatory_prefix with prefix_requirement.
 397
 398 2015-04-15  Renlin Li  <renlin.li@arm.com>
 399
 400         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
 401         use it for ssat and ssat16.
 402         (print_insn_thumb32): Add handle case for 'D' control code.
 403
 404 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
 405             H.J. Lu  <hongjiu.lu@intel.com>
 406
 407         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
 408         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
 409         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
 410         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
 411         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
 412         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
 413         Fill prefix_requirement field.
 414         (struct dis386): Add prefix_requirement field.
 415         (dis386): Fill prefix_requirement field.
 416         (dis386_twobyte): Ditto.
 417         (twobyte_has_mandatory_prefix_: Remove.
 418         (reg_table): Fill prefix_requirement field.
 419         (prefix_table): Ditto.
 420         (x86_64_table): Ditto.
 421         (three_byte_table): Ditto.
 422         (xop_table): Ditto.
 423         (vex_table): Ditto.
 424         (vex_len_table): Ditto.
 425         (vex_w_table): Ditto.
 426         (mod_table): Ditto.
 427         (bad_opcode): Ditto.
 428         (print_insn): Use prefix_requirement.
 429         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
 430         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
 431         (float_reg): Ditto.
 432
 433 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
 434
 435         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
 436
 437 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 438
 439         * Makefile.in: Regenerated.
 440
 441 2015-03-25  Anton Blanchard  <anton@samba.org>
 442
 443         * ppc-dis.c (disassemble_init_powerpc): Only initialise
 444         powerpc_opcd_indices and vle_opcd_indices once.
 445
 446 2015-03-25  Anton Blanchard  <anton@samba.org>
 447
 448         * ppc-opc.c (powerpc_opcodes): Add slbfee.
 449
 450 2015-03-24  Terry Guo  <terry.guo@arm.com>
 451
 452         * arm-dis.c (opcode32): Updated to use new arm feature struct.
 453         (opcode16): Likewise.
 454         (coprocessor_opcodes): Replace bit with feature struct.
 455         (neon_opcodes): Likewise.
 456         (arm_opcodes): Likewise.
 457         (thumb_opcodes): Likewise.
 458         (thumb32_opcodes): Likewise.
 459         (print_insn_coprocessor): Likewise.
 460         (print_insn_arm): Likewise.
 461         (select_arm_features): Follow new feature struct.
 462
 463 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 464
 465         * i386-dis.c (rm_table): Add clzero.
 466         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
 467         Add CPU_CLZERO_FLAGS.
 468         (cpu_flags): Add CpuCLZERO.
 469         * i386-opc.h: Add CpuCLZERO.
 470         * i386-opc.tbl: Add clzero.
 471         * i386-init.h: Re-generated.
 472         * i386-tbl.h: Re-generated.
 473
 474 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 475
 476         * mips-opc.c (decode_mips_operand): Fix constraint issues
 477         with u and y operands.
 478
 479 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 480
 481         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
 482
 483 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 484
 485         * s390-opc.c: Add new IBM z13 instructions.
 486         * s390-opc.txt: Likewise.
 487
 488 2015-03-10  Renlin Li  <renlin.li@arm.com>
 489
 490         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
 491         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
 492         related alias.
 493         * aarch64-asm-2.c: Regenerate.
 494         * aarch64-dis-2.c: Likewise.
 495         * aarch64-opc-2.c: Likewise.
 496
 497 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
 498
 499         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
 500
 501 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
 502
 503         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
 504         arch_sh_up.
 505         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
 506         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
 507
 508 2015-02-23  Vinay  <Vinay.G@kpit.com>
 509
 510         * rl78-decode.opc (MOV): Added space between two operands for
 511         'mov' instruction in index addressing mode.
 512         * rl78-decode.c: Regenerate.
 513
 514 2015-02-19  Pedro Alves  <palves@redhat.com>
 515
 516         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
 517
 518 2015-02-10  Pedro Alves  <palves@redhat.com>
 519             Tom Tromey  <tromey@redhat.com>
 520
 521         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
 522         microblaze_and, microblaze_xor.
 523         * microblaze-opc.h (opcodes): Adjust.
 524
 525 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
 526
 527         * Makefile.am: Add FT32 files.
 528         * configure.ac: Handle FT32.
 529         * disassemble.c (disassembler): Call print_insn_ft32.
 530         * ft32-dis.c: New file.
 531         * ft32-opc.c: New file.
 532         * Makefile.in: Regenerate.
 533         * configure: Regenerate.
 534         * po/POTFILES.in: Regenerate.
 535
 536 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 537
 538         * nds32-asm.c (keyword_sr): Add new system registers.
 539
 540 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 541
 542         * s390-dis.c (s390_extract_operand): Support vector register
 543         operands.
 544         (s390_print_insn_with_opcode): Support new operands types and add
 545         new handling of optional operands.
 546         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
 547         and include opcode/s390.h instead.
 548         (struct op_struct): New field `flags'.
 549         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
 550         (dumpTable): Dump flags.
 551         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
 552         string.
 553         * s390-opc.c: Add new operands types, instruction formats, and
 554         instruction masks.
 555         (s390_opformats): Add new formats for .insn.
 556         * s390-opc.txt: Add new instructions.
 557
 558 2015-01-01  Alan Modra  <amodra@gmail.com>
 559
 560         Update year range in copyright notice of all files.
 561
 562 For older changes see ChangeLog-2014
 563 \f
 564 Copyright (C) 2015 Free Software Foundation, Inc.
 565
 566 Copying and distribution of this file, with or without modification,
 567 are permitted in any medium without royalty provided the copyright
 568 notice and this notice are preserved.
 569
 570 Local Variables:
 571 mode: change-log
 572 left-margin: 8
 573 fill-column: 74
 574 version-control: never
 575 End: