opcodes/ChangeLog

   1 2015-08-11  Nick Clifton  <nickc@redhat.com>
   2
   3         PR 18800
   4         * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
   5         instruction.
   6
   7 2015-08-10  Robert Suchanek  <robert.suchanek@imgtec.com>
   8
   9         * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
  10
  11 2015-08-07  Amit Pawar <Amit.Pawar@amd.com>
  12
  13         * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
  14         * i386-init.h: Regenerated.
  15
  16 2015-07-30  H.J. Lu  <hongjiu.lu@intel.com>
  17
  18         PR binutils/13571
  19         * i386-dis.c (MOD_0FC3): New.
  20         (PREFIX_0FC3): Renamed to ...
  21         (PREFIX_MOD_0_0FC3): This.
  22         (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
  23         (prefix_table): Replace Ma with Ev on movntiS.
  24         (mod_table): Add MOD_0FC3.
  25
  26 2015-07-27  H.J. Lu  <hongjiu.lu@intel.com>
  27
  28         * configure: Regenerated.
  29
  30 2015-07-23  Alan Modra  <amodra@gmail.com>
  31
  32         PR 18708
  33         * i386-dis.c (get64): Avoid signed integer overflow.
  34
  35 2015-07-22  Alexander Fomin  <alexander.fomin@intel.com>
  36
  37         PR binutils/18631
  38         * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
  39         "EXEvexHalfBcstXmmq" for the second operand.
  40         (EVEX_W_0F79_P_2): Likewise.
  41         (EVEX_W_0F7A_P_2): Likewise.
  42         (EVEX_W_0F7B_P_2): Likewise.
  43
  44 2015-07-16  Alessandro Marzocchi  <alessandro.marzocchi@gmail.com>
  45
  46         * arm-dis.c (print_insn_coprocessor): Added support for quarter
  47         float bitfield format.
  48         (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
  49         quarter float bitfield format.
  50
  51 2015-07-14  H.J. Lu  <hongjiu.lu@intel.com>
  52
  53         * configure: Regenerated.
  54
  55 2015-07-03  Alan Modra  <amodra@gmail.com>
  56
  57         * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
  58         * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries.  Add
  59         PPC_OPCODE_7450 to 7450 entry.  Add PPC_OPCODE_750 to 750cl entry.
  60
  61 2015-07-01  Sandra Loosemore  <sandra@codesourcery.com>
  62             Cesar Philippidis  <cesar@codesourcery.com>
  63
  64         * nios2-dis.c (nios2_extract_opcode): New.
  65         (nios2_disassembler_state): New.
  66         (nios2_find_opcode_hash): Use mach parameter to select correct
  67         disassembler state.
  68         (nios2_print_insn_arg): Extend to support new R2 argument letters
  69         and formats.
  70         (print_insn_nios2): Check for 16-bit instruction at end of memory.
  71         * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
  72         (NIOS2_NUM_OPCODES): Rename to...
  73         (NIOS2_NUM_R1_OPCODES): This.
  74         (nios2_r2_opcodes): New.
  75         (NIOS2_NUM_R2_OPCODES): New.
  76         (nios2_num_r2_opcodes): New.
  77         (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
  78         (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
  79         (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
  80         (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
  81         (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
  82
  83 2015-06-30  Amit Pawar  <Amit.Pawar@amd.com>
  84
  85         * i386-dis.c (OP_Mwaitx): New.
  86         (rm_table): Add monitorx/mwaitx.
  87         * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
  88         and CPU_ZNVER1_FLAGS.  Add CPU_MWAITX_FLAGS.
  89         (operand_type_init): Add CpuMWAITX.
  90         * i386-opc.h (CpuMWAITX): New.
  91         (i386_cpu_flags): Add cpumwaitx.
  92         * i386-opc.tbl: Add monitorx and mwaitx.
  93         * i386-init.h: Regenerated.
  94         * i386-tbl.h: Likewise.
  95
  96 2015-06-22  Peter Bergner  <bergner@vnet.ibm.com>
  97
  98         * ppc-opc.c (insert_ls): Test for invalid LS operands.
  99         (insert_esync): New function.
 100         (LS, WC): Use insert_ls.
 101         (ESYNC): Use insert_esync.
 102
 103 2015-06-22  Nick Clifton  <nickc@redhat.com>
 104
 105         * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
 106         requested region lies beyond it.
 107         * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
 108         looking for 32-bit insns.
 109         * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
 110         data.
 111         * sh-dis.c (print_insn_sh): Likewise.
 112         * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
 113         blocks of instructions.
 114         * vax-dis.c (print_insn_vax): Check that the requested address
 115         does not clash with the stop_vma.
 116
 117 2015-06-19  Peter Bergner  <bergner@vnet.ibm.com>
 118
 119         * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
 120         * ppc-opc.c (FXM4): Add non-zero optional value.
 121         (TBR): Likewise.
 122         (SXL): Likewise.
 123         (insert_fxm): Handle new default operand value.
 124         (extract_fxm): Likewise.
 125         (insert_tbr): Likewise.
 126         (extract_tbr): Likewise.
 127
 128 2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
 129
 130         * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
 131
 132 2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 133
 134         * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
 135
 136 2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>
 137
 138         * ppc-opc.c: Add comment accidentally removed by old commit.
 139         (MTMSRD_L): Delete.
 140
 141 2015-06-04  Peter Bergner  <bergner@vnet.ibm.com>
 142
 143         * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
 144
 145 2015-06-04  Nick Clifton  <nickc@redhat.com>
 146
 147         PR 18474
 148         * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
 149
 150 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 151
 152         * arm-dis.c (arm_opcodes): Add "setpan".
 153         (thumb_opcodes): Add "setpan".
 154
 155 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 156
 157         * arm-dis.c (select_arm_features): Rework to avoid used of redefined
 158         macros.
 159
 160 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 161
 162         * aarch64-tbl.h (aarch64_feature_rdma): New.
 163         (RDMA): New.
 164         (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
 165         * aarch64-asm-2.c: Regenerate.
 166         * aarch64-dis-2.c: Regenerate.
 167         * aarch64-opc-2.c: Regenerate.
 168
 169 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 170
 171         * aarch64-tbl.h (aarch64_feature_lor): New.
 172         (LOR): New.
 173         (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
 174         "stllrb", "stllrh".
 175         * aarch64-asm-2.c: Regenerate.
 176         * aarch64-dis-2.c: Regenerate.
 177         * aarch64-opc-2.c: Regenerate.
 178
 179 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
 180
 181         * aarch64-opc.c (F_ARCHEXT): New.
 182         (aarch64_sys_regs): Add "pan".
 183         (aarch64_sys_reg_supported_p): New.
 184         (aarch64_pstatefields): Add "pan".
 185         (aarch64_pstatefield_supported_p): New.
 186
 187 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 188
 189         * i386-tbl.h: Regenerate.
 190
 191 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 192
 193         * i386-dis.c (print_insn): Swap rounding mode specifier and
 194         general purpose register in Intel mode.
 195
 196 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 197
 198         * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
 199         * i386-tbl.h: Regenerate.
 200
 201 2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
 202
 203         * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
 204         * i386-init.h: Regenerated.
 205
 206 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 207
 208         PR binutis/18386
 209         * i386-dis.c: Add comments for '@'.
 210         (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
 211         (enum x86_64_isa): New.
 212         (isa64): Likewise.
 213         (print_i386_disassembler_options): Add amd64 and intel64.
 214         (print_insn): Handle amd64 and intel64.
 215         (putop): Handle '@'.
 216         (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
 217         * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
 218         * i386-opc.h (AMD64): New.
 219         (CpuIntel64): Likewise.
 220         (i386_cpu_flags): Add cpuamd64 and cpuintel64.
 221         * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
 222         Mark direct call/jmp without Disp16|Disp32 as Intel64.
 223         * i386-init.h: Regenerated.
 224         * i386-tbl.h: Likewise.
 225
 226 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
 227
 228         * ppc-opc.c (IH) New define.
 229         (powerpc_opcodes) <wait>: Do not enable for POWER7.
 230         <tlbie>: Add RS operand for POWER7.
 231         <slbia>: Add IH operand for POWER6.
 232
 233 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 234
 235         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
 236         direct branch.
 237         (jmp): Likewise.
 238         * i386-tbl.h: Regenerated.
 239
 240 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 241
 242         * configure.ac: Support bfd_iamcu_arch.
 243         * disassemble.c (disassembler): Support bfd_iamcu_arch.
 244         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
 245         CPU_IAMCU_COMPAT_FLAGS.
 246         (cpu_flags): Add CpuIAMCU.
 247         * i386-opc.h (CpuIAMCU): New.
 248         (i386_cpu_flags): Add cpuiamcu.
 249         * configure: Regenerated.
 250         * i386-init.h: Likewise.
 251         * i386-tbl.h: Likewise.
 252
 253 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
 254
 255         PR binutis/18386
 256         * i386-dis.c (X86_64_E8): New.
 257         (X86_64_E9): Likewise.
 258         Update comments on 'T', 'U', 'V'.  Add comments for '^'.
 259         (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
 260         (x86_64_table): Add X86_64_E8 and X86_64_E9.
 261         (mod_table): Replace {T|} with ^ on Jcall/Jmp.
 262         (putop): Handle '^'.
 263         (OP_J): Ignore the operand size prefix in 64-bit.  Don't check
 264         REX_W.
 265
 266 2015-04-30  DJ Delorie  <dj@redhat.com>
 267
 268         * disassemble.c (disassembler): Choose suitable disassembler based
 269         on E_ABI.
 270         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
 271         it to decode mul/div insns.
 272         * rl78-decode.c: Regenerate.
 273         * rl78-dis.c (print_insn_rl78): Rename to...
 274         (print_insn_rl78_common): ...this, take ISA parameter.
 275         (print_insn_rl78): New.
 276         (print_insn_rl78_g10): New.
 277         (print_insn_rl78_g13): New.
 278         (print_insn_rl78_g14): New.
 279         (rl78_get_disassembler): New.
 280
 281 2015-04-29  Nick Clifton  <nickc@redhat.com>
 282
 283         * po/fr.po: Updated French translation.
 284
 285 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
 286
 287         * ppc-opc.c (DCBT_EO): New define.
 288         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
 289         <lharx>: Likewise.
 290         <stbcx.>: Likewise.
 291         <sthcx.>: Likewise.
 292         <waitrsv>: Do not enable for POWER7 and later.
 293         <waitimpl>: Likewise.
 294         <dcbt>: Default to the two operand form of the instruction for all
 295         "old" cpus.  For "new" cpus, use the operand ordering that matches
 296         whether the cpu is server or embedded.
 297         <dcbtst>: Likewise.
 298
 299 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 300
 301         * s390-opc.c: New instruction type VV0UU2.
 302         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
 303         and WFC.
 304
 305 2015-04-23  Jan Beulich  <jbeulich@suse.com>
 306
 307         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
 308         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
 309         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
 310         (vfpclasspd, vfpclassps): Add %XZ.
 311
 312 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 313
 314         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
 315         (PREFIX_UD_REPZ): Likewise.
 316         (PREFIX_UD_REPNZ): Likewise.
 317         (PREFIX_UD_DATA): Likewise.
 318         (PREFIX_UD_ADDR): Likewise.
 319         (PREFIX_UD_LOCK): Likewise.
 320
 321 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 322
 323         * i386-dis.c (prefix_requirement): Removed.
 324         (print_insn): Don't set prefix_requirement.  Check
 325         dp->prefix_requirement instead of prefix_requirement.
 326
 327 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 328
 329         PR binutils/17898
 330         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
 331         (PREFIX_MOD_0_0FC7_REG_6): This.
 332         (PREFIX_MOD_3_0FC7_REG_6): New.
 333         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
 334         (prefix_table): Replace PREFIX_0FC7_REG_6 with
 335         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
 336         PREFIX_MOD_3_0FC7_REG_7.
 337         (mod_table): Replace PREFIX_0FC7_REG_6 with
 338         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
 339         PREFIX_MOD_3_0FC7_REG_7.
 340
 341 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 342
 343         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
 344         (PREFIX_MANDATORY_REPNZ): Likewise.
 345         (PREFIX_MANDATORY_DATA): Likewise.
 346         (PREFIX_MANDATORY_ADDR): Likewise.
 347         (PREFIX_MANDATORY_LOCK): Likewise.
 348         (PREFIX_MANDATORY): Likewise.
 349         (PREFIX_UD_SHIFT): Set to 8
 350         (PREFIX_UD_REPZ): Updated.
 351         (PREFIX_UD_REPNZ): Likewise.
 352         (PREFIX_UD_DATA): Likewise.
 353         (PREFIX_UD_ADDR): Likewise.
 354         (PREFIX_UD_LOCK): Likewise.
 355         (PREFIX_IGNORED_SHIFT): New.
 356         (PREFIX_IGNORED_REPZ): Likewise.
 357         (PREFIX_IGNORED_REPNZ): Likewise.
 358         (PREFIX_IGNORED_DATA): Likewise.
 359         (PREFIX_IGNORED_ADDR): Likewise.
 360         (PREFIX_IGNORED_LOCK): Likewise.
 361         (PREFIX_OPCODE): Likewise.
 362         (PREFIX_IGNORED): Likewise.
 363         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 364         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 365         (three_byte_table): Likewise.
 366         (mod_table): Likewise.
 367         (mandatory_prefix): Renamed to ...
 368         (prefix_requirement): This.
 369         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 370         Update PREFIX_90 entry.
 371         (get_valid_dis386): Check prefix_requirement to see if a prefix
 372         should be ignored.
 373         (print_insn): Replace mandatory_prefix with prefix_requirement.
 374
 375 2015-04-15  Renlin Li  <renlin.li@arm.com>
 376
 377         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
 378         use it for ssat and ssat16.
 379         (print_insn_thumb32): Add handle case for 'D' control code.
 380
 381 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
 382             H.J. Lu  <hongjiu.lu@intel.com>
 383
 384         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
 385         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
 386         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
 387         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
 388         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
 389         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
 390         Fill prefix_requirement field.
 391         (struct dis386): Add prefix_requirement field.
 392         (dis386): Fill prefix_requirement field.
 393         (dis386_twobyte): Ditto.
 394         (twobyte_has_mandatory_prefix_: Remove.
 395         (reg_table): Fill prefix_requirement field.
 396         (prefix_table): Ditto.
 397         (x86_64_table): Ditto.
 398         (three_byte_table): Ditto.
 399         (xop_table): Ditto.
 400         (vex_table): Ditto.
 401         (vex_len_table): Ditto.
 402         (vex_w_table): Ditto.
 403         (mod_table): Ditto.
 404         (bad_opcode): Ditto.
 405         (print_insn): Use prefix_requirement.
 406         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
 407         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
 408         (float_reg): Ditto.
 409
 410 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
 411
 412         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
 413
 414 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 415
 416         * Makefile.in: Regenerated.
 417
 418 2015-03-25  Anton Blanchard  <anton@samba.org>
 419
 420         * ppc-dis.c (disassemble_init_powerpc): Only initialise
 421         powerpc_opcd_indices and vle_opcd_indices once.
 422
 423 2015-03-25  Anton Blanchard  <anton@samba.org>
 424
 425         * ppc-opc.c (powerpc_opcodes): Add slbfee.
 426
 427 2015-03-24  Terry Guo  <terry.guo@arm.com>
 428
 429         * arm-dis.c (opcode32): Updated to use new arm feature struct.
 430         (opcode16): Likewise.
 431         (coprocessor_opcodes): Replace bit with feature struct.
 432         (neon_opcodes): Likewise.
 433         (arm_opcodes): Likewise.
 434         (thumb_opcodes): Likewise.
 435         (thumb32_opcodes): Likewise.
 436         (print_insn_coprocessor): Likewise.
 437         (print_insn_arm): Likewise.
 438         (select_arm_features): Follow new feature struct.
 439
 440 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 441
 442         * i386-dis.c (rm_table): Add clzero.
 443         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
 444         Add CPU_CLZERO_FLAGS.
 445         (cpu_flags): Add CpuCLZERO.
 446         * i386-opc.h: Add CpuCLZERO.
 447         * i386-opc.tbl: Add clzero.
 448         * i386-init.h: Re-generated.
 449         * i386-tbl.h: Re-generated.
 450
 451 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 452
 453         * mips-opc.c (decode_mips_operand): Fix constraint issues
 454         with u and y operands.
 455
 456 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 457
 458         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
 459
 460 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 461
 462         * s390-opc.c: Add new IBM z13 instructions.
 463         * s390-opc.txt: Likewise.
 464
 465 2015-03-10  Renlin Li  <renlin.li@arm.com>
 466
 467         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
 468         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
 469         related alias.
 470         * aarch64-asm-2.c: Regenerate.
 471         * aarch64-dis-2.c: Likewise.
 472         * aarch64-opc-2.c: Likewise.
 473
 474 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
 475
 476         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
 477
 478 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
 479
 480         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
 481         arch_sh_up.
 482         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
 483         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
 484
 485 2015-02-23  Vinay  <Vinay.G@kpit.com>
 486
 487         * rl78-decode.opc (MOV): Added space between two operands for
 488         'mov' instruction in index addressing mode.
 489         * rl78-decode.c: Regenerate.
 490
 491 2015-02-19  Pedro Alves  <palves@redhat.com>
 492
 493         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
 494
 495 2015-02-10  Pedro Alves  <palves@redhat.com>
 496             Tom Tromey  <tromey@redhat.com>
 497
 498         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
 499         microblaze_and, microblaze_xor.
 500         * microblaze-opc.h (opcodes): Adjust.
 501
 502 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
 503
 504         * Makefile.am: Add FT32 files.
 505         * configure.ac: Handle FT32.
 506         * disassemble.c (disassembler): Call print_insn_ft32.
 507         * ft32-dis.c: New file.
 508         * ft32-opc.c: New file.
 509         * Makefile.in: Regenerate.
 510         * configure: Regenerate.
 511         * po/POTFILES.in: Regenerate.
 512
 513 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 514
 515         * nds32-asm.c (keyword_sr): Add new system registers.
 516
 517 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 518
 519         * s390-dis.c (s390_extract_operand): Support vector register
 520         operands.
 521         (s390_print_insn_with_opcode): Support new operands types and add
 522         new handling of optional operands.
 523         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
 524         and include opcode/s390.h instead.
 525         (struct op_struct): New field `flags'.
 526         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
 527         (dumpTable): Dump flags.
 528         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
 529         string.
 530         * s390-opc.c: Add new operands types, instruction formats, and
 531         instruction masks.
 532         (s390_opformats): Add new formats for .insn.
 533         * s390-opc.txt: Add new instructions.
 534
 535 2015-01-01  Alan Modra  <amodra@gmail.com>
 536
 537         Update year range in copyright notice of all files.
 538
 539 For older changes see ChangeLog-2014
 540 \f
 541 Copyright (C) 2015 Free Software Foundation, Inc.
 542
 543 Copying and distribution of this file, with or without modification,
 544 are permitted in any medium without royalty provided the copyright
 545 notice and this notice are preserved.
 546
 547 Local Variables:
 548 mode: change-log
 549 left-margin: 8
 550 fill-column: 74
 551 version-control: never
 552 End: