opcodes/ChangeLog

   1 2016-11-22  Ambrogino Modigliani  <ambrogino.modigliani@gmail.com>
   2
   3         * configure: Regenerate.
   4
   5 2016-11-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
   6
   7         * sparc-opc.c (HWS_V8): Definition moved from
   8         gas/config/tc-sparc.c.
   9         (HWS_V9): Likewise.
  10         (HWS_VA): Likewise.
  11         (HWS_VB): Likewise.
  12         (HWS_VC): Likewise.
  13         (HWS_VD): Likewise.
  14         (HWS_VE): Likewise.
  15         (HWS_VV): Likewise.
  16         (HWS_VM): Likewise.
  17         (HWS2_VM): Likewise.
  18         (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
  19         existing entries.
  20
  21 2016-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
  22
  23         * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
  24         instructions.
  25
  26 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  27
  28         * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
  29         (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
  30         (aarch64_opcode_table): Add fcmla and fcadd.
  31         (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
  32         * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
  33         * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
  34         * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
  35         * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
  36         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
  37         * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
  38         (operand_general_constraint_met_p): Rotate and index range check.
  39         (aarch64_print_operand): Handle rotate operand.
  40         * aarch64-asm-2.c: Regenerate.
  41         * aarch64-dis-2.c: Likewise.
  42         * aarch64-opc-2.c: Likewise.
  43
  44 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  45
  46         * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
  47         * aarch64-asm-2.c: Regenerate.
  48         * aarch64-dis-2.c: Regenerate.
  49         * aarch64-opc-2.c: Regenerate.
  50
  51 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  52
  53         * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
  54         (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
  55         * aarch64-asm-2.c: Regenerate.
  56         * aarch64-dis-2.c: Regenerate.
  57         * aarch64-opc-2.c: Regenerate.
  58
  59 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  60
  61         * aarch64-tbl.h (QL_X1NIL): New.
  62         (arch64_opcode_table): Add ldraa, ldrab.
  63         (AARCH64_OPERANDS): Add "ADDR_SIMM10".
  64         * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
  65         * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
  66         * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
  67         * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
  68         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
  69         * aarch64-opc.c (fields): Add data for FLD_S_simm10.
  70         (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
  71         (aarch64_print_operand): Likewise.
  72         * aarch64-asm-2.c: Regenerate.
  73         * aarch64-dis-2.c: Regenerate.
  74         * aarch64-opc-2.c: Regenerate.
  75
  76 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  77
  78         * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
  79         brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
  80         * aarch64-asm-2.c: Regenerate.
  81         * aarch64-dis-2.c: Regenerate.
  82         * aarch64-opc-2.c: Regenerate.
  83
  84 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  85
  86         * aarch64-tbl.h (arch64_opcode_table): Add pacga.
  87         (AARCH64_OPERANDS): Add Rm_SP.
  88         * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
  89         * aarch64-asm-2.c: Regenerate.
  90         * aarch64-dis-2.c: Regenerate.
  91         * aarch64-opc-2.c: Regenerate.
  92
  93 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  94
  95         * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
  96         autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
  97         autdzb, xpaci, xpacd.
  98         * aarch64-asm-2.c: Regenerate.
  99         * aarch64-dis-2.c: Regenerate.
 100         * aarch64-opc-2.c: Regenerate.
 101
 102 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 103
 104         * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
 105         apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
 106         apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
 107         (aarch64_sys_reg_supported_p): Add feature test for new registers.
 108
 109 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 110
 111         * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
 112         (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
 113         autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
 114         autibsp.
 115         * aarch64-asm-2.c: Regenerate.
 116         * aarch64-dis-2.c: Regenerate.
 117
 118 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 119
 120         * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
 121
 122 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 123
 124         PR binutils/20799
 125         * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
 126         * i386-dis.c (EdqwS): Removed.
 127         (dqw_swap_mode): Likewise.
 128         (intel_operand_size): Don't check dqw_swap_mode.
 129         (OP_E_register): Likewise.
 130         (OP_E_memory): Likewise.
 131         (OP_G): Likewise.
 132         (OP_EX): Likewise.
 133         * i386-opc.tbl: Remove "S" from EVEX vpextrw.
 134         * i386-tbl.h: Regerated.
 135
 136 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 137
 138         * i386-opc.tbl: Merge AVX512F vmovq.
 139         * i386-tbl.h: Regerated.
 140
 141 2016-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 142
 143         PR binutils/20701
 144         * i386-dis.c (THREE_BYTE_0F7A): Removed.
 145         (dis386_twobyte): Don't use THREE_BYTE_0F7A.
 146         (three_byte_table): Remove THREE_BYTE_0F7A.
 147
 148 2016-11-07  H.J. Lu  <hongjiu.lu@intel.com>
 149
 150         PR binutils/20775
 151         * i386-dis.c (FGRPd9_2): Replace 0 with 1.
 152         (FGRPd9_4): Replace 1 with 2.
 153         (FGRPd9_5): Replace 2 with 3.
 154         (FGRPd9_6): Replace 3 with 4.
 155         (FGRPd9_7): Replace 4 with 5.
 156         (FGRPda_5): Replace 5 with 6.
 157         (FGRPdb_4): Replace 6 with 7.
 158         (FGRPde_3): Replace 7 with 8.
 159         (FGRPdf_4): Replace 8 with 9.
 160         (fgrps): Add an entry for Bad_Opcode.
 161
 162 2016-11-04  Andrew Burgess  <andrew.burgess@embecosm.com>
 163
 164         * arc-opc.c (arc_flag_operands): Add F_DI14.
 165         (arc_flag_classes): Add C_DI14.
 166         * arc-nps400-tbl.h: Add new exc instructions.
 167
 168 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 169
 170         * arc-dis.c (arc_insn_length): Return length 8 for instructions with
 171         major opcode 0xa.
 172         * arc-nps-400-tbl.h: Add dcmac instruction.
 173         * arc-opc.c (arc_operands): Added operands for dcmac instruction.
 174         (insert_nps_rbdouble_64): Added.
 175         (extract_nps_rbdouble_64): Added.
 176         (insert_nps_proto_size): Added.
 177         (extract_nps_proto_size): Added.
 178
 179 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 180
 181         * arc-dis.c (struct arc_operand_iterator): Remove all fields
 182         relating to long instruction processing, add new limm field.
 183         (OPCODE): Rename to...
 184         (OPCODE_32BIT_INSN): ...this.
 185         (OPCODE_AC): Delete.
 186         (skip_this_opcode): Handle different instruction lengths, update
 187         macro name.
 188         (special_flag_p): Update parameter type.
 189         (find_format_from_table): Update for more instruction lengths.
 190         (find_format_long_instructions): Delete.
 191         (find_format): Update for more instruction lengths.
 192         (arc_insn_length): Likewise.
 193         (extract_operand_value): Update for more instruction lengths.
 194         (operand_iterator_next): Remove code relating to long
 195         instructions.
 196         (arc_opcode_to_insn_type): New function.
 197         (print_insn_arc):Update for more instructions lengths.
 198         * arc-ext.c (extInstruction_t): Change argument type.
 199         * arc-ext.h (extInstruction_t): Change argument type.
 200         * arc-fxi.h: Change type unsigned to unsigned long long
 201         extensively throughout.
 202         * arc-nps400-tbl.h: Add long instructions taken from
 203         arc_long_opcodes table in arc-opc.c.
 204         * arc-opc.c: Update parameter types on insert/extract handlers.
 205         (arc_long_opcodes): Delete.
 206         (arc_num_long_opcodes): Delete.
 207         (arc_opcode_len): Update for more instruction lengths.
 208
 209 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 210
 211         * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
 212
 213 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 214
 215         * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
 216         with arc_opcode_len.
 217         (find_format_long_instructions): Likewise.
 218         * arc-opc.c (arc_opcode_len): New function.
 219
 220 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 221
 222         * arc-nps400-tbl.h: Fix some instruction masks.
 223
 224 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 225
 226         * i386-dis.c (REG_82): Removed.
 227         (X86_64_82_REG_0): Likewise.
 228         (X86_64_82_REG_1): Likewise.
 229         (X86_64_82_REG_2): Likewise.
 230         (X86_64_82_REG_3): Likewise.
 231         (X86_64_82_REG_4): Likewise.
 232         (X86_64_82_REG_5): Likewise.
 233         (X86_64_82_REG_6): Likewise.
 234         (X86_64_82_REG_7): Likewise.
 235         (X86_64_82): New.
 236         (dis386): Use X86_64_82 instead of REG_82.
 237         (reg_table): Remove REG_82.
 238         (x86_64_table): Add X86_64_82.  Remove X86_64_82_REG_0,
 239         X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
 240         X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
 241         X86_64_82_REG_7.
 242
 243 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 244
 245         PR binutils/20754
 246         * i386-dis.c (REG_82): New.
 247         (X86_64_82_REG_0): Likewise.
 248         (X86_64_82_REG_1): Likewise.
 249         (X86_64_82_REG_2): Likewise.
 250         (X86_64_82_REG_3): Likewise.
 251         (X86_64_82_REG_4): Likewise.
 252         (X86_64_82_REG_5): Likewise.
 253         (X86_64_82_REG_6): Likewise.
 254         (X86_64_82_REG_7): Likewise.
 255         (dis386): Use REG_82.
 256         (reg_table): Add REG_82.
 257         (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
 258         X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
 259         X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
 260
 261 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 262
 263         * i386-dis.c (REG_82): Renamed to ...
 264         (REG_83): This.
 265         (dis386): Updated.
 266         (reg_table): Likewise.
 267
 268 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 269
 270         * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
 271         * i386-dis-evex.h (evex_table): Updated.
 272         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
 273         CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 274         (cpu_flags): Add CpuAVX512_4VNNIW.
 275         * i386-opc.h (enum): (AVX512_4VNNIW): New.
 276         (i386_cpu_flags): Add cpuavx512_4vnniw.
 277         * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
 278         * i386-init.h: Regenerate.
 279         * i386-tbl.h: Ditto.
 280
 281 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 282
 283         * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
 284         PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
 285         * i386-dis-evex.h (evex_table): Updated.
 286         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
 287         CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 288         (cpu_flags): Add CpuAVX512_4FMAPS.
 289         (opcode_modifiers): Add ImplicitQuadGroup modifier.
 290         * i386-opc.h (AVX512_4FMAP): New.
 291         (i386_cpu_flags): Add cpuavx512_4fmaps.
 292         (ImplicitQuadGroup): New.
 293         (i386_opcode_modifier): Add implicitquadgroup.
 294         * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
 295         * i386-init.h: Regenerate.
 296         * i386-tbl.h: Ditto.
 297
 298 2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
 299             Andrew Waterman <andrew@sifive.com>
 300
 301         Add support for RISC-V architecture.
 302         * configure.ac: Add entry for bfd_riscv_arch.
 303         * configure: Regenerate.
 304         * disassemble.c (disassembler): Add support for riscv.
 305         (disassembler_usage): Likewise.
 306         * riscv-dis.c: New file.
 307         * riscv-opc.c: New file.
 308
 309 2016-10-21  H.J. Lu  <hongjiu.lu@intel.com>
 310
 311         * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
 312         (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
 313         (rm_table): Update the RM_0FAE_REG_7 entry.
 314         * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
 315         (cpu_flags): Remove CpuPCOMMIT.
 316         * i386-opc.h (CpuPCOMMIT): Removed.
 317         (i386_cpu_flags): Remove cpupcommit.
 318         * i386-opc.tbl: Remove pcommit.
 319         * i386-init.h: Regenerated.
 320         * i386-tbl.h: Likewise.
 321
 322 2016-10-20  H.J. Lu  <hongjiu.lu@intel.com>
 323
 324         PR binutis/20705
 325         * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
 326         the highest bit in VEX.vvvv for the 3-byte VEX prefix in
 327         32-bit mode.  Don't check vex.register_specifier in 32-bit
 328         mode.
 329         (OP_VEX): Check for invalid mask registers.
 330
 331 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 332
 333         PR binutis/20699
 334         * i386-dis.c (OP_E_memory): Check addr32flag in stead of
 335         sizeflag.
 336
 337 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 338
 339         PR binutis/20704
 340         * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
 341
 342 2016-10-18  Maciej W. Rozycki  <macro@imgtec.com>
 343
 344         * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
 345         local variable to `index_regno'.
 346
 347 2016-10-17  Cupertino Miranda  <cmiranda@synopsys.com>
 348
 349         * arc-tbl.h: Removed any "inv.+" instructions from the table.
 350
 351 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
 352
 353         * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
 354         usage on ISA basis.
 355
 356 2016-10-11  Jiong Wang  <jiong.wang@arm.com>
 357
 358         PR target/20666
 359         * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
 360
 361 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
 362
 363         PR target/20667
 364         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
 365         available.
 366
 367 2016-10-07  Alan Modra  <amodra@gmail.com>
 368
 369         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
 370
 371 2016-10-06  Alan Modra  <amodra@gmail.com>
 372
 373         * aarch64-opc.c: Spell fall through comments consistently.
 374         * i386-dis.c: Likewise.
 375         * aarch64-dis.c: Add missing fall through comments.
 376         * aarch64-opc.c: Likewise.
 377         * arc-dis.c: Likewise.
 378         * arm-dis.c: Likewise.
 379         * i386-dis.c: Likewise.
 380         * m68k-dis.c: Likewise.
 381         * mep-asm.c: Likewise.
 382         * ns32k-dis.c: Likewise.
 383         * sh-dis.c: Likewise.
 384         * tic4x-dis.c: Likewise.
 385         * tic6x-dis.c: Likewise.
 386         * vax-dis.c: Likewise.
 387
 388 2016-10-06  Alan Modra  <amodra@gmail.com>
 389
 390         * arc-ext.c (create_map): Add missing break.
 391         * msp430-decode.opc (encode_as): Likewise.
 392         * msp430-decode.c: Regenerate.
 393
 394 2016-10-06  Alan Modra  <amodra@gmail.com>
 395
 396         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
 397         * crx-dis.c (print_insn_crx): Likewise.
 398
 399 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 400
 401         PR binutils/20657
 402         * i386-dis.c (putop): Don't assign alt twice.
 403
 404 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
 405
 406         PR target/20553
 407         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
 408
 409 2016-09-29  Alan Modra  <amodra@gmail.com>
 410
 411         * ppc-opc.c (L): Make compulsory.
 412         (LOPT): New, optional form of L.
 413         (HTM_R): Define as LOPT.
 414         (L0, L1): Delete.
 415         (L32OPT): New, optional for 32-bit L.
 416         (L2OPT): New, 2-bit L for dcbf.
 417         (SVC_LEC): Update.
 418         (L2): Define.
 419         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
 420         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
 421         <dcbf>: Use L2OPT.
 422         <tlbiel, tlbie>: Use LOPT.
 423         <wclr, wclrall>: Use L2.
 424
 425 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
 426
 427         * Makefile.in: Regenerate.
 428         * configure: Likewise.
 429
 430 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 431
 432         * arc-ext-tbl.h (EXTINSN2OPF): Define.
 433         (EXTINSN2OP): Use EXTINSN2OPF.
 434         (bspeekm, bspop, modapp): New extension instructions.
 435         * arc-opc.c (F_DNZ_ND): Define.
 436         (F_DNZ_D): Likewise.
 437         (F_SIZEB1): Changed.
 438         (C_DNZ_D): Define.
 439         (C_HARD): Changed.
 440         * arc-tbl.h (dbnz): New instruction.
 441         (prealloc): Allow it for ARC EM.
 442         (xbfu): Likewise.
 443
 444 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 445
 446         * aarch64-opc.c (print_immediate_offset_address): Print spaces
 447         after commas in addresses.
 448         (aarch64_print_operand): Likewise.
 449
 450 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 451
 452         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
 453         rather than "should be" or "expected to be" in error messages.
 454
 455 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 456
 457         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
 458         (print_mnemonic_name): ...here.
 459         (print_comment): New function.
 460         (print_aarch64_insn): Call it.
 461         * aarch64-opc.c (aarch64_conds): Add SVE names.
 462         (aarch64_print_operand): Print alternative condition names in
 463         a comment.
 464
 465 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 466
 467         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 468         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 469         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 470         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 471         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 472         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 473         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 474         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 475         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 476         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 477         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 478         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 479         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 480         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 481         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 482         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 483         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 484         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 485         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 486         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 487         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 488         (aarch64_feature_sve): New variable.
 489         (SVE): New macro.
 490         (_SVE_INSN): Likewise.
 491         (aarch64_opcode_table): Add SVE instructions.
 492         * aarch64-opc.h (extract_fields): Declare.
 493         * aarch64-opc-2.c: Regenerate.
 494         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 495         * aarch64-asm-2.c: Regenerate.
 496         * aarch64-dis.c (extract_fields): Make global.
 497         (do_misc_decoding): Handle the new SVE aarch64_ops.
 498         * aarch64-dis-2.c: Regenerate.
 499
 500 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 501
 502         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 503         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 504         aarch64_field_kinds.
 505         * aarch64-opc.c (fields): Add corresponding entries.
 506         * aarch64-asm.c (aarch64_get_variant): New function.
 507         (aarch64_encode_variant_using_iclass): Likewise.
 508         (aarch64_opcode_encode): Call it.
 509         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 510         (aarch64_opcode_decode): Call it.
 511
 512 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 513
 514         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 515         and FP register operands.
 516         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 517         (FLD_SVE_Vn): New aarch64_field_kinds.
 518         * aarch64-opc.c (fields): Add corresponding entries.
 519         (aarch64_print_operand): Handle the new SVE core and FP register
 520         operands.
 521         * aarch64-opc-2.c: Regenerate.
 522         * aarch64-asm-2.c: Likewise.
 523         * aarch64-dis-2.c: Likewise.
 524
 525 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 526
 527         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 528         immediate operands.
 529         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 530         * aarch64-opc.c (fields): Add corresponding entry.
 531         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 532         operands.
 533         (aarch64_print_operand): Likewise.
 534         * aarch64-opc-2.c: Regenerate.
 535         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 536         (ins_sve_float_zero_one): New inserters.
 537         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 538         (aarch64_ins_sve_float_half_two): Likewise.
 539         (aarch64_ins_sve_float_zero_one): Likewise.
 540         * aarch64-asm-2.c: Regenerate.
 541         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 542         (ext_sve_float_zero_one): New extractors.
 543         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 544         (aarch64_ext_sve_float_half_two): Likewise.
 545         (aarch64_ext_sve_float_zero_one): Likewise.
 546         * aarch64-dis-2.c: Regenerate.
 547
 548 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 549
 550         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 551         integer immediate operands.
 552         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 553         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 554         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 555         * aarch64-opc.c (fields): Add corresponding entries.
 556         (operand_general_constraint_met_p): Handle the new SVE integer
 557         immediate operands.
 558         (aarch64_print_operand): Likewise.
 559         (aarch64_sve_dupm_mov_immediate_p): New function.
 560         * aarch64-opc-2.c: Regenerate.
 561         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 562         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 563         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 564         (aarch64_ins_limm): ...here.
 565         (aarch64_ins_inv_limm): New function.
 566         (aarch64_ins_sve_aimm): Likewise.
 567         (aarch64_ins_sve_asimm): Likewise.
 568         (aarch64_ins_sve_limm_mov): Likewise.
 569         (aarch64_ins_sve_shlimm): Likewise.
 570         (aarch64_ins_sve_shrimm): Likewise.
 571         * aarch64-asm-2.c: Regenerate.
 572         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 573         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 574         * aarch64-dis.c (decode_limm): New function, split out from...
 575         (aarch64_ext_limm): ...here.
 576         (aarch64_ext_inv_limm): New function.
 577         (decode_sve_aimm): Likewise.
 578         (aarch64_ext_sve_aimm): Likewise.
 579         (aarch64_ext_sve_asimm): Likewise.
 580         (aarch64_ext_sve_limm_mov): Likewise.
 581         (aarch64_top_bit): Likewise.
 582         (aarch64_ext_sve_shlimm): Likewise.
 583         (aarch64_ext_sve_shrimm): Likewise.
 584         * aarch64-dis-2.c: Regenerate.
 585
 586 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 587
 588         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 589         operands.
 590         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 591         the AARCH64_MOD_MUL_VL entry.
 592         (value_aligned_p): Cope with non-power-of-two alignments.
 593         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 594         (print_immediate_offset_address): Likewise.
 595         (aarch64_print_operand): Likewise.
 596         * aarch64-opc-2.c: Regenerate.
 597         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 598         (ins_sve_addr_ri_s9xvl): New inserters.
 599         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 600         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 601         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 602         * aarch64-asm-2.c: Regenerate.
 603         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 604         (ext_sve_addr_ri_s9xvl): New extractors.
 605         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 606         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 607         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 608         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 609         * aarch64-dis-2.c: Regenerate.
 610
 611 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 612
 613         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 614         address operands.
 615         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 616         (FLD_SVE_xs_22): New aarch64_field_kinds.
 617         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 618         (get_operand_specific_data): New function.
 619         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 620         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 621         (operand_general_constraint_met_p): Handle the new SVE address
 622         operands.
 623         (sve_reg): New array.
 624         (get_addr_sve_reg_name): New function.
 625         (aarch64_print_operand): Handle the new SVE address operands.
 626         * aarch64-opc-2.c: Regenerate.
 627         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 628         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 629         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 630         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 631         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 632         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 633         (aarch64_ins_sve_addr_zi_u5): Likewise.
 634         (aarch64_ins_sve_addr_zz): Likewise.
 635         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 636         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 637         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 638         * aarch64-asm-2.c: Regenerate.
 639         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 640         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 641         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 642         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 643         (aarch64_ext_sve_addr_ri_u6): Likewise.
 644         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 645         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 646         (aarch64_ext_sve_addr_zi_u5): Likewise.
 647         (aarch64_ext_sve_addr_zz): Likewise.
 648         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 649         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 650         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 651         * aarch64-dis-2.c: Regenerate.
 652
 653 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 654
 655         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 656         AARCH64_OPND_SVE_PATTERN_SCALED.
 657         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 658         * aarch64-opc.c (fields): Add a corresponding entry.
 659         (set_multiplier_out_of_range_error): New function.
 660         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 661         (operand_general_constraint_met_p): Handle
 662         AARCH64_OPND_SVE_PATTERN_SCALED.
 663         (print_register_offset_address): Use PRIi64 to print the
 664         shift amount.
 665         (aarch64_print_operand): Likewise.  Handle
 666         AARCH64_OPND_SVE_PATTERN_SCALED.
 667         * aarch64-opc-2.c: Regenerate.
 668         * aarch64-asm.h (ins_sve_scale): New inserter.
 669         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 670         * aarch64-asm-2.c: Regenerate.
 671         * aarch64-dis.h (ext_sve_scale): New inserter.
 672         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 673         * aarch64-dis-2.c: Regenerate.
 674
 675 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 676
 677         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 678         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 679         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 680         (FLD_SVE_prfop): Likewise.
 681         * aarch64-opc.c: Include libiberty.h.
 682         (aarch64_sve_pattern_array): New variable.
 683         (aarch64_sve_prfop_array): Likewise.
 684         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 685         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 686         AARCH64_OPND_SVE_PRFOP.
 687         * aarch64-asm-2.c: Regenerate.
 688         * aarch64-dis-2.c: Likewise.
 689         * aarch64-opc-2.c: Likewise.
 690
 691 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 692
 693         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 694         AARCH64_OPND_QLF_P_[ZM].
 695         (aarch64_print_operand): Print /z and /m where appropriate.
 696
 697 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 698
 699         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 700         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 701         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 702         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 703         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 704         * aarch64-opc.c (fields): Add corresponding entries here.
 705         (operand_general_constraint_met_p): Check that SVE register lists
 706         have the correct length.  Check the ranges of SVE index registers.
 707         Check for cases where p8-p15 are used in 3-bit predicate fields.
 708         (aarch64_print_operand): Handle the new SVE operands.
 709         * aarch64-opc-2.c: Regenerate.
 710         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 711         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 712         (aarch64_ins_sve_reglist): Likewise.
 713         * aarch64-asm-2.c: Regenerate.
 714         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 715         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 716         (aarch64_ext_sve_reglist): Likewise.
 717         * aarch64-dis-2.c: Regenerate.
 718
 719 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 720
 721         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 722         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 723         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 724         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 725         tied operands.
 726
 727 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 728
 729         * aarch64-opc.c (get_offset_int_reg_name): New function.
 730         (print_immediate_offset_address): Likewise.
 731         (print_register_offset_address): Take the base and offset
 732         registers as parameters.
 733         (aarch64_print_operand): Update caller accordingly.  Use
 734         print_immediate_offset_address.
 735
 736 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 737
 738         * aarch64-opc.c (BANK): New macro.
 739         (R32, R64): Take a register number as argument
 740         (int_reg): Use BANK.
 741
 742 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 743
 744         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 745         (aarch64_print_operand): Update accordingly.
 746
 747 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 748
 749         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 750         for FPIMM.
 751         * aarch64-asm.h (ins_fpimm): New inserter.
 752         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 753         * aarch64-asm-2.c: Regenerate.
 754         * aarch64-dis.h (ext_fpimm): New extractor.
 755         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 756         (aarch64_ext_fpimm): New function.
 757         * aarch64-dis-2.c: Regenerate.
 758
 759 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 760
 761         * aarch64-asm.c: Include libiberty.h.
 762         (insert_fields): New function.
 763         (aarch64_ins_imm): Use it.
 764         * aarch64-dis.c (extract_fields): New function.
 765         (aarch64_ext_imm): Use it.
 766
 767 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 768
 769         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 770         with an esize parameter.
 771         (operand_general_constraint_met_p): Update accordingly.
 772         Fix misindented code.
 773         * aarch64-asm.c (aarch64_ins_limm): Update call to
 774         aarch64_logical_immediate_p.
 775
 776 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 777
 778         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 779
 780 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 781
 782         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 783
 784 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 785
 786         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 787
 788 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 789
 790         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 791         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 792         xor3>: Delete mnemonics.
 793         <cp_abort>: Rename mnemonic from ...
 794         <cpabort>: ...to this.
 795         <setb>: Change to a X form instruction.
 796         <sync>: Change to 1 operand form.
 797         <copy>: Delete mnemonic.
 798         <copy_first>: Rename mnemonic from ...
 799         <copy>: ...to this.
 800         <paste, paste.>: Delete mnemonics.
 801         <paste_last>: Rename mnemonic from ...
 802         <paste.>: ...to this.
 803
 804 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 805
 806         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 807
 808 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 809
 810         * s390-mkopc.c (main): Support alternate arch strings.
 811
 812 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 813
 814         * s390-opc.txt: Fix kmctr instruction type.
 815
 816 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 817
 818         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 819         * i386-init.h: Regenerated.
 820
 821 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 822
 823         * opcodes/arc-dis.c (print_insn_arc): Changed.
 824
 825 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 826
 827         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 828         camellia_fl.
 829
 830 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 831
 832         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 833         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 834         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 835
 836 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 837
 838         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 839         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 840         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 841         PREFIX_MOD_3_0FAE_REG_4.
 842         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 843         PREFIX_MOD_3_0FAE_REG_4.
 844         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 845         (cpu_flags): Add CpuPTWRITE.
 846         * i386-opc.h (CpuPTWRITE): New.
 847         (i386_cpu_flags): Add cpuptwrite.
 848         * i386-opc.tbl: Add ptwrite instruction.
 849         * i386-init.h: Regenerated.
 850         * i386-tbl.h: Likewise.
 851
 852 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 853
 854         * arc-dis.h: Wrap around in extern "C".
 855
 856 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 857
 858         * aarch64-tbl.h (V8_2_INSN): New macro.
 859         (aarch64_opcode_table): Use it.
 860
 861 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 862
 863         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 864         CORE_INSN, __FP_INSN and SIMD_INSN.
 865
 866 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 867
 868         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 869         (aarch64_opcode_table): Update uses accordingly.
 870
 871 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 872         Kwok Cheung Yeung  <kcy@codesourcery.com>
 873
 874         opcodes/
 875         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 876         'e_cmplwi' to 'e_cmpli' instead.
 877         (OPVUPRT, OPVUPRT_MASK): Define.
 878         (powerpc_opcodes): Add E200Z4 insns.
 879         (vle_opcodes): Add context save/restore insns.
 880
 881 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 882
 883         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 884         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 885         "j".
 886
 887 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 888
 889         * arc-nps400-tbl.h: Change block comments to GNU format.
 890         * arc-dis.c: Add new globals addrtypenames,
 891         addrtypenames_max, and addtypeunknown.
 892         (get_addrtype): New function.
 893         (print_insn_arc): Print colons and address types when
 894         required.
 895         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 896         define insert and extract functions for all address types.
 897         (arc_operands): Add operands for colon and all address
 898         types.
 899         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 900         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 901         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 902         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 903         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 904         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 905
 906 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 907
 908         * configure: Regenerated.
 909
 910 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 911
 912         * arc-dis.c (skipclass): New structure.
 913         (decodelist): New variable.
 914         (is_compatible_p): New function.
 915         (new_element): Likewise.
 916         (skip_class_p): Likewise.
 917         (find_format_from_table): Use skip_class_p function.
 918         (find_format): Decode first the extension instructions.
 919         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 920         e_flags.
 921         (parse_option): New function.
 922         (parse_disassembler_options): Likewise.
 923         (print_arc_disassembler_options): Likewise.
 924         (print_insn_arc): Use parse_disassembler_options function.  Proper
 925         select ARCv2 cpu variant.
 926         * disassemble.c (disassembler_usage): Add ARC disassembler
 927         options.
 928
 929 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 930
 931         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 932         annotation from the "nal" entry and reorder it beyond "bltzal".
 933
 934 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 935
 936         * sparc-opc.c (ldtxa): New macro.
 937         (sparc_opcodes): Use the macro defined above to add entries for
 938         the LDTXA instructions.
 939         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 940         instruction.
 941
 942 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 943
 944         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 945         and "jmpc".
 946
 947 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 948
 949         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 950         (movzb): Adjust to cover all permitted suffixes.
 951         (movzw): New.
 952         * i386-tbl.h: Re-generate.
 953
 954 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 955
 956         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 957         (lgdt): Remove Tbyte from non-64-bit variant.
 958         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 959         xsaves64, xsavec64): Remove Disp16.
 960         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 961         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 962         64-bit variants.
 963         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 964         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 965         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 966         64-bit variants.
 967         * i386-tbl.h: Re-generate.
 968
 969 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 970
 971         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 972         * i386-tbl.h: Re-generate.
 973
 974 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 975
 976         * arm-dis.c (print_insn): Fix typo in comment.
 977
 978 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 979
 980         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 981         range of ldst_elemlist operands.
 982         (print_register_list): Use PRIi64 to print the index.
 983         (aarch64_print_operand): Likewise.
 984
 985 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 986
 987         * mcore-opc.h: Remove sentinal.
 988         * mcore-dis.c (print_insn_mcore): Adjust.
 989
 990 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 991
 992         * arc-opc.c: Correct description of availability of NPS400
 993         features.
 994
 995 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 996
 997         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 998         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 999         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1000         xor3>: New mnemonics.
1001         <setb>: Change to a VX form instruction.
1002         (insert_sh6): Add support for rldixor.
1003         (extract_sh6): Likewise.
1004
1005 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1006
1007         * arc-ext.h: Wrap in extern C.
1008
1009 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
1010
1011         * arc-dis.c (arc_insn_length): Add comment on instruction length.
1012         Use same method for determining instruction length on ARC700 and
1013         NPS-400.
1014         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1015         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1016         with the NPS400 subclass.
1017         * arc-opc.c: Likewise.
1018
1019 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1020
1021         * sparc-opc.c (rdasr): New macro.
1022         (wrasr): Likewise.
1023         (rdpr): Likewise.
1024         (wrpr): Likewise.
1025         (rdhpr): Likewise.
1026         (wrhpr): Likewise.
1027         (sparc_opcodes): Use the macros above to fix and expand the
1028         definition of read/write instructions from/to
1029         asr/privileged/hyperprivileged instructions.
1030         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1031         %hva_mask_nz.  Prefer softint_set and softint_clear over
1032         set_softint and clear_softint.
1033         (print_insn_sparc): Support %ver in Rd.
1034
1035 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1036
1037         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1038         architecture according to the hardware capabilities they require.
1039
1040 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1041
1042         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1043         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1044         bfd_mach_sparc_v9{c,d,e,v,m}.
1045         * sparc-opc.c (MASK_V9C): Define.
1046         (MASK_V9D): Likewise.
1047         (MASK_V9E): Likewise.
1048         (MASK_V9V): Likewise.
1049         (MASK_V9M): Likewise.
1050         (v6): Add MASK_V9{C,D,E,V,M}.
1051         (v6notlet): Likewise.
1052         (v7): Likewise.
1053         (v8): Likewise.
1054         (v9): Likewise.
1055         (v9andleon): Likewise.
1056         (v9a): Likewise.
1057         (v9b): Likewise.
1058         (v9c): Define.
1059         (v9d): Likewise.
1060         (v9e): Likewise.
1061         (v9v): Likewise.
1062         (v9m): Likewise.
1063         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1064
1065 2016-06-15  Nick Clifton  <nickc@redhat.com>
1066
1067         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1068         constants to match expected behaviour.
1069         (nds32_parse_opcode): Likewise.  Also for whitespace.
1070
1071 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
1072
1073         * arc-opc.c (extract_rhv1): Extract value from insn.
1074
1075 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1076
1077         * arc-nps400-tbl.h: Add ldbit instruction.
1078         * arc-opc.c: Add flag classes required for ldbit.
1079
1080 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1081
1082         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1083         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1084         support the above instructions.
1085
1086 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1087
1088         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1089         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1090         csma, cbba, zncv, and hofs.
1091         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1092         support the above instructions.
1093
1094 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1095
1096         * arc-nps400-tbl.h: Add andab and orab instructions.
1097
1098 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1099
1100         * arc-nps400-tbl.h: Add addl-like instructions.
1101
1102 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1103
1104         * arc-nps400-tbl.h: Add mxb and imxb instructions.
1105
1106 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1107
1108         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1109         instructions.
1110
1111 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1112
1113         * s390-dis.c (option_use_insn_len_bits_p): New file scope
1114         variable.
1115         (init_disasm): Handle new command line option "insnlength".
1116         (print_s390_disassembler_options): Mention new option in help
1117         output.
1118         (print_insn_s390): Use the encoded insn length when dumping
1119         unknown instructions.
1120
1121 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
1122
1123         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1124          to the address and set as symbol address for LDS/ STS immediate operands.
1125
1126 2016-06-07  Alan Modra  <amodra@gmail.com>
1127
1128         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
1129         cpu for "vle" to e500.
1130         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1131         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1132         (PPCNONE): Delete, substitute throughout.
1133         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
1134         except for major opcode 4 and 31.
1135         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1136
1137 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
1138
1139         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1140         ARM_EXT_RAS in relevant entries.
1141
1142 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
1143
1144         PR binutils/20196
1145         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1146         opcodes for E6500.
1147
1148 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
1149
1150         PR binutis/18386
1151         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1152         (indir_v_mode): New.
1153         Add comments for '&'.
1154         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1155         (putop): Handle '&'.
1156         (intel_operand_size): Handle indir_v_mode.
1157         (OP_E_register): Likewise.
1158         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
1159         64-bit indirect call/jmp for AMD64.
1160         * i386-tbl.h: Regenerated
1161
1162 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1163
1164         * arc-dis.c (struct arc_operand_iterator): New structure.
1165         (find_format_from_table): All the old content from find_format,
1166         with some minor adjustments, and parameter renaming.
1167         (find_format_long_instructions): New function.
1168         (find_format): Rewritten.
1169         (arc_insn_length): Add LSB parameter.
1170         (extract_operand_value): New function.
1171         (operand_iterator_next): New function.
1172         (print_insn_arc): Use new functions to find opcode, and iterator
1173         over operands.
1174         * arc-opc.c (insert_nps_3bit_dst_short): New function.
1175         (extract_nps_3bit_dst_short): New function.
1176         (insert_nps_3bit_src2_short): New function.
1177         (extract_nps_3bit_src2_short): New function.
1178         (insert_nps_bitop1_size): New function.
1179         (extract_nps_bitop1_size): New function.
1180         (insert_nps_bitop2_size): New function.
1181         (extract_nps_bitop2_size): New function.
1182         (insert_nps_bitop_mod4_msb): New function.
1183         (extract_nps_bitop_mod4_msb): New function.
1184         (insert_nps_bitop_mod4_lsb): New function.
1185         (extract_nps_bitop_mod4_lsb): New function.
1186         (insert_nps_bitop_dst_pos3_pos4): New function.
1187         (extract_nps_bitop_dst_pos3_pos4): New function.
1188         (insert_nps_bitop_ins_ext): New function.
1189         (extract_nps_bitop_ins_ext): New function.
1190         (arc_operands): Add new operands.
1191         (arc_long_opcodes): New global array.
1192         (arc_num_long_opcodes): New global.
1193         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1194
1195 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1196
1197         * nds32-asm.h: Add extern "C".
1198         * sh-opc.h: Likewise.
1199
1200 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
1201
1202         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1203         0,b,limm to the rflt instruction.
1204
1205 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1206
1207         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1208         constant.
1209
1210 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
1211
1212         PR gas/20145
1213         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1214         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1215         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1216         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1217         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1218         * i386-init.h: Regenerated.
1219
1220 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1221
1222         PR gas/20145
1223         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
1224         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
1225         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1226         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1227         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
1228         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1229         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1230         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
1231         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1232         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1233         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
1234         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
1235         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
1236         CpuRegMask for AVX512.
1237         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1238         and CpuRegMask.
1239         (set_bitfield_from_cpu_flag_init): New function.
1240         (set_bitfield): Remove const on f.  Call
1241         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1242         * i386-opc.h (CpuRegMMX): New.
1243         (CpuRegXMM): Likewise.
1244         (CpuRegYMM): Likewise.
1245         (CpuRegZMM): Likewise.
1246         (CpuRegMask): Likewise.
1247         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1248         and cpuregmask.
1249         * i386-init.h: Regenerated.
1250         * i386-tbl.h: Likewise.
1251
1252 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1253
1254         PR gas/20154
1255         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1256         (opcode_modifiers): Add AMD64 and Intel64.
1257         (main): Properly verify CpuMax.
1258         * i386-opc.h (CpuAMD64): Removed.
1259         (CpuIntel64): Likewise.
1260         (CpuMax): Set to CpuNo64.
1261         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1262         (AMD64): New.
1263         (Intel64): Likewise.
1264         (i386_opcode_modifier): Add amd64 and intel64.
1265         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1266         on call and jmp.
1267         * i386-init.h: Regenerated.
1268         * i386-tbl.h: Likewise.
1269
1270 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1271
1272         PR gas/20154
1273         * i386-gen.c (main): Fail if CpuMax is incorrect.
1274         * i386-opc.h (CpuMax): Set to CpuIntel64.
1275         * i386-tbl.h: Regenerated.
1276
1277 2016-05-27  Nick Clifton  <nickc@redhat.com>
1278
1279         PR target/20150
1280         * msp430-dis.c (msp430dis_read_two_bytes): New function.
1281         (msp430dis_opcode_unsigned): New function.
1282         (msp430dis_opcode_signed): New function.
1283         (msp430_singleoperand): Use the new opcode reading functions.
1284         Only disassenmble bytes if they were successfully read.
1285         (msp430_doubleoperand): Likewise.
1286         (msp430_branchinstr): Likewise.
1287         (msp430x_callx_instr): Likewise.
1288         (print_insn_msp430): Check that it is safe to read bytes before
1289         attempting disassembly.  Use the new opcode reading functions.
1290
1291 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
1292
1293         * ppc-opc.c (CY): New define.  Document it.
1294         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1295
1296 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1297
1298         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1299         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1300         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
1301         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1302         CPU_ANY_AVX_FLAGS.
1303         * i386-init.h: Regenerated.
1304
1305 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1306
1307         PR gas/20141
1308         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1309         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1310         * i386-init.h: Regenerated.
1311
1312 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1313
1314         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1315         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
1316         * i386-init.h: Regenerated.
1317
1318 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1319
1320         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1321         information.
1322         (print_insn_arc): Set insn_type information.
1323         * arc-opc.c (C_CC): Add F_CLASS_COND.
1324         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1325         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1326         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1327         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1328         (brne, brne_s, jeq_s, jne_s): Likewise.
1329
1330 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1331
1332         * arc-tbl.h (neg): New instruction variant.
1333
1334 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
1335
1336         * arc-dis.c (find_format, find_format, get_auxreg)
1337         (print_insn_arc): Changed.
1338         * arc-ext.h (INSERT_XOP): Likewise.
1339
1340 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1341
1342         * tic54x-dis.c (sprint_mmr): Adjust.
1343         * tic54x-opc.c: Likewise.
1344
1345 2016-05-19  Alan Modra  <amodra@gmail.com>
1346
1347         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1348
1349 2016-05-19  Alan Modra  <amodra@gmail.com>
1350
1351         * ppc-opc.c: Formatting.
1352         (NSISIGNOPT): Define.
1353         (powerpc_opcodes <subis>): Use NSISIGNOPT.
1354
1355 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
1356
1357         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1358         replacing references to `micromips_ase' throughout.
1359         (_print_insn_mips): Don't use file-level microMIPS annotation to
1360         determine the disassembly mode with the symbol table.
1361
1362 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1363
1364         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1365
1366 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1367
1368         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1369         mips64r6.
1370         * mips-opc.c (D34): New macro.
1371         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1372
1373 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1374
1375         * i386-dis.c (prefix_table): Add RDPID instruction.
1376         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1377         (cpu_flags): Add RDPID bitfield.
1378         * i386-opc.h (enum): Add RDPID element.
1379         (i386_cpu_flags): Add RDPID field.
1380         * i386-opc.tbl: Add RDPID instruction.
1381         * i386-init.h: Regenerate.
1382         * i386-tbl.h: Regenerate.
1383
1384 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1385
1386         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1387         branch type of a symbol.
1388         (print_insn): Likewise.
1389
1390 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1391
1392         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1393         Mainline Security Extensions instructions.
1394         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1395         Extensions instructions.
1396         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1397         instructions.
1398         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1399         special registers.
1400
1401 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1402
1403         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1404
1405 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1406
1407         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1408         (arcExtMap_genOpcode): Likewise.
1409         * arc-opc.c (arg_32bit_rc): Define new variable.
1410         (arg_32bit_u6): Likewise.
1411         (arg_32bit_limm): Likewise.
1412
1413 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1414
1415         * aarch64-gen.c (VERIFIER): Define.
1416         * aarch64-opc.c (VERIFIER): Define.
1417         (verify_ldpsw): Use static linkage.
1418         * aarch64-opc.h (verify_ldpsw): Remove.
1419         * aarch64-tbl.h: Use VERIFIER for verifiers.
1420
1421 2016-04-28  Nick Clifton  <nickc@redhat.com>
1422
1423         PR target/19722
1424         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1425         * aarch64-opc.c (verify_ldpsw): New function.
1426         * aarch64-opc.h (verify_ldpsw): New prototype.
1427         * aarch64-tbl.h: Add initialiser for verifier field.
1428         (LDPSW): Set verifier to verify_ldpsw.
1429
1430 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1431
1432         PR binutils/19983
1433         PR binutils/19984
1434         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1435         smaller than address size.
1436
1437 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1438
1439         * alpha-dis.c: Regenerate.
1440         * crx-dis.c: Likewise.
1441         * disassemble.c: Likewise.
1442         * epiphany-opc.c: Likewise.
1443         * fr30-opc.c: Likewise.
1444         * frv-opc.c: Likewise.
1445         * ip2k-opc.c: Likewise.
1446         * iq2000-opc.c: Likewise.
1447         * lm32-opc.c: Likewise.
1448         * lm32-opinst.c: Likewise.
1449         * m32c-opc.c: Likewise.
1450         * m32r-opc.c: Likewise.
1451         * m32r-opinst.c: Likewise.
1452         * mep-opc.c: Likewise.
1453         * mt-opc.c: Likewise.
1454         * or1k-opc.c: Likewise.
1455         * or1k-opinst.c: Likewise.
1456         * tic80-opc.c: Likewise.
1457         * xc16x-opc.c: Likewise.
1458         * xstormy16-opc.c: Likewise.
1459
1460 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1461
1462         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1463         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1464         calcsd, and calcxd instructions.
1465         * arc-opc.c (insert_nps_bitop_size): Delete.
1466         (extract_nps_bitop_size): Delete.
1467         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1468         (extract_nps_qcmp_m3): Define.
1469         (extract_nps_qcmp_m2): Define.
1470         (extract_nps_qcmp_m1): Define.
1471         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1472         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1473         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1474         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1475         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1476         NPS_QCMP_M3.
1477
1478 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1479
1480         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1481
1482 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1483
1484         * Makefile.in: Regenerated with automake 1.11.6.
1485         * aclocal.m4: Likewise.
1486
1487 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1488
1489         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1490         instructions.
1491         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1492         (extract_nps_cmem_uimm16): New function.
1493         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1494
1495 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1496
1497         * arc-dis.c (arc_insn_length): New function.
1498         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1499         (find_format): Change insnLen parameter to unsigned.
1500
1501 2016-04-13  Nick Clifton  <nickc@redhat.com>
1502
1503         PR target/19937
1504         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1505         the LD.B and LD.BU instructions.
1506
1507 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1508
1509         * arc-dis.c (find_format): Check for extension flags.
1510         (print_flags): New function.
1511         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1512         .extAuxRegister.
1513         * arc-ext.c (arcExtMap_coreRegName): Use
1514         LAST_EXTENSION_CORE_REGISTER.
1515         (arcExtMap_coreReadWrite): Likewise.
1516         (dump_ARC_extmap): Update printing.
1517         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1518         (arc_aux_regs): Add cpu field.
1519         * arc-regs.h: Add cpu field, lower case name aux registers.
1520
1521 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1522
1523         * arc-tbl.h: Add rtsc, sleep with no arguments.
1524
1525 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1526
1527         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1528         Initialize.
1529         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1530         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1531         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1532         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1533         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1534         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1535         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1536         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1537         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1538         (arc_opcode arc_opcodes): Null terminate the array.
1539         (arc_num_opcodes): Remove.
1540         * arc-ext.h (INSERT_XOP): Define.
1541         (extInstruction_t): Likewise.
1542         (arcExtMap_instName): Delete.
1543         (arcExtMap_insn): New function.
1544         (arcExtMap_genOpcode): Likewise.
1545         * arc-ext.c (ExtInstruction): Remove.
1546         (create_map): Zero initialize instruction fields.
1547         (arcExtMap_instName): Remove.
1548         (arcExtMap_insn): New function.
1549         (dump_ARC_extmap): More info while debuging.
1550         (arcExtMap_genOpcode): New function.
1551         * arc-dis.c (find_format): New function.
1552         (print_insn_arc): Use find_format.
1553         (arc_get_disassembler): Enable dump_ARC_extmap only when
1554         debugging.
1555
1556 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1557
1558         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1559         instruction bits out.
1560
1561 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1562
1563         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1564         * arc-opc.c (arc_flag_operands): Add new flags.
1565         (arc_flag_classes): Add new classes.
1566
1567 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1568
1569         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1570
1571 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1572
1573         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1574         encode1, rflt, crc16, and crc32 instructions.
1575         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1576         (arc_flag_classes): Add C_NPS_R.
1577         (insert_nps_bitop_size_2b): New function.
1578         (extract_nps_bitop_size_2b): Likewise.
1579         (insert_nps_bitop_uimm8): Likewise.
1580         (extract_nps_bitop_uimm8): Likewise.
1581         (arc_operands): Add new operand entries.
1582
1583 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1584
1585         * arc-regs.h: Add a new subclass field.  Add double assist
1586         accumulator register values.
1587         * arc-tbl.h: Use DPA subclass to mark the double assist
1588         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1589         * arc-opc.c (RSP): Define instead of SP.
1590         (arc_aux_regs): Add the subclass field.
1591
1592 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1593
1594         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1595
1596 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1597
1598         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1599         NPS_R_SRC1.
1600
1601 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1602
1603         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1604         issues.  No functional changes.
1605
1606 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1607
1608         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1609         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1610         (RTT): Remove duplicate.
1611         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1612         (PCT_CONFIG*): Remove.
1613         (D1L, D1H, D2H, D2L): Define.
1614
1615 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1616
1617         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1618
1619 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1620
1621         * arc-tbl.h (invld07): Remove.
1622         * arc-ext-tbl.h: New file.
1623         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1624         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1625
1626 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1627
1628         Fix -Wstack-usage warnings.
1629         * aarch64-dis.c (print_operands): Substitute size.
1630         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1631
1632 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1633
1634         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1635         to get a proper diagnostic when an invalid ASR register is used.
1636
1637 2016-03-22  Nick Clifton  <nickc@redhat.com>
1638
1639         * configure: Regenerate.
1640
1641 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1642
1643         * arc-nps400-tbl.h: New file.
1644         * arc-opc.c: Add top level comment.
1645         (insert_nps_3bit_dst): New function.
1646         (extract_nps_3bit_dst): New function.
1647         (insert_nps_3bit_src2): New function.
1648         (extract_nps_3bit_src2): New function.
1649         (insert_nps_bitop_size): New function.
1650         (extract_nps_bitop_size): New function.
1651         (arc_flag_operands): Add nps400 entries.
1652         (arc_flag_classes): Add nps400 entries.
1653         (arc_operands): Add nps400 entries.
1654         (arc_opcodes): Add nps400 include.
1655
1656 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1657
1658         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1659         the new class enum values.
1660
1661 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1662
1663         * arc-dis.c (print_insn_arc): Handle nps400.
1664
1665 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1666
1667         * arc-opc.c (BASE): Delete.
1668
1669 2016-03-18  Nick Clifton  <nickc@redhat.com>
1670
1671         PR target/19721
1672         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1673         of MOV insn that aliases an ORR insn.
1674
1675 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1676
1677         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1678
1679 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1680
1681         * mcore-opc.h: Add const qualifiers.
1682         * microblaze-opc.h (struct op_code_struct): Likewise.
1683         * sh-opc.h: Likewise.
1684         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1685         (tic4x_print_op): Likewise.
1686
1687 2016-03-02  Alan Modra  <amodra@gmail.com>
1688
1689         * or1k-desc.h: Regenerate.
1690         * fr30-ibld.c: Regenerate.
1691         * rl78-decode.c: Regenerate.
1692
1693 2016-03-01  Nick Clifton  <nickc@redhat.com>
1694
1695         PR target/19747
1696         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1697
1698 2016-02-24  Renlin Li  <renlin.li@arm.com>
1699
1700         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1701         (print_insn_coprocessor): Support fp16 instructions.
1702
1703 2016-02-24  Renlin Li  <renlin.li@arm.com>
1704
1705         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1706         vminnm, vrint(mpna).
1707
1708 2016-02-24  Renlin Li  <renlin.li@arm.com>
1709
1710         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1711         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1712
1713 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1714
1715         * i386-dis.c (print_insn): Parenthesize expression to prevent
1716         truncated addresses.
1717         (OP_J): Likewise.
1718
1719 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1720             Janek van Oirschot  <jvanoirs@synopsys.com>
1721
1722         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1723         variable.
1724
1725 2016-02-04  Nick Clifton  <nickc@redhat.com>
1726
1727         PR target/19561
1728         * msp430-dis.c (print_insn_msp430): Add a special case for
1729         decoding an RRC instruction with the ZC bit set in the extension
1730         word.
1731
1732 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1733
1734         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1735         * epiphany-ibld.c: Regenerate.
1736         * fr30-ibld.c: Regenerate.
1737         * frv-ibld.c: Regenerate.
1738         * ip2k-ibld.c: Regenerate.
1739         * iq2000-ibld.c: Regenerate.
1740         * lm32-ibld.c: Regenerate.
1741         * m32c-ibld.c: Regenerate.
1742         * m32r-ibld.c: Regenerate.
1743         * mep-ibld.c: Regenerate.
1744         * mt-ibld.c: Regenerate.
1745         * or1k-ibld.c: Regenerate.
1746         * xc16x-ibld.c: Regenerate.
1747         * xstormy16-ibld.c: Regenerate.
1748
1749 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1750
1751         * epiphany-dis.c: Regenerated from latest cpu files.
1752
1753 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1754
1755         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1756         test bit.
1757
1758 2016-01-25  Renlin Li  <renlin.li@arm.com>
1759
1760         * arm-dis.c (mapping_symbol_for_insn): New function.
1761         (find_ifthen_state): Call mapping_symbol_for_insn().
1762
1763 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1764
1765         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1766         of MSR UAO immediate operand.
1767
1768 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1769
1770         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1771         instruction support.
1772
1773 2016-01-17  Alan Modra  <amodra@gmail.com>
1774
1775         * configure: Regenerate.
1776
1777 2016-01-14  Nick Clifton  <nickc@redhat.com>
1778
1779         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1780         instructions that can support stack pointer operations.
1781         * rl78-decode.c: Regenerate.
1782         * rl78-dis.c: Fix display of stack pointer in MOVW based
1783         instructions.
1784
1785 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1786
1787         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1788         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1789         erxtatus_el1 and erxaddr_el1.
1790
1791 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1792
1793         * arm-dis.c (arm_opcodes): Add "esb".
1794         (thumb_opcodes): Likewise.
1795
1796 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1797
1798         * ppc-opc.c <xscmpnedp>: Delete.
1799         <xvcmpnedp>: Likewise.
1800         <xvcmpnedp.>: Likewise.
1801         <xvcmpnesp>: Likewise.
1802         <xvcmpnesp.>: Likewise.
1803
1804 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1805
1806         PR gas/13050
1807         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1808         addition to ISA_A.
1809
1810 2016-01-01  Alan Modra  <amodra@gmail.com>
1811
1812         Update year range in copyright notice of all files.
1813
1814 For older changes see ChangeLog-2015
1815 \f
1816 Copyright (C) 2016 Free Software Foundation, Inc.
1817
1818 Copying and distribution of this file, with or without modification,
1819 are permitted in any medium without royalty provided the copyright
1820 notice and this notice are preserved.
1821
1822 Local Variables:
1823 mode: change-log
1824 left-margin: 8
1825 fill-column: 74
1826 version-control: never
1827 End: