opcodes/ChangeLog

   1 2021-03-24  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-gen.c (output_i386_opcode): Drop processing of
   4         opcode_length. Calculate length from base_opcode. Adjust prefix
   5         encoding determination.
   6         (process_i386_opcodes): Drop output of fake opcode_length.
   7         * i386-opc.h (struct insn_template): Drop opcode_length field.
   8         * i386-opc.tbl: Drop opcode length field from all templates.
   9         * i386-tbl.h: Re-generate.
  10
  11 2021-03-24  Jan Beulich  <jbeulich@suse.com>
  12
  13         * i386-gen.c (process_i386_opcode_modifier): Return void. New
  14         parameter "prefix". Drop local variable "regular_encoding".
  15         Record prefix setting / check for consistency.
  16         (output_i386_opcode): Parse opcode_length and base_opcode
  17         earlier. Derive prefix encoding. Drop no longer applicable
  18         consistency checking. Adjust process_i386_opcode_modifier()
  19         invocation.
  20         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
  21         invocation.
  22         * i386-tbl.h: Re-generate.
  23
  24 2021-03-24  Jan Beulich  <jbeulich@suse.com>
  25
  26         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
  27         check.
  28         * i386-opc.h (Prefix_*): Move #define-s.
  29         * i386-opc.tbl: Move pseudo prefix enumerator values to
  30         extension opcode field. Introduce pseudopfx template.
  31         * i386-tbl.h: Re-generate.
  32
  33 2021-03-23  Jan Beulich  <jbeulich@suse.com>
  34
  35         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
  36         comment.
  37         * i386-tbl.h: Re-generate.
  38
  39 2021-03-23  Jan Beulich  <jbeulich@suse.com>
  40
  41         * i386-opc.h (struct insn_template): Move cpu_flags field past
  42         opcode_modifier one.
  43         * i386-tbl.h: Re-generate.
  44
  45 2021-03-23  Jan Beulich  <jbeulich@suse.com>
  46
  47         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
  48         * i386-opc.h (OpcodeSpace): New enumerator.
  49         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
  50         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
  51         SPACE_XOP09, SPACE_XOP0A): ... respectively.
  52         (struct i386_opcode_modifier): New field opcodespace. Shrink
  53         opcodeprefix field.
  54         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
  55         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
  56         OpcodePrefix uses.
  57         * i386-tbl.h: Re-generate.
  58
  59 2021-03-22  Martin Liska  <mliska@suse.cz>
  60
  61         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
  62         * arc-dis.c (parse_option): Likewise.
  63         * arm-dis.c (parse_arm_disassembler_options): Likewise.
  64         * cris-dis.c (print_with_operands): Likewise.
  65         * h8300-dis.c (bfd_h8_disassemble): Likewise.
  66         * i386-dis.c (print_insn): Likewise.
  67         * ia64-gen.c (fetch_insn_class): Likewise.
  68         (parse_resource_users): Likewise.
  69         (in_iclass): Likewise.
  70         (lookup_specifier): Likewise.
  71         (insert_opcode_dependencies): Likewise.
  72         * mips-dis.c (parse_mips_ase_option): Likewise.
  73         (parse_mips_dis_option): Likewise.
  74         * s390-dis.c (disassemble_init_s390): Likewise.
  75         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
  76
  77 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
  78
  79         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
  80
  81 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  82
  83         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
  84         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
  85
  86 2021-03-12  Alan Modra  <amodra@gmail.com>
  87
  88         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
  89
  90 2021-03-11  Jan Beulich  <jbeulich@suse.com>
  91
  92         * i386-dis.c (OP_XMM): Re-order checks.
  93
  94 2021-03-11  Jan Beulich  <jbeulich@suse.com>
  95
  96         * i386-dis.c (putop): Drop need_vex check when also checking
  97         vex.evex.
  98         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
  99         checking vex.b.
 100
 101 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 102
 103         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 104         checks. Move case label past broadcast check.
 105
 106 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 107
 108         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 109         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 110         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 111         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 112         EVEX_W_0F38C7_M_0_L_2): Delete.
 113         (REG_EVEX_0F38C7_M_0_L_2): New.
 114         (intel_operand_size): Handle VEX and EVEX the same for
 115         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 116         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 117         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 118         vex_vsib_q_w_d_mode uses.
 119         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 120         0F38A1, and 0F38A3 entries.
 121         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 122         entry.
 123         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 124         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 125         0F38A3 entries.
 126
 127 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 128
 129         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 130         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 131         MOD_VEX_0FXOP_09_12): Rename to ...
 132         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 133         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 134         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 135         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 136         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 137         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 138         (reg_table): Adjust comments.
 139         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 140         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 141         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 142         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 143         (vex_len_table): Adjust opcode 0A_12 entry.
 144         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 145         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 146         (rm_table): Move hreset entry.
 147
 148 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 149
 150         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 151         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 152         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 153         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 154         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 155         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 156         (get_valid_dis386): Also handle 512-bit vector length when
 157         vectoring into vex_len_table[].
 158         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 159         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 160         entries.
 161         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 162         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 163         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 164         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 165         entries.
 166
 167 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 168
 169         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 170         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 171         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 172         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 173         entries.
 174         * i386-dis-evex-len.h (evex_len_table): Likewise.
 175         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 176
 177 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 178
 179         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 180         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 181         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 182         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 183         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 184         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 185         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 186         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 187         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 188         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 189         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 190         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 191         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 192         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 193         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 194         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 195         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 196         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 197         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 198         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 199         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 200         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 201         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 202         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 203         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 204         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 205         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 206         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 207         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 208         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 209         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 210         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 211         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 212         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 213         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 214         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 215         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 216         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 217         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 218         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 219         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 220         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 221         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 222         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 223         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 224         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 225         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 226         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 227         EVEX_W_0F3A43_L_n): New.
 228         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 229         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 230         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 231         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 232         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 233         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 234         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 235         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 236         0F385B, 0F38C6, and 0F38C7 entries.
 237         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 238         0F38C6 and 0F38C7.
 239         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 240         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 241         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 242         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 243
 244 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 245
 246         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 247         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 248         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 249         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 250         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 251         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 252         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 253         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 254         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 255         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 256         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 257         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 258         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 259         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 260         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 261         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 262         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 263         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 264         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 265         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 266         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 267         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 268         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 269         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 270         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 271         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 272         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 273         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 274         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 275         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 276         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 277         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 278         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 279         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 280         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 281         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 282         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 283         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 284         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 285         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 286         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 287         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 288         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 289         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 290         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 291         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 292         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 293         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 294         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 295         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 296         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 297         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 298         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 299         VEX_W_0F99_P_2_LEN_0): Delete.
 300         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 301         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 302         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 303         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 304         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 305         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 306         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 307         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 308         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 309         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 310         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 311         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 312         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 313         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 314         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 315         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 316         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 317         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 318         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 319         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 320         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 321         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 322         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 323         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 324         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 325         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 326         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 327         (prefix_table): No longer link to vex_len_table[] for opcodes
 328         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 329         0F92, 0F93, 0F98, and 0F99.
 330         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 331         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 332         0F98, and 0F99.
 333         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 334         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 335         0F98, and 0F99.
 336         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 337         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 338         0F98, and 0F99.
 339         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 340         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 341         0F98, and 0F99.
 342
 343 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 344
 345         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 346         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 347         REG_VEX_0F73_M_0 respectively.
 348         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 349         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 350         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 351         MOD_VEX_0F73_REG_7): Delete.
 352         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 353         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 354         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 355         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 356         PREFIX_VEX_0F3AF0_L_0 respectively.
 357         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 358         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 359         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 360         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 361         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 362         VEX_LEN_0F38F7): New.
 363         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 364         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 365         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 366         0F38F3.
 367         (prefix_table): No longer link to vex_len_table[] for opcodes
 368         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 369         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 370         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 371         0F38F6, 0F38F7, and 0F3AF0.
 372         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 373         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 374         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 375         0F73.
 376
 377 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 378
 379         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 380         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 381         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 382         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 383         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 384         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 385         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 386         73.
 387         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 388         0F72, and 0F73.
 389         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 390         0F73.
 391
 392 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 393
 394         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 395         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 396         (reg_table): Don't link to mod_table[] where not needed. Add
 397         PREFIX_IGNORED to nop entries.
 398         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 399         (mod_table): Add nop entries next to prefetch ones. Drop
 400         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 401         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 402         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 403         PREFIX_OPCODE from endbr* entries.
 404         (get_valid_dis386): Also consider entry's name when zapping
 405         vindex.
 406         (print_insn): Handle PREFIX_IGNORED.
 407
 408 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 409
 410         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 411         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 412         element.
 413         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 414         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 415         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 416         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 417         (struct i386_opcode_modifier): Delete notrackprefixok,
 418         islockable, hleprefixok, and repprefixok fields. Add prefixok
 419         field.
 420         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 421         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 422         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 423         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 424         Replace HLEPrefixOk.
 425         * opcodes/i386-tbl.h: Re-generate.
 426
 427 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 428
 429         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 430         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 431         64-bit form.
 432         * opcodes/i386-tbl.h: Re-generate.
 433
 434 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 435
 436         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 437         for {} instead of {0}. Don't look for '0'.
 438         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 439         size specifiers.
 440
 441 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 442
 443         PR 27158
 444         * riscv-dis.c (print_insn_args): Updated encoding macros.
 445         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 446         (match_c_addi16sp): Updated encoding macros.
 447         (match_c_lui): Likewise.
 448         (match_c_lui_with_hint): Likewise.
 449         (match_c_addi4spn): Likewise.
 450         (match_c_slli): Likewise.
 451         (match_slli_as_c_slli): Likewise.
 452         (match_c_slli64): Likewise.
 453         (match_srxi_as_c_srxi): Likewise.
 454         (riscv_insn_types): Added .insn css/cl/cs.
 455
 456 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 457
 458         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 459         (default_priv_spec): Updated type to riscv_spec_class.
 460         (parse_riscv_dis_option): Updated.
 461         * riscv-opc.c: Moved stuff and make the file tidy.
 462
 463 2021-02-17  Alan Modra  <amodra@gmail.com>
 464
 465         * wasm32-dis.c: Include limits.h.
 466         (CHAR_BIT): Provide backup define.
 467         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 468         Correct signed overflow checking.
 469
 470 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 471
 472         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 473         * i386-tbl.h: Re-generate.
 474
 475 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 476
 477         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 478         Oword.
 479         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 480
 481 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 482
 483         * s390-mkopc.c (main): Accept arch14 as cpu string.
 484         * s390-opc.txt: Add new arch14 instructions.
 485
 486 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 487
 488         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 489         favour of LIBINTL.
 490         * configure: Regenerated.
 491
 492 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 493
 494         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 495         * tic54x-opc.c (regs): Rename to ...
 496         (tic54x_regs): ... this.
 497         (mmregs): Rename to ...
 498         (tic54x_mmregs): ... this.
 499         (condition_codes): Rename to ...
 500         (tic54x_condition_codes): ... this.
 501         (cc2_codes): Rename to ...
 502         (tic54x_cc2_codes): ... this.
 503         (cc3_codes): Rename to ...
 504         (tic54x_cc3_codes): ... this.
 505         (status_bits): Rename to ...
 506         (tic54x_status_bits): ... this.
 507         (misc_symbols): Rename to ...
 508         (tic54x_misc_symbols): ... this.
 509
 510 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 511
 512         * riscv-opc.c (MASK_RVB_IMM): Removed.
 513         (riscv_opcodes): Removed zb* instructions.
 514         (riscv_ext_version_table): Removed versions for zb*.
 515
 516 2021-01-26  Alan Modra  <amodra@gmail.com>
 517
 518         * i386-gen.c (parse_template): Ensure entire template_instance
 519         is initialised.
 520
 521 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 522
 523         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 524         (riscv_fpr_names_abi): Likewise.
 525         (riscv_opcodes): Likewise.
 526         (riscv_insn_types): Likewise.
 527
 528 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 529
 530         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 531
 532 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 533
 534         * riscv-dis.c: Comments tidy and improvement.
 535         * riscv-opc.c: Likewise.
 536
 537 2021-01-13  Alan Modra  <amodra@gmail.com>
 538
 539         * Makefile.in: Regenerate.
 540
 541 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 542
 543         PR binutils/26792
 544         * configure.ac: Use GNU_MAKE_JOBSERVER.
 545         * aclocal.m4: Regenerated.
 546         * configure: Likewise.
 547
 548 2021-01-12  Nick Clifton  <nickc@redhat.com>
 549
 550         * po/sr.po: Updated Serbian translation.
 551
 552 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 553
 554         PR ld/27173
 555         * configure: Regenerated.
 556
 557 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 558
 559         * aarch64-asm-2.c: Regenerate.
 560         * aarch64-dis-2.c: Likewise.
 561         * aarch64-opc-2.c: Likewise.
 562         * aarch64-opc.c (aarch64_print_operand):
 563         Delete handling of AARCH64_OPND_CSRE_CSR.
 564         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 565         (CSRE): Likewise.
 566         (_CSRE_INSN): Likewise.
 567         (aarch64_opcode_table): Delete csr.
 568
 569 2021-01-11  Nick Clifton  <nickc@redhat.com>
 570
 571         * po/de.po: Updated German translation.
 572         * po/fr.po: Updated French translation.
 573         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 574         * po/sv.po: Updated Swedish translation.
 575         * po/uk.po: Updated Ukranian translation.
 576
 577 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 578
 579         * configure: Regenerated.
 580
 581 2021-01-09  Nick Clifton  <nickc@redhat.com>
 582
 583         * configure: Regenerate.
 584         * po/opcodes.pot: Regenerate.
 585
 586 2021-01-09  Nick Clifton  <nickc@redhat.com>
 587
 588         * 2.36 release branch crated.
 589
 590 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 591
 592         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 593         (DW, (XRC_MASK): Define.
 594         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 595
 596 2021-01-09  Alan Modra  <amodra@gmail.com>
 597
 598         * configure: Regenerate.
 599
 600 2021-01-08  Nick Clifton  <nickc@redhat.com>
 601
 602         * po/sv.po: Updated Swedish translation.
 603
 604 2021-01-08  Nick Clifton  <nickc@redhat.com>
 605
 606         PR 27129
 607         * aarch64-dis.c (determine_disassembling_preference): Move call to
 608         aarch64_match_operands_constraint outside of the assertion.
 609         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 610         Replace with a return of FALSE.
 611
 612         PR 27139
 613         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 614         core system register.
 615
 616 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 617
 618         * configure: Regenerate.
 619
 620 2021-01-07  Nick Clifton  <nickc@redhat.com>
 621
 622         * po/fr.po: Updated French translation.
 623
 624 2021-01-07  Fredrik Noring  <noring@nocrew.org>
 625
 626         * m68k-opc.c (chkl): Change minimum architecture requirement to
 627         m68020.
 628
 629 2021-01-07  Philipp Tomsich  <prt@gnu.org>
 630
 631         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
 632
 633 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
 634             Jim Wilson  <jimw@sifive.com>
 635             Andrew Waterman  <andrew@sifive.com>
 636             Maxim Blinov  <maxim.blinov@embecosm.com>
 637             Kito Cheng  <kito.cheng@sifive.com>
 638             Nelson Chu  <nelson.chu@sifive.com>
 639
 640         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
 641         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
 642
 643 2021-01-01  Alan Modra  <amodra@gmail.com>
 644
 645         Update year range in copyright notice of all files.
 646
 647 For older changes see ChangeLog-2020
 648 \f
 649 Copyright (C) 2021 Free Software Foundation, Inc.
 650
 651 Copying and distribution of this file, with or without modification,
 652 are permitted in any medium without royalty provided the copyright
 653 notice and this notice are preserved.
 654
 655 Local Variables:
 656 mode: change-log
 657 left-margin: 8
 658 fill-column: 74
 659 version-control: never
 660 End: