opcodes/ChangeLog

   1 2013-10-10  Roland McGrath  <mcgrathr@google.com>
   2
   3         * i386-dis.c (oappend_maybe_intel): New function.
   4         (OP_ST, OP_STi, append_seg, OP_I, OP_I64, OP_sI, OP_ESreg): Use it.
   5         (OP_C, OP_T, CMP_Fixup, OP_EX_VexImmW): Likewise.
   6         (VCMP_Fixup, VPCMP_Fixup, PCLMUL_Fixup): Likewise.
   7
   8         * cr16-opc.c (REG): Cast NAME to 'reg' enum type to suppress
   9         possible compiler warnings when the union's initializer is
  10         actually meant for the 'preg' enum typed member.
  11         * crx-opc.c (REG): Likewise.
  12
  13         * v850-dis.c (v850_cacheop_codes, v850_prefop_codes):
  14         Remove duplicate const qualifier.
  15
  16 2013-10-08  Jan Beulich <jbeulich@suse.com>
  17
  18         * i386-opc.tbl (invlpg): Use Anysize instead of Unspecified.
  19         (clflush): Use Anysize instead of Byte|Unspecified.
  20         (prefetch*): Likewise.
  21         * i386-tbl.h: Re-generate.
  22
  23 2013-10-07  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
  24
  25         * micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0.
  26
  27 2013-09-30  H.J. Lu  <hongjiu.lu@intel.com>
  28
  29         * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.
  30         * i386-init.h: Regenerated.
  31
  32 2013-09-30  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
  33
  34         * i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS.
  35         * i386-init.h: Regenerated.
  36
  37 2013-09-20  Alan Modra  <amodra@gmail.com>
  38
  39         * configure: Regenerate.
  40
  41 2013-09-17  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
  42
  43         * s390-opc.txt (clih): Make the immediate unsigned.
  44
  45 2013-09-04  Roland McGrath  <mcgrathr@google.com>
  46
  47         PR gas/15914
  48         * arm-dis.c (arm_opcodes): Add udf.
  49         (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
  50         (thumb32_opcodes): Add udf.w.
  51         (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
  52
  53 2013-09-02  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  54
  55         * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
  56         For the load fp integer instructions only the suppression flag was
  57         new with z196 version.
  58
  59 2013-08-28  Nick Clifton  <nickc@redhat.com>
  60
  61         * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
  62         immediate is not suitable for the 32-bit ABI.
  63
  64 2013-08-23  Maciej W. Rozycki  <macro@codesourcery.com>
  65
  66         * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
  67         replacing NODS.
  68
  69 2013-08-23  Yuri Chornoivan  <yurchor@ukr.net>
  70
  71         PR binutils/15834
  72         * aarch64-asm.c: Fix typos.
  73         * aarch64-dis.c: Likewise.
  74         * msp430-dis.c: Likewise.
  75
  76 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
  77
  78         * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
  79         macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
  80         Use +H rather than +C for the real "dext".
  81         * mips-opc.c (mips_builtin_opcodes): Likewise.
  82
  83 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
  84
  85         * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
  86         * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
  87         and OPTIONAL_MAPPED_REG.
  88         * mips-opc.c (decode_mips_operand): Likewise.
  89         * mips16-opc.c (decode_mips16_operand): Likewise.
  90         * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
  91
  92 2013-08-19  H.J. Lu  <hongjiu.lu@intel.com>
  93
  94         * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
  95         (PREFIX_EVEX_0F3A3F): Likewise.
  96         * i386-dis-evex.h (evex_table): Updated.
  97
  98 2013-08-06  Jürgen Urban  <JuergenUrban@gmx.de>
  99
 100         * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
 101         VCLIPW.
 102
 103 2013-08-05  Eric Botcazou  <ebotcazou@adacore.com>
 104             Konrad Eisele  <konrad@gaisler.com>
 105
 106         * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
 107         bfd_mach_sparc.
 108         * sparc-opc.c (MASK_LEON): Define.
 109         (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
 110         (letandleon): New macro.
 111         (v9andleon): Likewise.
 112         (sparc_opc): Add leon.
 113         (umac): Enable for letandleon.
 114         (smac): Likewise.
 115         (casa): Enable for v9andleon.
 116         (cas): Likewise.
 117         (casl): Likewise.
 118
 119 2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
 120             Richard Sandiford  <rdsandiford@googlemail.com>
 121
 122         * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
 123         OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
 124         (print_vu0_channel): New function.
 125         (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
 126         (print_insn_args): Handle '#'.
 127         (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
 128         * mips-opc.c (mips_vu0_channel_mask): New constant.
 129         (decode_mips_operand): Handle new VU0 operand types.
 130         (VU0, VU0CH): New macros.
 131         (mips_builtin_opcodes): Add VU0 opcodes.  Use "+7" rather than "E"
 132         for LQC2 and SQC2.  Use "+9" rather than "G" for EE CFC2 and CTC2.
 133         Use "+6" rather than "G" for QMFC2 and QMTC2.
 134
 135 2013-08-03  Richard Sandiford  <rdsandiford@googlemail.com>
 136
 137         * mips-formats.h (PCREL): Reorder parameters and update the definition
 138         to match new mips_pcrel_operand layout.
 139         (JUMP, JALX, BRANCH): Update accordingly.
 140         * mips16-opc.c (decode_mips16_operand): Likewise.
 141
 142 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 143
 144         * micromips-opc.c (WR_s): Delete.
 145
 146 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 147
 148         * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
 149         New macros.
 150         (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
 151         (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
 152         (mips_builtin_opcodes): Use the new position-based read-write flags
 153         instead of field-based ones.  Use UDI for "udi..." instructions.
 154         * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
 155         New macros.
 156         (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
 157         (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
 158         (WR_SP, RD_16): New macros.
 159         (RD_SP): Redefine as an INSN2_* flag.
 160         (MOD_SP): Redefine in terms of RD_SP and WR_SP.
 161         (mips16_opcodes): Use the new position-based read-write flags
 162         instead of field-based ones.  Use RD_16 for "nop".  Move RD_SP to
 163         pinfo2 field.
 164         * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
 165         New macros.
 166         (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
 167         (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
 168         (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
 169         (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
 170         (micromips_opcodes): Use the new position-based read-write flags
 171         instead of field-based ones.
 172         * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
 173         (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
 174         of field-based flags.
 175
 176 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 177
 178         * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
 179         (WR_SP): Replace with...
 180         (MOD_SP): ...this.
 181         (mips16_opcodes): Update accordingly.
 182         * mips-dis.c (print_insn_mips16): Likewise.
 183
 184 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 185
 186         * mips16-opc.c (mips16_opcodes): Reformat.
 187
 188 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 189
 190         * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
 191         for operands that are hard-coded to $0.
 192         * micromips-opc.c (micromips_opcodes): Likewise.
 193
 194 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 195
 196         * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
 197         for the single-operand forms of JALR and JALR.HB.
 198         * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
 199         and JALRS.HB.
 200
 201 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 202
 203         * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
 204         instructions.  Fix them to use WR_MACC instead of WR_CC and
 205         add missing RD_MACCs.
 206
 207 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 208
 209         * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
 210
 211 2013-07-29  Peter Bergner <bergner@vnet.ibm.com>
 212
 213         * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
 214
 215 2013-07-26  Sergey Guriev  <sergey.s.guriev@intel.com>
 216             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 217             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 218             Sergey Lega  <sergey.s.lega@intel.com>
 219             Anna Tikhonova  <anna.tikhonova@intel.com>
 220             Ilya Tocar  <ilya.tocar@intel.com>
 221             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 222             Ilya Verbin  <ilya.verbin@intel.com>
 223             Kirill Yukhin  <kirill.yukhin@intel.com>
 224             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 225
 226         * i386-dis-evex.h: New.
 227         * i386-dis.c (OP_Rounding): New.
 228         (VPCMP_Fixup): New.
 229         (OP_Mask): New.
 230         (Rdq): New.
 231         (XMxmmq): New.
 232         (EXdScalarS): New.
 233         (EXymm): New.
 234         (EXEvexHalfBcstXmmq): New.
 235         (EXxmm_mdq): New.
 236         (EXEvexXGscat): New.
 237         (EXEvexXNoBcst): New.
 238         (VPCMP): New.
 239         (EXxEVexR): New.
 240         (EXxEVexS): New.
 241         (XMask): New.
 242         (MaskG): New.
 243         (MaskE): New.
 244         (MaskR): New.
 245         (MaskVex): New.
 246         (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
 247         evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
 248         evex_rounding_mode, evex_sae_mode, mask_mode.
 249         (USE_EVEX_TABLE): New.
 250         (EVEX_TABLE): New.
 251         (EVEX enum): New.
 252         (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
 253         REG_EVEX_0F38C7.
 254         (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
 255         MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
 256         MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
 257         MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 258         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,  MOD_EVEX_0F38C7_REG_5,
 259         MOD_EVEX_0F38C7_REG_6.
 260         (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 261         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
 262         PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 263         PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
 264         PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
 265         PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
 266         PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
 267         PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
 268         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
 269         PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
 270         PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
 271         PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
 272         PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
 273         PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
 274         PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
 275         PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
 276         PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
 277         PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
 278         PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
 279         PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
 280         PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
 281         PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
 282         PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
 283         PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
 284         PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
 285         PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
 286         PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
 287         PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
 288         PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
 289         PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
 290         PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
 291         PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
 292         PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
 293         PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
 294         PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
 295         PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
 296         PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
 297         PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
 298         PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
 299         PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
 300         PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
 301         PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
 302         PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
 303         PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
 304         PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
 305         PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
 306         PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
 307         PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
 308         PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
 309         PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
 310         PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
 311         PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
 312         PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
 313         PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
 314         PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
 315         PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
 316         PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
 317         PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
 318         PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
 319         PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
 320         PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
 321         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
 322         PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
 323         PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
 324         PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
 325         PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
 326         PREFIX_EVEX_0F3A00,  PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
 327         PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
 328         PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
 329         PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
 330         PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
 331         PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
 332         PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
 333         PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
 334         PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
 335         PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
 336         PREFIX_EVEX_0F3A55.
 337         (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
 338         VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
 339         VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
 340         VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
 341         VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
 342         VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
 343         VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
 344         VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
 345         VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
 346         VEX_W_0F3A32_P_2_LEN_0.
 347         (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
 348         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
 349         EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
 350         EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
 351         EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
 352         EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 353         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
 354         EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
 355         EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 356         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
 357         EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 358         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
 359         EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
 360         EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
 361         EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
 362         EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
 363         EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
 364         EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
 365         EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
 366         EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
 367         EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
 368         EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
 369         EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
 370         EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
 371         EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
 372         EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
 373         EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
 374         EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
 375         EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
 376         EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
 377         EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
 378         EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
 379         EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
 380         EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
 381         EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
 382         EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
 383         EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
 384         EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
 385         EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
 386         EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
 387         EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
 388         EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
 389         EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
 390         EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
 391         EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
 392         EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
 393         EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
 394         EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
 395         EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
 396         EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
 397         EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
 398         EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
 399         EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
 400         EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
 401         (struct vex): Add fields evex, r, v, mask_register_specifier,
 402         zeroing, ll, b.
 403         (intel_names_xmm): Add upper 16 registers.
 404         (att_names_xmm): Ditto.
 405         (intel_names_ymm): Ditto.
 406         (att_names_ymm): Ditto.
 407         (names_zmm): New.
 408         (intel_names_zmm): Ditto.
 409         (att_names_zmm): Ditto.
 410         (names_mask): Ditto.
 411         (intel_names_mask): Ditto.
 412         (att_names_mask): Ditto.
 413         (names_rounding): Ditto.
 414         (names_broadcast): Ditto.
 415         (x86_64_table): Add escape to evex-table.
 416         (reg_table): Include reg_table evex-entries from
 417         i386-dis-evex.h.  Fix prefetchwt1 instruction.
 418         (prefix_table): Add entries for new instructions.
 419         (vex_table): Ditto.
 420         (vex_len_table): Ditto.
 421         (vex_w_table): Ditto.
 422         (mod_table): Ditto.
 423         (get_valid_dis386): Properly handle new instructions.
 424         (print_insn): Handle zmm and mask registers, print mask operand.
 425         (intel_operand_size): Support EVEX, new modes and sizes.
 426         (OP_E_register): Handle new modes.
 427         (OP_E_memory): Ditto.
 428         (OP_G): Ditto.
 429         (OP_XMM): Ditto.
 430         (OP_EX): Ditto.
 431         (OP_VEX): Ditto.
 432         * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
 433         CPU_ANY_AVX_FLAGS.  Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
 434         CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 435         (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
 436         CpuAVX512PF and CpuVREX.
 437         (operand_type_init): Add OPERAND_TYPE_REGZMM,
 438         OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
 439         (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
 440         StaticRounding, SAE, Disp8MemShift, NoDefMask.
 441         (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
 442         * i386-init.h: Regenerate.
 443         * i386-opc.h (CpuAVX512F): New.
 444         (CpuAVX512CD): New.
 445         (CpuAVX512ER): New.
 446         (CpuAVX512PF): New.
 447         (CpuVREX): New.
 448         (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
 449         cpuavx512pf and cpuvrex fields.
 450         (VecSIB): Add VecSIB512.
 451         (EVex): New.
 452         (Masking): New.
 453         (VecESize): New.
 454         (Broadcast): New.
 455         (StaticRounding): New.
 456         (SAE): New.
 457         (Disp8MemShift): New.
 458         (NoDefMask): New.
 459         (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
 460         staticrounding, sae, disp8memshift and nodefmask.
 461         (RegZMM): New.
 462         (Zmmword): Ditto.
 463         (Vec_Disp8): Ditto.
 464         (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
 465         fields.
 466         (RegVRex): New.
 467         * i386-opc.tbl: Add AVX512 instructions.
 468         * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
 469         registers, mask registers.
 470         * i386-tbl.h: Regenerate.
 471
 472 2013-07-25  Aaro Koskinen  <aaro.koskinen@iki.fi>
 473
 474         PR gas/15220
 475         * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
 476         Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
 477
 478 2013-07-25  Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 479
 480         * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
 481         PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
 482         PREFIX_0F3ACC.
 483         (prefix_table): Updated.
 484         (three_byte_table): Likewise.
 485         * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
 486         (cpu_flags): Add CpuSHA.
 487         (i386_cpu_flags): Add cpusha.
 488         * i386-init.h: Regenerate.
 489         * i386-opc.h (CpuSHA): New.
 490         (CpuUnused): Restored.
 491         (i386_cpu_flags): Add cpusha.
 492         * i386-opc.tbl: Add SHA instructions.
 493         * i386-tbl.h: Regenerate.
 494
 495 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
 496             Kirill Yukhin  <kirill.yukhin@intel.com>
 497             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 498
 499         * i386-dis.c (BND_Fixup): New.
 500         (Ebnd): New.
 501         (Ev_bnd): New.
 502         (Gbnd): New.
 503         (BND): New.
 504         (v_bnd_mode): New.
 505         (bnd_mode): New.
 506         (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
 507         MOD_0F1B_PREFIX_1.
 508         (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
 509         (dis tables): Replace XX with BND for near branch and call
 510         instructions.
 511         (prefix_table): Add new entries.
 512         (mod_table): Likewise.
 513         (names_bnd): New.
 514         (intel_names_bnd): New.
 515         (att_names_bnd): New.
 516         (BND_PREFIX): New.
 517         (prefix_name): Handle BND_PREFIX.
 518         (print_insn): Initialize names_bnd.
 519         (intel_operand_size): Handle new modes.
 520         (OP_E_register): Likewise.
 521         (OP_E_memory): Likewise.
 522         (OP_G): Likewise.
 523         * i386-gen.c (cpu_flag_init): Add CpuMPX.
 524         (cpu_flags): Add CpuMPX.
 525         (operand_type_init): Add RegBND.
 526         (opcode_modifiers): Add BNDPrefixOk.
 527         (operand_types): Add RegBND.
 528         * i386-init.h: Regenerate.
 529         * i386-opc.h (CpuMPX): New.
 530         (CpuUnused): Comment out.
 531         (i386_cpu_flags): Add cpumpx.
 532         (BNDPrefixOk): New.
 533         (i386_opcode_modifier): Add bndprefixok.
 534         (RegBND): New.
 535         (i386_operand_type): Add regbnd.
 536         * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
 537         Add MPX instructions and bnd prefix.
 538         * i386-reg.tbl: Add bnd0-bnd3 registers.
 539         * i386-tbl.h: Regenerate.
 540
 541 2013-07-17  Richard Sandiford  <rdsandiford@googlemail.com>
 542
 543         * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
 544         ATTRIBUTE_UNUSED.
 545
 546 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 547
 548         * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
 549         special rules.
 550         * Makefile.in: Regenerate.
 551         * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
 552         all fields.  Reformat.
 553
 554 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 555
 556         * mips16-opc.c: Include mips-formats.h.
 557         (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
 558         static arrays.
 559         (decode_mips16_operand): New function.
 560         * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
 561         (print_insn_arg): Handle OP_ENTRY_EXIT list.
 562         Abort for OP_SAVE_RESTORE_LIST.
 563         (print_mips16_insn_arg): Change interface.  Use mips_operand
 564         structures.  Delete GET_OP_S.  Move GET_OP definition to...
 565         (print_insn_mips16): ...here.  Call init_print_arg_state.
 566         Update the call to print_mips16_insn_arg.
 567
 568 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 569
 570         * mips-formats.h: New file.
 571         * mips-opc.c: Include mips-formats.h.
 572         (reg_0_map): New static array.
 573         (decode_mips_operand): New function.
 574         * micromips-opc.c: Remove <stdio.h> include.  Include mips-formats.h.
 575         (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
 576         (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
 577         (int_c_map): New static arrays.
 578         (decode_micromips_operand): New function.
 579         * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
 580         (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
 581         (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
 582         (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
 583         (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
 584         (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
 585         (micromips_imm_b_map, micromips_imm_c_map): Delete.
 586         (print_reg): New function.
 587         (mips_print_arg_state): New structure.
 588         (init_print_arg_state, print_insn_arg): New functions.
 589         (print_insn_args): Change interface and use mips_operand structures.
 590         Delete GET_OP_S.  Move GET_OP definition to...
 591         (print_insn_mips): ...here.  Update the call to print_insn_args.
 592         (print_insn_micromips): Use print_insn_args.
 593
 594 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 595
 596         * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
 597         in macros.
 598
 599 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 600
 601         * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
 602         ADDA.S, MULA.S and SUBA.S.
 603
 604 2013-07-08  H.J. Lu  <hongjiu.lu@intel.com>
 605
 606         PR gas/13572
 607         * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
 608         * i386-tbl.h: Regenerated.
 609
 610 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 611
 612         * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros.  Move LD
 613         and SD A(B) macros up.
 614         * micromips-opc.c (micromips_opcodes): Likewise.
 615
 616 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 617
 618         * mips16-opc.c: Add entries for argumentless "entry" and "exit"
 619         instructions.
 620
 621 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 622
 623         * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
 624         MDMX-like instructions.
 625         * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
 626         printing "Q" operands for INSN_5400 instructions.
 627
 628 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 629
 630         * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
 631         "+S" for "cins".
 632         * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
 633         Combine cases.
 634
 635 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 636
 637         * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
 638         "jalx".
 639         * mips16-opc.c (mips16_opcodes): Likewise.
 640         * micromips-opc.c (micromips_opcodes): Likewise.
 641         * mips-dis.c (print_insn_args, print_mips16_insn_arg)
 642         (print_insn_mips16): Handle "+i".
 643         (print_insn_micromips): Likewise.  Conditionally preserve the
 644         ISA bit for "a" but not for "+i".
 645
 646 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 647
 648         * micromips-opc.c (WR_mhi): Rename to..
 649         (WR_mh): ...this.
 650         (micromips_opcodes): Update "movep" entry accordingly.  Replace
 651         "mh,mi" with "mh".
 652         * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
 653         (micromips_to_32_reg_h_map1): ...this.
 654         (micromips_to_32_reg_i_map): Rename to...
 655         (micromips_to_32_reg_h_map2): ...this.
 656         (print_micromips_insn): Remove "mi" case.  Print both registers
 657         in the pair for "mh".
 658
 659 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 660
 661         * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
 662         * micromips-opc.c (micromips_opcodes): Likewise.
 663         * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
 664         and "+T" handling.  Check for a "0" suffix when deciding whether to
 665         use coprocessor 0 names.  In that case, also check for ",H" selectors.
 666
 667 2013-07-05  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 668
 669         * s390-opc.c (J12_12, J24_24): New macros.
 670         (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
 671         (MASK_MII_UPI): Rename to MASK_MII_UPP.
 672         * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
 673
 674 2013-07-04  Alan Modra  <amodra@gmail.com>
 675
 676         * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
 677
 678 2013-06-26  Nick Clifton  <nickc@redhat.com>
 679
 680         * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
 681         field when checking for type 2 nop.
 682         * rx-decode.c: Regenerate.
 683
 684 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
 685
 686         * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
 687         and "movep" macros.
 688
 689 2013-06-24  Maciej W. Rozycki  <macro@codesourcery.com>
 690
 691         * mips-dis.c (is_mips16_plt_tail): New function.
 692         (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
 693         word.
 694         (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
 695
 696 2013-06-21  DJ Delorie  <dj@redhat.com>
 697
 698         * msp430-decode.opc: New.
 699         * msp430-decode.c: New/generated.
 700         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
 701         (MAINTAINER_CLEANFILES): Likewise.
 702         Add rule to build msp430-decode.c frommsp430decode.opc
 703         using the opc2c program.
 704         * Makefile.in: Regenerate.
 705         * configure.in: Add msp430-decode.lo to msp430 architecture files.
 706         * configure: Regenerate.
 707
 708 2013-06-20  Yufeng Zhang  <yufeng.zhang@arm.com>
 709
 710         * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
 711         (SYMTAB_AVAILABLE): Removed.
 712         (#include "elf/aarch64.h): Ditto.
 713
 714 2013-06-17  Catherine Moore  <clm@codesourcery.com>
 715             Maciej W. Rozycki  <macro@codesourcery.com>
 716             Chao-Ying Fu  <fu@mips.com>
 717
 718         * micromips-opc.c (EVA): Define.
 719         (TLBINV): Define.
 720         (micromips_opcodes): Add EVA opcodes.
 721         * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
 722         (print_insn_args): Handle EVA offsets.
 723         (print_insn_micromips): Likewise.
 724         * mips-opc.c (EVA): Define.
 725         (TLBINV): Define.
 726         (mips_builtin_opcodes): Add EVA opcodes.
 727
 728 2013-06-17  Alan Modra  <amodra@gmail.com>
 729
 730         * Makefile.am (mips-opc.lo): Add rules to create automatic
 731         dependency files.  Pass archdefs.
 732         (micromips-opc.lo, mips16-opc.lo): Likewise.
 733         * Makefile.in: Regenerate.
 734
 735 2013-06-14  DJ Delorie  <dj@redhat.com>
 736
 737         * rx-decode.opc (rx_decode_opcode): Bit operations on
 738         registers are 32-bit operations, not 8-bit operations.
 739         * rx-decode.c: Regenerate.
 740
 741 2013-06-13  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 742
 743         * micromips-opc.c (IVIRT): New define.
 744         (IVIRT64): New define.
 745         (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 746         tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
 747
 748         * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
 749         dmtgc0 to print cp0 names.
 750
 751 2013-06-09  Sandra Loosemore  <sandra@codesourcery.com>
 752
 753         * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
 754         argument.
 755
 756 2013-06-08  Catherine Moore  <clm@codesourcery.com>
 757             Richard Sandiford  <rdsandiford@googlemail.com>
 758
 759         * micromips-opc.c (D32, D33, MC): Update definitions.
 760         (micromips_opcodes):  Initialize ase field.
 761         * mips-dis.c (mips_arch_choice): Add ase field.
 762         (mips_arch_choices): Initialize ase field.
 763         (set_default_mips_dis_options): Declare and setup mips_ase.
 764         * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
 765         MT32, MC): Update definitions.
 766         (mips_builtin_opcodes): Initialize ase field.
 767
 768 2013-05-24  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 769
 770         * s390-opc.txt (flogr): Require a register pair destination.
 771
 772 2013-05-23  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 773
 774         * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
 775         instruction format.
 776
 777 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 778
 779         * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
 780
 781 2013-05-20  Peter Bergner <bergner@vnet.ibm.com>
 782
 783         * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
 784         * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
 785         XLS_MASK, PPCVSX2): New defines.
 786         (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
 787         fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
 788         mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
 789         mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
 790         mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
 791         vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
 792         vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
 793         vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
 794         vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
 795         vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
 796         vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
 797         vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
 798         vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
 799         vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
 800         xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
 801         xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
 802         xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
 803         xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
 804         <lxvx, stxvx>: New extended mnemonics.
 805
 806 2013-05-17  Alan Modra  <amodra@gmail.com>
 807
 808         * ia64-raw.tbl: Replace non-ASCII char.
 809         * ia64-waw.tbl: Likewise.
 810         * ia64-asmtab.c: Regenerate.
 811
 812 2013-05-15  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 813
 814         * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
 815         * i386-init.h: Regenerated.
 816
 817 2013-05-13  Yufeng Zhang  <yufeng.zhang@arm.com>
 818
 819         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
 820         * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
 821         check from [0, 255] to [-128, 255].
 822
 823 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 824
 825         * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
 826         Add INSN_VIRT and INSN_VIRT64 to mips64r2.
 827         (parse_mips_dis_option): Handle the virt option.
 828         (print_insn_args): Handle "+J".
 829         (print_mips_disassembler_options): Print out message about virt64.
 830         * mips-opc.c (IVIRT): New define.
 831         (IVIRT64): New define.
 832         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 833         tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
 834         Move rfe to the bottom as it conflicts with tlbgp.
 835
 836 2013-05-09  Alan Modra  <amodra@gmail.com>
 837
 838         * ppc-opc.c (extract_vlesi): Properly sign extend.
 839         (extract_vlensi): Likewise.  Comment reason for setting invalid.
 840
 841 2013-05-02  Nick Clifton  <nickc@redhat.com>
 842
 843         * msp430-dis.c: Add support for MSP430X instructions.
 844
 845 2013-04-24  Sandra Loosemore  <sandra@codesourcery.com>
 846
 847         * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
 848         to "eccinj".
 849
 850 2013-04-17  Wei-chen Wang  <cole945@gmail.com>
 851
 852         PR binutils/15369
 853         * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
 854         of CGEN_CPU_ENDIAN.
 855         (hash_insns_list): Likewise.
 856
 857 2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>
 858
 859         * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
 860         warning workaround.
 861
 862 2013-04-08  Jan Beulich <jbeulich@suse.com>
 863
 864         * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
 865         * i386-tbl.h: Re-generate.
 866
 867 2013-04-06  David S. Miller  <davem@davemloft.net>
 868
 869         * sparc-dis.c (compare_opcodes): When encountering multiple aliases
 870         of an opcode, prefer the one with F_PREFERRED set.
 871         * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
 872         lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
 873         ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
 874         mark existing mnenomics as aliases.  Add "cc" suffix to edge
 875         instructions generating condition codes, mark existing mnenomics
 876         as aliases.  Add "fp" prefix to VIS compare instructions, mark
 877         existing mnenomics as aliases.
 878
 879 2013-04-03  Nick Clifton  <nickc@redhat.com>
 880
 881         * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
 882         destination address by subtracting the operand from the current
 883         address.
 884         * v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
 885         a positive value in the insn.
 886         (extract_u16_loop): Do not negate the returned value.
 887         (D16_LOOP): Add V850_INVERSE_PCREL flag.
 888
 889         (ceilf.sw): Remove duplicate entry.
 890         (cvtf.hs): New entry.
 891         (cvtf.sh): Likewise.
 892         (fmaf.s): Likewise.
 893         (fmsf.s): Likewise.
 894         (fnmaf.s): Likewise.
 895         (fnmsf.s): Likewise.
 896         (maddf.s): Restrict to E3V5 architectures.
 897         (msubf.s): Likewise.
 898         (nmaddf.s): Likewise.
 899         (nmsubf.s): Likewise.
 900
 901 2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>
 902
 903         * i386-dis.c (get_sib): Add the sizeflag argument.  Properly
 904         check address mode.
 905         (print_insn): Pass sizeflag to get_sib.
 906
 907 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 908
 909         PR binutils/15068
 910         * tic6x-dis.c: Add support for displaying 16-bit insns.
 911
 912 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 913
 914         PR gas/15095
 915         * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
 916         individual msb and lsb halves in src1 & src2 fields.  Discard the
 917         src1 (lsb) value and only use src2 (msb), discarding bit 0, to
 918         follow what Ti SDK does in that case as any value in the src1
 919         field yields the same output with SDK disassembler.
 920
 921 2013-03-12  Michael Eager <eager@eagercon.com>
 922
 923         * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
 924
 925 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 926
 927         * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
 928
 929 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 930
 931         * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
 932
 933 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 934
 935         * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
 936
 937 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 938
 939         * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
 940         (thumb32_opcodes): Likewise.
 941         (print_insn_thumb32): Handle 'S' control char.
 942
 943 2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
 944
 945         * lm32-desc.c: Regenerate.
 946
 947 2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 948
 949         * i386-reg.tbl (riz): Add RegRex64.
 950         * i386-tbl.h: Regenerated.
 951
 952 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 953
 954         * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
 955         (aarch64_feature_crc): New static.
 956         (CRC): New macro.
 957         (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
 958         crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
 959         * aarch64-asm-2.c: Re-generate.
 960         * aarch64-dis-2.c: Ditto.
 961         * aarch64-opc-2.c: Ditto.
 962
 963 2013-02-27  Alan Modra  <amodra@gmail.com>
 964
 965         * rl78-decode.opc (rl78_decode_opcode): Fix typo.
 966         * rl78-decode.c: Regenerate.
 967
 968 2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
 969
 970         * rl78-decode.opc: Fix encoding of DIVWU insn.
 971         * rl78-decode.c: Regenerate.
 972
 973 2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 974
 975         PR gas/15159
 976         * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
 977
 978         * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
 979         (cpu_flags): Add CpuSMAP.
 980
 981         * i386-opc.h (CpuSMAP): New.
 982         (i386_cpu_flags): Add cpusmap.
 983
 984         * i386-opc.tbl: Add clac and stac.
 985
 986         * i386-init.h: Regenerated.
 987         * i386-tbl.h: Likewise.
 988
 989 2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
 990
 991         * metag-dis.c: Initialize outf->bytes_per_chunk to 4
 992         which also makes the disassembler output be in little
 993         endian like it should be.
 994
 995 2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
 996
 997         * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
 998         fields to NULL.
 999         (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
1000
1001 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
1002
1003         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
1004         section disassembled.
1005
1006 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1007
1008         * arm-dis.c: Update strht pattern.
1009
1010 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
1011
1012         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
1013         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
1014         trunc.w.s macro for EE.
1015
1016 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
1017             Andrew Jenner <andrew@codesourcery.com>
1018
1019         Based on patches from Altera Corporation.
1020
1021         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
1022         nios2-opc.c.
1023         * Makefile.in: Regenerated.
1024         * configure.in: Add case for bfd_nios2_arch.
1025         * configure: Regenerated.
1026         * disassemble.c (ARCH_nios2): Define.
1027         (disassembler): Add case for bfd_arch_nios2.
1028         * nios2-dis.c: New file.
1029         * nios2-opc.c: New file.
1030
1031 2013-02-04  Alan Modra  <amodra@gmail.com>
1032
1033         * po/POTFILES.in: Regenerate.
1034         * rl78-decode.c: Regenerate.
1035         * rx-decode.c: Regenerate.
1036
1037 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
1038
1039         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
1040         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
1041         * aarch64-asm.c (convert_xtl_to_shll): New function.
1042         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1043         calling convert_xtl_to_shll.
1044         * aarch64-dis.c (convert_shll_to_xtl): New function.
1045         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1046         calling convert_shll_to_xtl.
1047         * aarch64-gen.c: Update copyright year.
1048         * aarch64-asm-2.c: Re-generate.
1049         * aarch64-dis-2.c: Re-generate.
1050         * aarch64-opc-2.c: Re-generate.
1051
1052 2013-01-24  Nick Clifton  <nickc@redhat.com>
1053
1054         * v850-dis.c: Add support for e3v5 architecture.
1055         * v850-opc.c: Likewise.
1056
1057 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
1058
1059         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
1060         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
1061         * aarch64-opc.c (operand_general_constraint_met_p): For
1062         AARCH64_MOD_LSL, move the range check on the shift amount before the
1063         alignment check; change to call set_sft_amount_out_of_range_error
1064         instead of set_imm_out_of_range_error.
1065         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
1066         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
1067         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
1068         SIMD_IMM_SFT.
1069
1070 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
1071
1072         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
1073
1074         * i386-init.h: Regenerated.
1075         * i386-tbl.h: Likewise.
1076
1077 2013-01-15  Nick Clifton  <nickc@redhat.com>
1078
1079         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
1080         values.
1081         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1082
1083 2013-01-14  Will Newton <will.newton@imgtec.com>
1084
1085         * metag-dis.c (REG_WIDTH): Increase to 64.
1086
1087 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
1088
1089         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1090         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1091         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1092         (SH6): Update.
1093         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1094         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1095         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1096         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1097
1098 2013-01-10  Will Newton <will.newton@imgtec.com>
1099
1100         * Makefile.am: Add Meta.
1101         * configure.in: Add Meta.
1102         * disassemble.c: Add Meta support.
1103         * metag-dis.c: New file.
1104         * Makefile.in: Regenerate.
1105         * configure: Regenerate.
1106
1107 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1108
1109         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1110         (match_opcode): Rename to cr16_match_opcode.
1111
1112 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
1113
1114         * mips-dis.c: Add names for CP0 registers of r5900.
1115         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1116         instructions sq and lq.
1117         Add support for MIPS r5900 CPU.
1118         Add support for 128 bit MMI (Multimedia Instructions).
1119         Add support for EE instructions (Emotion Engine).
1120         Disable unsupported floating point instructions (64 bit and
1121         undefined compare operations).
1122         Enable instructions of MIPS ISA IV which are supported by r5900.
1123         Disable 64 bit co processor instructions.
1124         Disable 64 bit multiplication and division instructions.
1125         Disable instructions for co-processor 2 and 3, because these are
1126         not supported (preparation for later VU0 support (Vector Unit)).
1127         Disable cvt.w.s because this behaves like trunc.w.s and the
1128         correct execution can't be ensured on r5900.
1129         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1130         will confuse less developers and compilers.
1131
1132 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1133
1134         * aarch64-opc.c (aarch64_print_operand): Change to print
1135         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1136         in comment.
1137         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1138         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1139         OP_MOV_IMM_WIDE.
1140
1141 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1142
1143         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1144         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
1145
1146 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
1147
1148         * i386-gen.c (process_copyright): Update copyright year to 2013.
1149
1150 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1151
1152         * cr16-dis.c (match_opcode,make_instruction): Remove static
1153         declaration.
1154         (dwordU,wordU): Moved typedefs to opcode/cr16.h
1155         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
1156
1157 For older changes see ChangeLog-2012
1158 \f
1159 Copyright (C) 2013 Free Software Foundation, Inc.
1160
1161 Copying and distribution of this file, with or without modification,
1162 are permitted in any medium without royalty provided the copyright
1163 notice and this notice are preserved.
1164
1165 Local Variables:
1166 mode: change-log
1167 left-margin: 8
1168 fill-column: 74
1169 version-control: never
1170 End: