opcodes/ChangeLog

   1 2014-11-17  Ilya Tocar  <ilya.tocar@intel.com>
   2
   3         * i386-dis.c (PREFIX enum): Add PREFIX_RM_0_0FAE_REG_7.
   4         (prefix_table): Add pcommit.
   5         * i386-gen.c (cpu_flag_init): Add CPU_PCOMMIT_FLAGS.
   6         (cpu_flags): Add CpuPCOMMIT.
   7         * i386-opc.h (enum): Add CpuPCOMMIT.
   8         (i386_cpu_flags): Add cpupcommit.
   9         * i386-opc.tbl: Add pcommit.
  10         * i386-init.h: Regenerated.
  11         * i386-tbl.h: Likewise.
  12
  13 2014-11-17  Ilya Tocar  <ilya.tocar@intel.com>
  14
  15         * i386-dis.c (PREFIX enum): Add PREFIX_0FAE_REG_6.
  16         (prefix_table): Add clwb.
  17         * i386-gen.c (cpu_flag_init): Add CPU_CLWB_FLAGS.
  18         (cpu_flags): Add CpuCLWB.
  19         * i386-opc.h (enum): Add CpuCLWB.
  20         (i386_cpu_flags): Add cpuclwb.
  21         * i386-opc.tbl: Add clwb.
  22         * i386-init.h: Regenerated.
  23         * i386-tbl.h: Likewise.
  24
  25 2014-11-06  Sandra Loosemore  <sandra@codesourcery.com>
  26
  27         * nios2-dis.c (nios2_find_opcode_hash): Add mach parameter.
  28         (nios2_disassemble): Adjust call to nios2_find_opcode_hash.
  29
  30 2014-11-03  Nick Clifton  <nickc@redhat.com>
  31
  32         * po/fi.po: Updated Finnish translation.
  33
  34 2014-10-31  Andrew Pinski  <apinski@cavium.com>
  35             Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>
  36
  37         * mips-dis.c (mips_arch_choices): Add octeon3.
  38         * mips-opc.c (IOCT): Include INSN_OCTEON3.
  39         (IOCT2): Likewise.
  40         (IOCT3): New define.
  41         (IVIRT): New define.
  42         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
  43         tlbinv, tlbinvf, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp, tlti
  44         IVIRT instructions.
  45         Extend mtm0, mtm1, mtm2, mtp0, mtp1, mtp2 instructions to take another
  46         operand for IOCT3.
  47
  48 2014-10-29  Nick Clifton  <nickc@redhat.com>
  49
  50         * po/de.po: Updated German translation.
  51
  52 2014-10-23  Sandra Loosemore  <sandra@codesourcery.com>
  53
  54         * nios2-opc.c (nios2_builtin_regs): Add regtype field initializers.
  55         (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.  Use new
  56         MATCH_R1_<insn> and MASK_R1_<insn> macros in initializers.  Add
  57         size and format initializers.  Merge 'b' arguments into 'j'.
  58         (NIOS2_NUM_OPCODES): Adjust definition.
  59         (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
  60         (nios2_opcodes): Adjust.
  61         (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
  62         * nios2-dis.c (INSNLEN): Update comment.
  63         (nios2_hash_init, nios2_hash): Delete.
  64         (OPCODE_HASH_SIZE): New.
  65         (nios2_r1_extract_opcode): New.
  66         (nios2_disassembler_state): New.
  67         (nios2_r1_disassembler_state): New.
  68         (nios2_init_opcode_hash): Add state parameter.  Adjust to use it.
  69         (nios2_find_opcode_hash): Use state object.
  70         (bad_opcode): New.
  71         (nios2_print_insn_arg): Add op parameter.  Use it to access
  72         format.  Remove 'b' case.
  73         (nios2_disassemble): Remove special case for nop.  Remove
  74         hard-coded instruction size.
  75
  76 2014-10-21  Jan Beulich  <jbeulich@suse.com>
  77
  78         * ppc-opc.c (powerpc_opcodes): Enable msgclr and msgsnd on Power8.
  79
  80 2014-10-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
  81
  82         * sparc-opc.c (sparc-opcodes): Fix several misplaced hwcap
  83         entries.
  84         Annotate several instructions with the HWCAP2_VIS3B hwcap.
  85
  86 2014-10-15  Tristan Gingold  <gingold@adacore.com>
  87
  88         * configure: Regenerate.
  89
  90 2014-10-09  Jose E. Marchesi  &lt;jose.marchesi@oracle.com&gt;
  91
  92         * sparc-opc.c (sparc-opcodes): Remove instructions `chkpt',
  93         `commit', `random', `wr r,r,%cps', `wr r,i,%cps' and `rd %cps,r'.
  94         Annotate table with HWCAP2 bits.
  95         Add instructions xmontmul, xmontsqr, xmpmul.
  96         (sparc-opcodes): Add the `mwait',  `wr r,r,%mwait', `wr
  97         r,i,%mwait' and `rd %mwait,r' instructions.
  98         Add rd/wr instructions for accessing the %mcdper ancillary state
  99         register.
 100         (sparc-opcodes): Add sparc5/vis4.0 instructions:
 101         subxc, subxccc, fpadd8, fpadds8, fpaddus8, fpaddus16, fpcmple8,
 102         fpcmpgt8, fpcmpule16, fpcmpugt16, fpcmpule32, fpcmpugt32, fpmax8,
 103         fpmax16, fpmax32, fpmaxu8, fpmaxu16, fpmaxu32, fpmin8, fpmin16,
 104         fpmin32, fpminu8, fpminu16, fpminu32, fpsub8, fpsubs8, fpsubus8,
 105         fpsubus16, and faligndatai.
 106         * sparc-dis.c (v9a_asr_reg_names): Add the %mwait (%asr28)
 107         ancillary state register to the table.
 108         (print_insn_sparc): Handle the %mcdper ancillary state register.
 109         (print_insn_sparc): Handle new operand type '}'.
 110
 111 2014-09-22  H.J. Lu  <hongjiu.lu@intel.com>
 112
 113         * i386-dis.c (MOD_0F20): Removed.
 114         (MOD_0F21): Likewise.
 115         (MOD_0F22): Likewise.
 116         (MOD_0F23): Likewise.
 117         (dis386_twobyte): Replace MOD_0F20, MOD_0F21, MOD_0F22 and
 118         MOD_0F23 with "movZ".
 119         (mod_table): Remove MOD_0F20, MOD_0F21, MOD_0F22 and MOD_0F23.
 120         (OP_R): Check mod/rm byte and call OP_E_register.
 121
 122 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 123
 124         * nds32-asm.c (nds32_opcodes, operand_fields, keyword_im5_i,
 125         keyword_im5_m, keyword_accumulator, keyword_aridx, keyword_aridx2,
 126         keyword_aridxi): Add audio ISA extension.
 127         (keyword_gpr, keyword_usr, keyword_sr, keyword_cp, keyword_cpr,
 128         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm, keyword_dpref_st,
 129         keyword_cctl_lv, keyword_standby_st, keyword_msync_st): Adjust scrope
 130         for nds32-dis.c using.
 131         (build_opcode_syntax): Remove dead code.
 132         (parse_re, parse_a30b20, parse_rt21, parse_rte_start, parse_rte_end,
 133         parse_rte69_start, parse_rte69_end, parse_im5_ip, parse_im5_mr,
 134         parse_im6_ip, parse_im6_iq, parse_im6_mr, parse_im6_ms): Add audio ISA
 135         operand parser.
 136         * nds32-asm.h: Declare.
 137         * nds32-dis.c: Use array nds32_opcodes to disassemble instead of
 138         decoding by switch.
 139
 140 2014-09-15  Andrew Bennett  <andrew.bennett@imgtec.com>
 141             Matthew Fortune  <matthew.fortune@imgtec.com>
 142
 143         * mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
 144         mips64r6.
 145         (parse_mips_dis_option): Allow MSA and virtualization support for
 146         mips64r6.
 147         (mips_print_arg_state): Add fields dest_regno and seen_dest.
 148         (mips_seen_register): New function.
 149         (print_insn_arg): Refactored code to use mips_seen_register
 150         function.  Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
 151         OP_NON_ZERO_REG.  Changed OP_REPEAT_DEST_REG case to print out
 152         the register rather than aborting.
 153         (print_insn_args): Add length argument.  Add code to correctly
 154         calculate the instruction address for pc relative instructions.
 155         (validate_insn_args): New static function.
 156         (print_insn_mips): Prevent jalx disassembling for r6.  Use
 157         validate_insn_args.
 158         (print_insn_micromips): Use validate_insn_args.
 159         all the arguments are valid.
 160         * mips-formats.h (PREV_CHECK): New define.
 161         * mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
 162         -t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
 163         (RD_pc): New define.
 164         (FS): New define.
 165         (I37): New define.
 166         (I69): New define.
 167         (mips_builtin_opcodes): Add MIPS R6 instructions.  Exclude recoded
 168         MIPS R6 instructions from MIPS R2 instructions.
 169
 170 2014-09-10  H.J. Lu  <hongjiu.lu@intel.com>
 171
 172         * i386-dis.c (dis386): Replace "P" with "%LP" for iret and sysret.
 173         (putop): Handle "%LP".
 174
 175 2014-09-03  Jiong Wang  <jiong.wang@arm.com>
 176
 177         * aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
 178         * aarch64-dis-2.c: Update auto-generated file.
 179
 180 2014-09-03  Jiong Wang  <jiong.wang@arm.com>
 181
 182         * aarch64-tbl.h (QL_R4NIL): New qualifiers.
 183         (aarch64_feature_lse): New feature added.
 184         (LSE): New Added.
 185         (aarch64_opcode_table): New LSE instructions added.  Improve
 186         descriptions for ldarb/ldarh/ldar.
 187         (aarch64_opcode_table): Describe PAIRREG.
 188         * aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
 189         * aarch64-opc.c (fields): Add entry for F_LSE_SZ.
 190         (aarch64_print_operand): Recognize PAIRREG.
 191         (operand_general_constraint_met_p): Check reg pair constraints for CASP
 192         instructions.
 193         * aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
 194         (do_special_decoding): Recognize F_LSE_SZ.
 195         * aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.
 196
 197 2014-08-26  Maciej W. Rozycki  <macro@codesourcery.com>
 198
 199         * micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
 200         (micromips_opcodes): Use "+J" in place of "B" for "hypcall",
 201         "sdbbp", "syscall" and "wait".
 202
 203 2014-08-21  Nathan Sidwell  <nathan@codesourcery.com>
 204             Maciej W. Rozycki  <macro@codesourcery.com>
 205
 206         * arm-dis.c (print_arm_address): Negate the GPR-relative offset
 207         returned if the U bit is set.
 208
 209 2014-08-21  Maciej W. Rozycki  <macro@codesourcery.com>
 210
 211         * micromips-opc.c (micromips_opcodes): Remove #ifdef-ed out
 212         48-bit "li" encoding.
 213
 214 2014-08-19  Andreas Arnez  <arnez@linux.vnet.ibm.com>
 215
 216         * s390-dis.c (s390_insn_length, s390_insn_matches_opcode)
 217         (s390_print_insn_with_opcode, opcode_mask_more_specific): New
 218         static functions, code was moved from...
 219         (print_insn_s390): ...here.
 220         (s390_extract_operand): Adjust comment.  Change type of first
 221         parameter from 'unsigned char *' to 'const bfd_byte *'.
 222         (union operand_value): New.
 223         (s390_extract_operand): Change return type to union operand_value.
 224         Also avoid integer overflow in sign-extension.
 225         (s390_print_insn_with_opcode): Adjust to changed return value from
 226         s390_extract_operand().  Change "%i" printf format to "%u" for
 227         unsigned values.
 228         (init_disasm): Simplify initialization of opc_index[].  This also
 229         fixes an access after the last element of s390_opcodes[].
 230         (print_insn_s390): Simplify the opcode search loop.
 231         Check architecture mask against all searched opcodes, not just the
 232         first matching one.
 233         (s390_print_insn_with_opcode): Drop function pointer dereferences
 234         without effect.
 235         (print_insn_s390): Likewise.
 236         (s390_insn_length): Simplify formula for return value.
 237         (s390_print_insn_with_opcode): Avoid special handling for the
 238         separator before the first operand.  Use new local variable
 239         'flags' in place of 'operand->flags'.
 240
 241 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 242
 243         * bfin-dis.c (struct private): Change int's to bfd_boolean's.
 244         (decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
 245         decode_dagMODik_0, decode_LDIMMhalf_0, decode_linkage_0):
 246         Change assignment of 1 to priv->comment to TRUE.
 247         (print_insn_bfin): Change legal to a bfd_boolean.  Change
 248         assignment of 0/1 with priv comment and parallel and legal
 249         to FALSE/TRUE.
 250
 251 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 252
 253         * bfin-dis.c (OUT): Define.
 254         (decode_CC2stat_0): Declare new op_names array.
 255         Replace multiple if statements with a single one.
 256
 257 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 258
 259         * bfin-dis.c (struct private): Add iw0.
 260         (_print_insn_bfin): Assign iw0 to priv.iw0.
 261         (print_insn_bfin): Drop ifetch and use priv.iw0.
 262
 263 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 264
 265         * bfin-dis.c (comment, parallel): Move from global scope ...
 266         (struct private): ... to this new struct.
 267         (decode_ProgCtrl_0, decode_CaCTRL_0, decode_PushPopReg_0,
 268         decode_PushPopMultiple_0, decode_ccMV_0, decode_CCflag_0,
 269         decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
 270         decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
 271         decode_dagMODik_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
 272         decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
 273         decode_pseudoOChar_0, decode_pseudodbg_assert_0, _print_insn_bfin,
 274         print_insn_bfin): Declare private struct.  Use priv's comment and
 275         parallel members.
 276
 277 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 278
 279         * bfin-dis.c (ifetch): Do not align pc to 2 bytes.
 280         (_print_insn_bfin): Add check for unaligned pc.
 281
 282 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 283
 284         * bfin-dis.c (ifetch): New function.
 285         (_print_insn_bfin, print_insn_bfin): Call new ifetch and return
 286         -1 when it errors.
 287
 288 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
 289
 290         * micromips-opc.c (COD): Rename throughout to...
 291         (CM): New define, update to use INSN_COPROC_MOVE.
 292         (LCD): Rename throughout to...
 293         (LC): New define, update to use INSN_LOAD_COPROC.
 294         * mips-opc.c: Likewise.
 295
 296 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
 297
 298         * micromips-opc.c (COD, LCD) New macros.
 299         (cfc1, ctc1): Remove FP_S attribute.
 300         (dmfc1, mfc1, mfhc1): Add LCD attribute.
 301         (dmtc1, mtc1, mthc1): Add COD attribute.
 302         * mips-opc.c (cfc1, cftc1, ctc, cttc1): Remove FP_S attribute.
 303
 304 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 305             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 306             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 307             Sergey Lega  <sergey.s.lega@intel.com>
 308             Anna Tikhonova  <anna.tikhonova@intel.com>
 309             Ilya Tocar  <ilya.tocar@intel.com>
 310             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 311             Ilya Verbin  <ilya.verbin@intel.com>
 312             Kirill Yukhin  <kirill.yukhin@intel.com>
 313             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 314
 315         * i386-dis-evex.h: Updated.
 316         * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
 317         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0F3A16,
 318         PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51,
 319         PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
 320         PREFIX_EVEX_0F3A67.
 321         (VEX_LEN enum): Add VEX_LEN_0F92_P_2, VEX_LEN_0F93_P_2,
 322         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_2_LEN_0.
 323         (VEX_W enum): Add EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 324         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, EVEX_W_0F57_P_0,
 325         EVEX_W_0F57_P_2, EVEX_W_0F78_P_2, EVEX_W_0F79_P_2, EVEX_W_0F7A_P_2,
 326         EVEX_W_0F7B_P_2, EVEX_W_0F3838_P_1, EVEX_W_0F3839_P_1,
 327         EVEX_W_0F3A16_P_2, EVEX_W_0F3A22_P_2, EVEX_W_0F3A50_P_2,
 328         EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2,
 329         EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2.
 330         (prefix_table): Add entries for new instructions.
 331         (vex_len_table): Ditto.
 332         (vex_w_table): Ditto.
 333         (OP_E_memory): Update xmmq_mode handling.
 334         * i386-gen.c (cpu_flag_init): Add CPU_AVX512DQ_FLAGS.
 335         (cpu_flags): Add CpuAVX512DQ.
 336         * i386-init.h: Regenerared.
 337         * i386-opc.h (CpuAVX512DQ): New.
 338         (i386_cpu_flags): Add cpuavx512dq.
 339         * i386-opc.tbl: Add AVX512DQ instructions.
 340         * i386-tbl.h: Regenerate.
 341
 342 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 343             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 344             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 345             Sergey Lega  <sergey.s.lega@intel.com>
 346             Anna Tikhonova  <anna.tikhonova@intel.com>
 347             Ilya Tocar  <ilya.tocar@intel.com>
 348             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 349             Ilya Verbin  <ilya.verbin@intel.com>
 350             Kirill Yukhin  <kirill.yukhin@intel.com>
 351             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 352
 353         * i386-dis-evex.h: Add new instructions (prefixes bellow).
 354         * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE.
 355         (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71.
 356         (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31,
 357         PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63,
 358         PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
 359         PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4,
 360         PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7,
 361         PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
 362         PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9,
 363         PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
 364         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4,
 365         PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA,
 366         PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
 367         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9,
 368         PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804,
 369         PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D,
 370         PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830,
 371         PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866,
 372         PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A,
 373         PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F,
 374         PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E,
 375         PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42.
 376         (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2,
 377         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 378         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2,
 379         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0,
 380         VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1,
 381         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1,
 382         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 383         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0,
 384         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0,
 385         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0,
 386         VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0.
 387         (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3,
 388         EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2,
 389         EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1,
 390         EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2,
 391         EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2,
 392         EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2,
 393         EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2.
 394         (prefix_table): Add entries for new instructions.
 395         (vex_table) : Ditto.
 396         (vex_len_table): Ditto.
 397         (vex_w_table): Ditto.
 398         (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode,
 399         mask_bd_mode handling.
 400         (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode
 401         handling.
 402         (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode
 403         handling.
 404         (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling.
 405         (OP_EX): Add dqw_swap_mode handling.
 406         (OP_VEX): Add mask_bd_mode handling.
 407         (OP_Mask): Add mask_bd_mode handling.
 408         * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS.
 409         (cpu_flags): Add CpuAVX512BW.
 410         * i386-init.h: Regenerated.
 411         * i386-opc.h (CpuAVX512BW): New.
 412         (i386_cpu_flags): Add cpuavx512bw.
 413         * i386-opc.tbl: Add AVX512BW instructions.
 414         * i386-tbl.h: Regenerate.
 415
 416 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 417             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 418             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 419             Sergey Lega  <sergey.s.lega@intel.com>
 420             Anna Tikhonova  <anna.tikhonova@intel.com>
 421             Ilya Tocar  <ilya.tocar@intel.com>
 422             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 423             Ilya Verbin  <ilya.verbin@intel.com>
 424             Kirill Yukhin  <kirill.yukhin@intel.com>
 425             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 426
 427         * i386-opc.tbl: Add AVX512VL and AVX512CD instructions.
 428         * i386-tbl.h: Regenerate.
 429
 430 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 431             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 432             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 433             Sergey Lega  <sergey.s.lega@intel.com>
 434             Anna Tikhonova  <anna.tikhonova@intel.com>
 435             Ilya Tocar  <ilya.tocar@intel.com>
 436             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 437             Ilya Verbin  <ilya.verbin@intel.com>
 438             Kirill Yukhin  <kirill.yukhin@intel.com>
 439             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 440
 441         * i386-dis.c (intel_operand_size): Support 128/256 length in
 442         vex_vsib_q_w_dq_mode.
 443         (OP_E_memory): Add ymmq_mode handling, handle new broadcast.
 444         * i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS.
 445         (cpu_flags): Add CpuAVX512VL.
 446         * i386-init.h: Regenerated.
 447         * i386-opc.h (CpuAVX512VL): New.
 448         (i386_cpu_flags): Add cpuavx512vl.
 449         (BROADCAST_1TO4, BROADCAST_1TO2): Define.
 450         * i386-opc.tbl: Add AVX512VL instructions.
 451         * i386-tbl.h: Regenerate.
 452
 453 2014-07-20  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>
 454
 455         * or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
 456         * or1k-opinst.c: Regenerate.
 457
 458 2014-07-08  Ilya Tocar  <ilya.tocar@intel.com>
 459
 460         * i386-dis-evex.h (EVEX_W_0F10_P_1_M_1): Fix vmovss.
 461         (EVEX_W_0F10_P_3_M_1): Fix vmovsd.
 462
 463 2014-07-04  Alan Modra  <amodra@gmail.com>
 464
 465         * configure.ac: Rename from configure.in.
 466         * Makefile.in: Regenerate.
 467         * config.in: Regenerate.
 468
 469 2014-07-04  Alan Modra  <amodra@gmail.com>
 470
 471         * configure.in: Include bfd/version.m4.
 472         (AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
 473         (BFD_VERSION): Delete.
 474         * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
 475         * configure: Regenerate.
 476         * Makefile.in: Regenerate.
 477
 478 2014-07-01  Barney Stratford   <barney_stratford@fastmail.fm>
 479             Senthil Kumar Selvaraj  <senthil_kumar.selvaraj@atmel.com>
 480             Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 481             Soundararajan  <Sounderarajan.D@atmel.com>
 482
 483         * avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
 484         (print_insn_avr): Do not select opcode if insn ISA is avrtiny and
 485         machine is not avrtiny.
 486
 487 2014-06-26  Philippe De Muyter <phdm@macqel.be>
 488
 489         * or1k-desc.h (spr_field_masks): Add U suffix to the end of long
 490         constants.
 491
 492 2014-06-12  Alan Modra  <amodra@gmail.com>
 493
 494         * or1k-asm.c, * or1k-desc.c, * or1k-desc.h, * or1k-dis.c,
 495         * or1k-ibld.c, * or1k-opc.c, * or1k-opc.h, * or1k-opinst.c: Regenerate.
 496
 497 2014-06-10  H.J. Lu  <hongjiu.lu@intel.com>
 498
 499         * i386-dis.c (fwait_prefix): New.
 500         (ckprefix): Set fwait_prefix.
 501         (print_insn): Properly print prefixes before fwait.
 502
 503 2014-06-07  Alan Modra  <amodra@gmail.com>
 504
 505         * ppc-opc.c (UISIGNOPT): Define and use with cmpli.
 506
 507 2014-06-05  Joel Brobecker  <brobecker@adacore.com>
 508
 509         * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
 510         bfd's development.sh.
 511         * Makefile.in, configure: Regenerate.
 512
 513 2014-06-03  Nick Clifton  <nickc@redhat.com>
 514
 515         * msp430-dis.c (msp430_doubleoperand): Use extension_word to
 516         decide when extended addressing is being used.
 517
 518 2014-06-02  Eric Botcazou  <ebotcazou@adacore.com>
 519
 520         * sparc-opc.c (cas): Disable for LEON.
 521         (casl): Likewise.
 522
 523 2014-05-20  Alan Modra  <amodra@gmail.com>
 524
 525         * m68k-dis.c: Don't include setjmp.h.
 526
 527 2014-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 528
 529         * i386-dis.c (ADDR16_PREFIX): Removed.
 530         (ADDR32_PREFIX): Likewise.
 531         (DATA16_PREFIX): Likewise.
 532         (DATA32_PREFIX): Likewise.
 533         (prefix_name): Updated.
 534         (print_insn): Simplify data and address size prefixes processing.
 535
 536 2014-05-08  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>
 537
 538         * or1k-desc.c: Regenerated.
 539         * or1k-desc.h: Likewise.
 540         * or1k-opc.c: Likewise.
 541         * or1k-opc.h: Likewise.
 542         * or1k-opinst.c: Likewise.
 543
 544 2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
 545
 546         * mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
 547         (I34): New define.
 548         (I36): New define.
 549         (I66): New define.
 550         (I68): New define.
 551         * mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
 552         mips64r5.
 553         (parse_mips_dis_option): Update MSA and virtualization support to
 554         allow mips64r3 and mips64r5.
 555
 556 2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
 557
 558         * mips-opc.c (G3): Remove I4.
 559
 560 2014-05-05  H.J. Lu  <hongjiu.lu@intel.com>
 561
 562         PR binutils/16893
 563         * i386-dis.c (twobyte_has_mandatory_prefix): New variable.
 564         (end_codep): Likewise.
 565         (mandatory_prefix): Likewise.
 566         (active_seg_prefix): Likewise.
 567         (ckprefix): Set active_seg_prefix to the active segment register
 568         prefix.
 569         (seg_prefix): Removed.
 570         (get_valid_dis386): Use the last of PREFIX_REPNZ and PREFIX_REPZ
 571         for prefix index.  Ignore the index if it is invalid and the
 572         mandatory prefix isn't required.
 573         (print_insn): Set mandatory_prefix if the PREFIX_XXX prefix is
 574         mandatory.  Don't set PREFIX_REPZ/PREFIX_REPNZ/PREFIX_LOCK bits
 575         in used_prefixes here.  Don't print unused prefixes.  Check
 576         active_seg_prefix for the active segment register prefix.
 577         Restore the DFLAG bit in sizeflag if the data size prefix is
 578         unused.  Check the unused mandatory PREFIX_XXX prefixes
 579         (append_seg): Only print the segment register which gets used.
 580         (OP_E_memory): Check active_seg_prefix for the segment register
 581         prefix.
 582         (OP_OFF): Likewise.
 583         (OP_OFF64): Likewise.
 584         (OP_DSreg): Set active_seg_prefix to PREFIX_DS if it is unset.
 585
 586 2014-05-02  H.J. Lu  <hongjiu.lu@intel.com>
 587
 588         PR binutils/16886
 589         * config.in: Regenerated.
 590         * configure: Likewise.
 591         * configure.in: Check if sigsetjmp is available.
 592         * h8500-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 593         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 594         (print_insn_h8500): Replace setjmp with OPCODES_SIGSETJMP.
 595         * i386-dis.c (dis_private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 596         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 597         (print_insn): Replace setjmp with OPCODES_SIGSETJMP.
 598         * ns32k-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 599         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 600         (print_insn_ns32k): Replace setjmp with OPCODES_SIGSETJMP.
 601         * sysdep.h (OPCODES_SIGJMP_BUF): New macro.
 602         (OPCODES_SIGSETJMP): Likewise.
 603         (OPCODES_SIGLONGJMP): Likewise.
 604         * vax-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 605         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 606         (print_insn_vax): Replace setjmp with OPCODES_SIGSETJMP.
 607         * xtensa-dis.c (dis_private): Replace jmp_buf with
 608         OPCODES_SIGJMP_BUF.
 609         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 610         (print_insn_xtensa): Replace setjmp with OPCODES_SIGSETJMP.
 611         * z8k-dis.c(instr_data_s): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 612         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 613         (print_insn_z8k): Replace setjmp with OPCODES_SIGSETJMP.
 614
 615 2014-05-01  H.J. Lu  <hongjiu.lu@intel.com>
 616
 617         PR binutils/16891
 618         * i386-dis.c (print_insn): Handle prefixes before fwait.
 619
 620 2014-04-26  Alan Modra  <amodra@gmail.com>
 621
 622         * po/POTFILES.in: Regenerate.
 623
 624 2014-04-23  Andrew Bennett  <andrew.bennett@imgtec.com>
 625
 626         * mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
 627         to allow the MIPS XPA ASE.
 628         (parse_mips_dis_option): Process the -Mxpa option.
 629         * mips-opc.c (XPA): New define.
 630         (mips_builtin_opcodes): Add MIPS XPA instructions and move the
 631         locations of the ctc0 and cfc0 instructions.
 632
 633 2014-04-22  Christian Svensson  <blue@cmd.nu>
 634
 635         * Makefile.am: Remove openrisc and or32 support.  Add support for or1k.
 636         * configure.in: Likewise.
 637         * disassemble.c: Likewise.
 638         * or1k-asm.c: New file.
 639         * or1k-desc.c: New file.
 640         * or1k-desc.h: New file.
 641         * or1k-dis.c: New file.
 642         * or1k-ibld.c: New file.
 643         * or1k-opc.c: New file.
 644         * or1k-opc.h: New file.
 645         * or1k-opinst.c: New file.
 646         * Makefile.in: Regenerate.
 647         * configure: Regenerate.
 648         * openrisc-asm.c: Delete.
 649         * openrisc-desc.c: Delete.
 650         * openrisc-desc.h: Delete.
 651         * openrisc-dis.c: Delete.
 652         * openrisc-ibld.c: Delete.
 653         * openrisc-opc.c: Delete.
 654         * openrisc-opc.h: Delete.
 655         * or32-dis.c: Delete.
 656         * or32-opc.c: Delete.
 657
 658 2014-04-04  Ilya Tocar  <ilya.tocar@intel.com>
 659
 660         * i386-dis.c (rm_table): Add encls, enclu.
 661         * i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
 662         (cpu_flags): Add CpuSE1.
 663         * i386-opc.h (enum): Add CpuSE1.
 664         (i386_cpu_flags): Add cpuse1.
 665         * i386-opc.tbl: Add encls, enclu.
 666         * i386-init.h: Regenerated.
 667         * i386-tbl.h: Likewise.
 668
 669 2014-04-02  Anthony Green  <green@moxielogic.com>
 670
 671         * moxie-opc.c (moxie_form1_opc_info): Add sign-extension
 672         instructions, sex.b and sex.s.
 673
 674 2014-03-26  Jiong Wang  <jiong.wang@arm.com>
 675
 676         * aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
 677         instructions.
 678
 679 2014-03-20  Ilya Tocar  <ilya.tocar@intel.com>
 680
 681         * i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
 682         vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
 683         vscatterqps.
 684         * i386-tbl.h: Regenerate.
 685
 686 2014-03-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 687
 688         * sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
 689         %hstick_enable added.
 690
 691 2014-03-19  Nick Clifton  <nickc@redhat.com>
 692
 693         * rx-decode.opc (bwl): Allow for bogus instructions with a size
 694         field of 3.
 695         (sbwl, ubwl, SCALE): Likewise.
 696         * rx-decode.c: Regenerate.
 697
 698 2014-03-12  Alan Modra  <amodra@gmail.com>
 699
 700         * Makefile.in: Regenerate.
 701
 702 2014-03-05  Alan Modra  <amodra@gmail.com>
 703
 704         Update copyright years.
 705
 706 2014-03-04  Heiher  <r@hev.cc>
 707
 708         * mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
 709
 710 2014-03-04  Richard Sandiford  <rdsandiford@googlemail.com>
 711
 712         * mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
 713         so that they come after the Loongson extensions.
 714
 715 2014-03-03  Alan Modra  <amodra@gmail.com>
 716
 717         * i386-gen.c (process_copyright): Emit copyright notice on one line.
 718
 719 2014-02-28  Alan Modra  <amodra@gmail.com>
 720
 721         * msp430-decode.c: Regenerate.
 722
 723 2014-02-27  Jiong Wang  <jiong.wang@arm.com>
 724
 725         * aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
 726         FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.
 727
 728 2014-02-27  Yufeng Zhang  <yufeng.zhang@arm.com>
 729
 730         * aarch64-opc.c (print_register_offset_address): Call
 731         get_int_reg_name to prepare the register name.
 732
 733 2014-02-25  Ilya Tocar  <ilya.tocar@intel.com>
 734
 735         * i386-opc.tbl: Remove wrong variant of vcvtps2ph
 736         * i386-tbl.h: Regenerate.
 737
 738 2014-02-20  Ilya Tocar  <ilya.tocar@intel.com>
 739
 740         * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
 741         (cpu_flags): Add CpuPREFETCHWT1.
 742         * i386-init.h: Regenerate.
 743         * i386-opc.h (CpuPREFETCHWT1): New.
 744         (i386_cpu_flags): Add cpuprefetchwt1.
 745         * i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1.
 746         * i386-tbl.h: Regenerate.
 747
 748 2014-02-20  Ilya Tocar  <ilya.tocar@intel.com>
 749
 750         * i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD,
 751         to CpuAVX512F.
 752         * i386-tbl.h: Regenerate.
 753
 754 2014-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 755
 756         * i386-gen.c (output_cpu_flags): Don't output trailing space.
 757         (output_opcode_modifier): Likewise.
 758         (output_operand_type): Likewise.
 759         * i386-init.h: Regenerated.
 760         * i386-tbl.h: Likewise.
 761
 762 2014-02-12  Ilya Tocar  <ilya.tocar@intel.com>
 763
 764         * i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
 765         MOD_0FC7_REG_5.
 766         (PREFIX enum): Add PREFIX_0FAE_REG_7.
 767         (reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
 768         (prefix_table): Add clflusopt.
 769         (mod_table): Add xrstors, xsavec, xsaves.
 770         * i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
 771         CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
 772         (cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
 773         * i386-init.h: Regenerate.
 774         * i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
 775         xsaves64, xsavec, xsavec64.
 776         * i386-tbl.h: Regenerate.
 777
 778 2014-02-10  Alan Modra  <amodra@gmail.com>
 779
 780         * po/POTFILES.in: Regenerate.
 781         * po/opcodes.pot: Regenerate.
 782
 783 2014-01-30  Michael Zolotukhin  <michael.v.zolotukhin@gmail.com>
 784             Jan Beulich  <jbeulich@suse.com>
 785
 786         PR binutils/16490
 787         * i386-dis.c (OP_E_memory): Fix shift computation for
 788         vex_vsib_q_w_dq_mode.
 789
 790 2014-01-09  Bradley Nelson  <bradnelson@google.com>
 791             Roland McGrath  <mcgrathr@google.com>
 792
 793         * i386-dis.c (print_insn): Do not touch all_prefixes[-1] when
 794         last_rex_prefix is -1.
 795
 796 2014-01-08  H.J. Lu  <hongjiu.lu@intel.com>
 797
 798         * i386-gen.c (process_copyright): Update copyright year to 2014.
 799
 800 2014-01-03  Maciej W. Rozycki  <macro@codesourcery.com>
 801
 802         * nds32-asm.c (parse_operand): Fix out-of-range integer constant.
 803
 804 For older changes see ChangeLog-2013
 805 \f
 806 Copyright (C) 2014 Free Software Foundation, Inc.
 807
 808 Copying and distribution of this file, with or without modification,
 809 are permitted in any medium without royalty provided the copyright
 810 notice and this notice are preserved.
 811
 812 Local Variables:
 813 mode: change-log
 814 left-margin: 8
 815 fill-column: 74
 816 version-control: never
 817 End: