1 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
3 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
5 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
8 2017-06-19 Nick Clifton <nickc@redhat.com>
11 * score-dis.c (score_opcodes): Add sentinel.
13 2017-06-16 Alan Modra <amodra@gmail.com>
15 * rx-decode.c: Regenerate.
17 2017-06-15 H.J. Lu <hongjiu.lu@intel.com>
20 * i386-dis.c (OP_E_register): Check valid bnd register.
23 2017-06-15 Nick Clifton <nickc@redhat.com>
26 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
29 2017-06-15 Nick Clifton <nickc@redhat.com>
32 * rl78-decode.opc (OP_BUF_LEN): Define.
33 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
34 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
36 * rl78-decode.c: Regenerate.
38 2017-06-15 Nick Clifton <nickc@redhat.com>
41 * bfin-dis.c (gregs): Clip index to prevent overflow.
46 2017-06-14 Nick Clifton <nickc@redhat.com>
49 * score7-dis.c (score_opcodes): Add sentinel.
51 2017-06-14 Yao Qi <yao.qi@linaro.org>
53 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
54 * arm-dis.c: Likewise.
55 * ia64-dis.c: Likewise.
56 * mips-dis.c: Likewise.
57 * spu-dis.c: Likewise.
58 * disassemble.h (print_insn_aarch64): New declaration, moved from
60 (print_insn_big_arm, print_insn_big_mips): Likewise.
61 (print_insn_i386, print_insn_ia64): Likewise.
62 (print_insn_little_arm, print_insn_little_mips): Likewise.
64 2017-06-14 Nick Clifton <nickc@redhat.com>
67 * rx-decode.opc: Include libiberty.h
68 (GET_SCALE): New macro - validates access to SCALE array.
69 (GET_PSCALE): New macro - validates access to PSCALE array.
70 (DIs, SIs, S2Is, rx_disp): Use new macros.
71 * rx-decode.c: Regenerate.
73 2017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
75 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
77 2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
79 * arc-dis.c (enforced_isa_mask): Declare.
80 (cpu_types): Likewise.
81 (parse_cpu_option): New function.
82 (parse_disassembler_options): Use it.
83 (print_insn_arc): Use enforced_isa_mask.
84 (print_arc_disassembler_options): Document new options.
86 2017-05-24 Yao Qi <yao.qi@linaro.org>
88 * alpha-dis.c: Include disassemble.h, don't include
90 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
91 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
92 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
93 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
94 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
95 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
96 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
97 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
98 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
99 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
100 * moxie-dis.c, msp430-dis.c, mt-dis.c:
101 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
102 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
103 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
104 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
105 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
106 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
107 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
108 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
109 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
110 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
111 * z80-dis.c, z8k-dis.c: Likewise.
112 * disassemble.h: New file.
114 2017-05-24 Yao Qi <yao.qi@linaro.org>
116 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
117 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
119 2017-05-24 Yao Qi <yao.qi@linaro.org>
121 * disassemble.c (disassembler): Add arguments a, big and mach.
124 2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
126 * i386-dis.c (NOTRACK_Fixup): New.
128 (NOTRACK_PREFIX): Likewise.
129 (last_active_prefix): Likewise.
130 (reg_table): Use NOTRACK on indirect call and jmp.
131 (ckprefix): Set last_active_prefix.
132 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
133 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
134 * i386-opc.h (NoTrackPrefixOk): New.
135 (i386_opcode_modifier): Add notrackprefixok.
136 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
138 * i386-tbl.h: Regenerated.
140 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
142 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
144 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
146 (print_insn_sparc): Handle new operand types.
147 * sparc-opc.c (MASK_M8): Define.
149 (v6notlet): Likewise.
160 (v9andleon): Likewise.
163 (HWS2_VM8): Likewise.
164 (sparc_opcode_archs): Add entry for "m8".
165 (sparc_opcodes): Add OSA2017 and M8 instructions
166 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
168 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
169 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
170 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
171 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
172 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
173 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
174 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
175 ASI_CORE_SELECT_COMMIT_NHT.
177 2017-05-18 Alan Modra <amodra@gmail.com>
179 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
180 * aarch64-dis.c: Likewise.
181 * aarch64-gen.c: Likewise.
182 * aarch64-opc.c: Likewise.
184 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
185 Matthew Fortune <matthew.fortune@imgtec.com>
187 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
188 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
189 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
190 (print_insn_arg) <OP_REG28>: Add handler.
191 (validate_insn_args) <OP_REG28>: Handle.
192 (print_mips16_insn_arg): Handle MIPS16 instructions that require
193 32-bit encoding and 9-bit immediates.
194 (print_insn_mips16): Handle MIPS16 instructions that require
195 32-bit encoding and MFC0/MTC0 operand decoding.
196 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
197 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
198 (RD_C0, WR_C0, E2, E2MT): New macros.
199 (mips16_opcodes): Add entries for MIPS16e2 instructions:
200 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
201 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
202 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
203 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
204 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
205 instructions, "swl", "swr", "sync" and its "sync_acquire",
206 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
207 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
208 regular/extended entries for original MIPS16 ISA revision
209 instructions whose extended forms are subdecoded in the MIPS16e2
210 ISA revision: "li", "sll" and "srl".
212 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
214 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
215 reference in CP0 move operand decoding.
217 2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
219 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
221 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
223 2017-05-11 Maciej W. Rozycki <macro@imgtec.com>
225 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
226 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
227 "sync_rmb" and "sync_wmb" as aliases.
228 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
229 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
231 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
233 * arc-dis.c (parse_option): Update quarkse_em option..
234 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
236 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
238 2017-05-03 Kito Cheng <kito.cheng@gmail.com>
240 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
242 2017-05-01 Michael Clark <michaeljclark@mac.com>
244 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
247 2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
249 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
250 and branches and not synthetic data instructions.
252 2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
254 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
256 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
258 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
259 * arc-opc.c (insert_r13el): New function.
261 * arc-tbl.h: Add new enter/leave variants.
263 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
265 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
267 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
269 * mips-dis.c (print_mips_disassembler_options): Add
272 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
274 * mips16-opc.c (AL): New macro.
275 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
276 of "ld" and "lw" as aliases.
278 2017-04-24 Tamar Christina <tamar.christina@arm.com>
280 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
283 2017-04-22 Alexander Fedotov <alfedotov@gmail.com>
284 Alan Modra <amodra@gmail.com>
286 * ppc-opc.c (ELEV): Define.
287 (vle_opcodes): Add se_rfgi and e_sc.
288 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
291 2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
293 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
295 2017-04-21 Nick Clifton <nickc@redhat.com>
298 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
301 2017-04-13 Alan Modra <amodra@gmail.com>
303 * epiphany-desc.c: Regenerate.
304 * fr30-desc.c: Regenerate.
305 * frv-desc.c: Regenerate.
306 * ip2k-desc.c: Regenerate.
307 * iq2000-desc.c: Regenerate.
308 * lm32-desc.c: Regenerate.
309 * m32c-desc.c: Regenerate.
310 * m32r-desc.c: Regenerate.
311 * mep-desc.c: Regenerate.
312 * mt-desc.c: Regenerate.
313 * or1k-desc.c: Regenerate.
314 * xc16x-desc.c: Regenerate.
315 * xstormy16-desc.c: Regenerate.
317 2017-04-11 Alan Modra <amodra@gmail.com>
319 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
320 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
321 PPC_OPCODE_TMR for e6500.
322 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
323 (PPCVEC3): Define as PPC_OPCODE_POWER9.
324 (PPCVSX2): Define as PPC_OPCODE_POWER8.
325 (PPCVSX3): Define as PPC_OPCODE_POWER9.
326 (PPCHTM): Define as PPC_OPCODE_POWER8.
327 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
329 2017-04-10 Alan Modra <amodra@gmail.com>
331 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
332 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
333 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
334 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
336 2017-04-09 Pip Cet <pipcet@gmail.com>
338 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
339 appropriate floating-point precision directly.
341 2017-04-07 Alan Modra <amodra@gmail.com>
343 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
344 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
345 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
346 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
347 vector instructions with E6500 not PPCVEC2.
349 2017-04-06 Pip Cet <pipcet@gmail.com>
351 * Makefile.am: Add wasm32-dis.c.
352 * configure.ac: Add wasm32-dis.c to wasm32 target.
353 * disassemble.c: Add wasm32 disassembler code.
354 * wasm32-dis.c: New file.
355 * Makefile.in: Regenerate.
356 * configure: Regenerate.
357 * po/POTFILES.in: Regenerate.
358 * po/opcodes.pot: Regenerate.
360 2017-04-05 Pedro Alves <palves@redhat.com>
362 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
363 * arm-dis.c (parse_arm_disassembler_options): Constify.
364 * ppc-dis.c (powerpc_init_dialect): Constify local.
365 * vax-dis.c (parse_disassembler_options): Constify.
367 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
369 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
372 2017-03-30 Pip Cet <pipcet@gmail.com>
374 * configure.ac: Add (empty) bfd_wasm32_arch target.
375 * configure: Regenerate
376 * po/opcodes.pot: Regenerate.
378 2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
380 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
382 * opcodes/sparc-opc.c (asi_table): New ASIs.
384 2017-03-29 Alan Modra <amodra@gmail.com>
386 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
388 (lookup_powerpc): Don't special case -1 dialect. Handle
390 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
391 lookup_powerpc call, pass it on second.
393 2017-03-27 Alan Modra <amodra@gmail.com>
396 * ppc-dis.c (struct ppc_mopt): Comment.
397 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
399 2017-03-27 Rinat Zelig <rinat@mellanox.com>
401 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
402 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
403 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
404 (insert_nps_misc_imm_offset): New function.
405 (extract_nps_misc imm_offset): New function.
406 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
407 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
409 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
411 * s390-mkopc.c (main): Remove vx2 check.
412 * s390-opc.txt: Remove vx2 instruction flags.
414 2017-03-21 Rinat Zelig <rinat@mellanox.com>
416 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
417 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
418 (insert_nps_imm_offset): New function.
419 (extract_nps_imm_offset): New function.
420 (insert_nps_imm_entry): New function.
421 (extract_nps_imm_entry): New function.
423 2017-03-17 Alan Modra <amodra@gmail.com>
426 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
427 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
428 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
430 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
432 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
436 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
438 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
440 2017-03-13 Andrew Waterman <andrew@sifive.com>
442 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
447 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
449 * i386-gen.c (opcode_modifiers): Replace S with Load.
450 * i386-opc.h (S): Removed.
452 (i386_opcode_modifier): Replace s with load.
453 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
454 and {evex}. Replace S with Load.
455 * i386-tbl.h: Regenerated.
457 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
459 * i386-opc.tbl: Use CpuCET on rdsspq.
460 * i386-tbl.h: Regenerated.
462 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
464 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
465 <vsx>: Do not use PPC_OPCODE_VSX3;
467 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
469 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
471 2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
473 * i386-dis.c (REG_0F1E_MOD_3): New enum.
474 (MOD_0F1E_PREFIX_1): Likewise.
475 (MOD_0F38F5_PREFIX_2): Likewise.
476 (MOD_0F38F6_PREFIX_0): Likewise.
477 (RM_0F1E_MOD_3_REG_7): Likewise.
478 (PREFIX_MOD_0_0F01_REG_5): Likewise.
479 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
480 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
481 (PREFIX_0F1E): Likewise.
482 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
483 (PREFIX_0F38F5): Likewise.
484 (dis386_twobyte): Use PREFIX_0F1E.
485 (reg_table): Add REG_0F1E_MOD_3.
486 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
487 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
488 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
489 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
490 (three_byte_table): Use PREFIX_0F38F5.
491 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
492 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
493 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
494 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
495 PREFIX_MOD_3_0F01_REG_5_RM_2.
496 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
497 (cpu_flags): Add CpuCET.
498 * i386-opc.h (CpuCET): New enum.
499 (CpuUnused): Commented out.
500 (i386_cpu_flags): Add cpucet.
501 * i386-opc.tbl: Add Intel CET instructions.
502 * i386-init.h: Regenerated.
503 * i386-tbl.h: Likewise.
505 2017-03-06 Alan Modra <amodra@gmail.com>
508 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
509 (extract_raq, extract_ras, extract_rbx): New functions.
510 (powerpc_operands): Use opposite corresponding insert function.
512 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
513 register restriction.
515 2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
517 * disassemble.c Include "safe-ctype.h".
518 (disassemble_init_for_target): Handle s390 init.
519 (remove_whitespace_and_extra_commas): New function.
520 (disassembler_options_cmp): Likewise.
521 * arm-dis.c: Include "libiberty.h".
523 (regnames): Use long disassembler style names.
524 Add force-thumb and no-force-thumb options.
525 (NUM_ARM_REGNAMES): Rename from this...
526 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
527 (get_arm_regname_num_options): Delete.
528 (set_arm_regname_option): Likewise.
529 (get_arm_regnames): Likewise.
530 (parse_disassembler_options): Likewise.
531 (parse_arm_disassembler_option): Rename from this...
532 (parse_arm_disassembler_options): ...to this. Make static.
533 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
534 (print_insn): Use parse_arm_disassembler_options.
535 (disassembler_options_arm): New function.
536 (print_arm_disassembler_options): Handle updated regnames.
537 * ppc-dis.c: Include "libiberty.h".
538 (ppc_opts): Add "32" and "64" entries.
539 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
540 (powerpc_init_dialect): Add break to switch statement.
541 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
542 (disassembler_options_powerpc): New function.
543 (print_ppc_disassembler_options): Use ARRAY_SIZE.
544 Remove printing of "32" and "64".
545 * s390-dis.c: Include "libiberty.h".
546 (init_flag): Remove unneeded variable.
547 (struct s390_options_t): New structure type.
548 (options): New structure.
549 (init_disasm): Rename from this...
550 (disassemble_init_s390): ...to this. Add initializations for
551 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
552 (print_insn_s390): Delete call to init_disasm.
553 (disassembler_options_s390): New function.
554 (print_s390_disassembler_options): Print using information from
556 * po/opcodes.pot: Regenerate.
558 2017-02-28 Jan Beulich <jbeulich@suse.com>
560 * i386-dis.c (PCMPESTR_Fixup): New.
561 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
562 (prefix_table): Use PCMPESTR_Fixup.
563 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
565 (vex_w_table): Delete VPCMPESTR{I,M} entries.
566 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
567 Split 64-bit and non-64-bit variants.
568 * opcodes/i386-tbl.h: Re-generate.
570 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
572 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
573 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
574 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
575 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
576 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
577 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
578 (OP_SVE_V_HSD): New macros.
579 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
580 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
581 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
582 (aarch64_opcode_table): Add new SVE instructions.
583 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
584 for rotation operands. Add new SVE operands.
585 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
586 (ins_sve_quad_index): Likewise.
587 (ins_imm_rotate): Split into...
588 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
589 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
590 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
592 (aarch64_ins_sve_addr_ri_s4): New function.
593 (aarch64_ins_sve_quad_index): Likewise.
594 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
595 * aarch64-asm-2.c: Regenerate.
596 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
597 (ext_sve_quad_index): Likewise.
598 (ext_imm_rotate): Split into...
599 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
600 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
601 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
603 (aarch64_ext_sve_addr_ri_s4): New function.
604 (aarch64_ext_sve_quad_index): Likewise.
605 (aarch64_ext_sve_index): Allow quad indices.
606 (do_misc_decoding): Likewise.
607 * aarch64-dis-2.c: Regenerate.
608 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
610 (OPD_F_OD_MASK): Widen by one bit.
611 (OPD_F_NO_ZR): Bump accordingly.
612 (get_operand_field_width): New function.
613 * aarch64-opc.c (fields): Add new SVE fields.
614 (operand_general_constraint_met_p): Handle new SVE operands.
615 (aarch64_print_operand): Likewise.
616 * aarch64-opc-2.c: Regenerate.
618 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
620 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
621 (aarch64_feature_compnum): ...this.
622 (SIMD_V8_3): Replace with...
624 (CNUM_INSN): New macro.
625 (aarch64_opcode_table): Use it for the complex number instructions.
627 2017-02-24 Jan Beulich <jbeulich@suse.com>
629 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
631 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
633 Add support for associating SPARC ASIs with an architecture level.
634 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
635 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
636 decoding of SPARC ASIs.
638 2017-02-23 Jan Beulich <jbeulich@suse.com>
640 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
641 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
643 2017-02-21 Jan Beulich <jbeulich@suse.com>
645 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
646 1 (instead of to itself). Correct typo.
648 2017-02-14 Andrew Waterman <andrew@sifive.com>
650 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
653 2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
655 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
656 (aarch64_sys_reg_supported_p): Handle them.
658 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
660 * arc-opc.c (UIMM6_20R): Define.
661 (SIMM12_20): Use above.
662 (SIMM12_20R): Define.
663 (SIMM3_5_S): Use above.
664 (UIMM7_A32_11R_S): Define.
665 (UIMM7_9_S): Use above.
666 (UIMM3_13R_S): Define.
667 (SIMM11_A32_7_S): Use above.
669 (UIMM10_A32_8_S): Use above.
670 (UIMM8_8R_S): Define.
672 (arc_relax_opcodes): Use all above defines.
674 2017-02-15 Vineet Gupta <vgupta@synopsys.com>
676 * arc-regs.h: Distinguish some of the registers different on
677 ARC700 and HS38 cpus.
679 2017-02-14 Alan Modra <amodra@gmail.com>
682 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
683 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
685 2017-02-11 Stafford Horne <shorne@gmail.com>
686 Alan Modra <amodra@gmail.com>
688 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
689 Use insn_bytes_value and insn_int_value directly instead. Don't
690 free allocated memory until function exit.
692 2017-02-10 Nicholas Piggin <npiggin@gmail.com>
694 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
696 2017-02-03 Nick Clifton <nickc@redhat.com>
699 * aarch64-opc.c (print_register_list): Ensure that the register
700 list index will fir into the tb buffer.
701 (print_register_offset_address): Likewise.
702 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
704 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
707 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
708 instructions when the previous fetch packet ends with a 32-bit
711 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
713 * pru-opc.c: Remove vague reference to a future GDB port.
715 2017-01-20 Nick Clifton <nickc@redhat.com>
717 * po/ga.po: Updated Irish translation.
719 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
721 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
723 2017-01-13 Yao Qi <yao.qi@linaro.org>
725 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
726 if FETCH_DATA returns 0.
727 (m68k_scan_mask): Likewise.
728 (print_insn_m68k): Update code to handle -1 return value.
730 2017-01-13 Yao Qi <yao.qi@linaro.org>
732 * m68k-dis.c (enum print_insn_arg_error): New.
733 (NEXTBYTE): Replace -3 with
734 PRINT_INSN_ARG_MEMORY_ERROR.
735 (NEXTULONG): Likewise.
736 (NEXTSINGLE): Likewise.
737 (NEXTDOUBLE): Likewise.
738 (NEXTDOUBLE): Likewise.
739 (NEXTPACKED): Likewise.
740 (FETCH_ARG): Likewise.
741 (FETCH_DATA): Update comments.
742 (print_insn_arg): Update comments. Replace magic numbers with
744 (match_insn_m68k): Likewise.
746 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
748 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
749 * i386-dis-evex.h (evex_table): Updated.
750 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
751 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
752 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
753 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
754 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
755 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
756 * i386-init.h: Regenerate.
759 2017-01-12 Yao Qi <yao.qi@linaro.org>
761 * msp430-dis.c (msp430_singleoperand): Return -1 if
762 msp430dis_opcode_signed returns false.
763 (msp430_doubleoperand): Likewise.
764 (msp430_branchinstr): Return -1 if
765 msp430dis_opcode_unsigned returns false.
766 (msp430x_calla_instr): Likewise.
767 (print_insn_msp430): Likewise.
769 2017-01-05 Nick Clifton <nickc@redhat.com>
772 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
773 could not be matched.
774 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
777 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
779 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
780 (aarch64_opcode_table): Use RCPC_INSN.
782 2017-01-03 Kito Cheng <kito.cheng@gmail.com>
784 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
786 * riscv-opcodes/all-opcodes: Likewise.
788 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
790 * riscv-dis.c (print_insn_args): Add fall through comment.
792 2017-01-03 Nick Clifton <nickc@redhat.com>
794 * po/sr.po: New Serbian translation.
795 * configure.ac (ALL_LINGUAS): Add sr.
796 * configure: Regenerate.
798 2017-01-02 Alan Modra <amodra@gmail.com>
800 * epiphany-desc.h: Regenerate.
801 * epiphany-opc.h: Regenerate.
802 * fr30-desc.h: Regenerate.
803 * fr30-opc.h: Regenerate.
804 * frv-desc.h: Regenerate.
805 * frv-opc.h: Regenerate.
806 * ip2k-desc.h: Regenerate.
807 * ip2k-opc.h: Regenerate.
808 * iq2000-desc.h: Regenerate.
809 * iq2000-opc.h: Regenerate.
810 * lm32-desc.h: Regenerate.
811 * lm32-opc.h: Regenerate.
812 * m32c-desc.h: Regenerate.
813 * m32c-opc.h: Regenerate.
814 * m32r-desc.h: Regenerate.
815 * m32r-opc.h: Regenerate.
816 * mep-desc.h: Regenerate.
817 * mep-opc.h: Regenerate.
818 * mt-desc.h: Regenerate.
819 * mt-opc.h: Regenerate.
820 * or1k-desc.h: Regenerate.
821 * or1k-opc.h: Regenerate.
822 * xc16x-desc.h: Regenerate.
823 * xc16x-opc.h: Regenerate.
824 * xstormy16-desc.h: Regenerate.
825 * xstormy16-opc.h: Regenerate.
827 2017-01-02 Alan Modra <amodra@gmail.com>
829 Update year range in copyright notice of all files.
831 For older changes see ChangeLog-2016
833 Copyright (C) 2017 Free Software Foundation, Inc.
835 Copying and distribution of this file, with or without modification,
836 are permitted in any medium without royalty provided the copyright
837 notice and this notice are preserved.
843 version-control: never