opcodes/ChangeLog

   1 2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
   2
   3         * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
   4         fields to NULL.
   5         (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
   6
   7 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
   8
   9         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
  10         section disassembled.
  11
  12 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
  13
  14         * arm-dis.c: Update strht pattern.
  15
  16 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
  17
  18         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
  19         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
  20         trunc.w.s macro for EE.
  21
  22 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
  23             Andrew Jenner <andrew@codesourcery.com>
  24
  25         Based on patches from Altera Corporation.
  26
  27         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
  28         nios2-opc.c.
  29         * Makefile.in: Regenerated.
  30         * configure.in: Add case for bfd_nios2_arch.
  31         * configure: Regenerated.
  32         * disassemble.c (ARCH_nios2): Define.
  33         (disassembler): Add case for bfd_arch_nios2.
  34         * nios2-dis.c: New file.
  35         * nios2-opc.c: New file.
  36
  37 2013-02-04  Alan Modra  <amodra@gmail.com>
  38
  39         * po/POTFILES.in: Regenerate.
  40         * rl78-decode.c: Regenerate.
  41         * rx-decode.c: Regenerate.
  42
  43 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
  44
  45         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
  46         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
  47         * aarch64-asm.c (convert_xtl_to_shll): New function.
  48         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
  49         calling convert_xtl_to_shll.
  50         * aarch64-dis.c (convert_shll_to_xtl): New function.
  51         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
  52         calling convert_shll_to_xtl.
  53         * aarch64-gen.c: Update copyright year.
  54         * aarch64-asm-2.c: Re-generate.
  55         * aarch64-dis-2.c: Re-generate.
  56         * aarch64-opc-2.c: Re-generate.
  57
  58 2013-01-24  Nick Clifton  <nickc@redhat.com>
  59
  60         * v850-dis.c: Add support for e3v5 architecture.
  61         * v850-opc.c: Likewise.
  62
  63 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
  64
  65         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
  66         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
  67         * aarch64-opc.c (operand_general_constraint_met_p): For
  68         AARCH64_MOD_LSL, move the range check on the shift amount before the
  69         alignment check; change to call set_sft_amount_out_of_range_error
  70         instead of set_imm_out_of_range_error.
  71         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
  72         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
  73         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
  74         SIMD_IMM_SFT.
  75
  76 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
  77
  78         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
  79
  80         * i386-init.h: Regenerated.
  81         * i386-tbl.h: Likewise.
  82
  83 2013-01-15  Nick Clifton  <nickc@redhat.com>
  84
  85         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
  86         values.
  87         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
  88
  89 2013-01-14  Will Newton <will.newton@imgtec.com>
  90
  91         * metag-dis.c (REG_WIDTH): Increase to 64.
  92
  93 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
  94
  95         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
  96         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
  97         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
  98         (SH6): Update.
  99         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
 100         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
 101         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
 102         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
 103
 104 2013-01-10  Will Newton <will.newton@imgtec.com>
 105
 106         * Makefile.am: Add Meta.
 107         * configure.in: Add Meta.
 108         * disassemble.c: Add Meta support.
 109         * metag-dis.c: New file.
 110         * Makefile.in: Regenerate.
 111         * configure: Regenerate.
 112
 113 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 114
 115         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
 116         (match_opcode): Rename to cr16_match_opcode.
 117
 118 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
 119
 120         * mips-dis.c: Add names for CP0 registers of r5900.
 121         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
 122         instructions sq and lq.
 123         Add support for MIPS r5900 CPU.
 124         Add support for 128 bit MMI (Multimedia Instructions).
 125         Add support for EE instructions (Emotion Engine).
 126         Disable unsupported floating point instructions (64 bit and
 127         undefined compare operations).
 128         Enable instructions of MIPS ISA IV which are supported by r5900.
 129         Disable 64 bit co processor instructions.
 130         Disable 64 bit multiplication and division instructions.
 131         Disable instructions for co-processor 2 and 3, because these are
 132         not supported (preparation for later VU0 support (Vector Unit)).
 133         Disable cvt.w.s because this behaves like trunc.w.s and the
 134         correct execution can't be ensured on r5900.
 135         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
 136         will confuse less developers and compilers.
 137
 138 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 139
 140         * aarch64-opc.c (aarch64_print_operand): Change to print
 141         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
 142         in comment.
 143         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
 144         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
 145         OP_MOV_IMM_WIDE.
 146
 147 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 148
 149         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
 150         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
 151
 152 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
 153
 154         * i386-gen.c (process_copyright): Update copyright year to 2013.
 155
 156 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 157
 158         * cr16-dis.c (match_opcode,make_instruction): Remove static
 159         declaration.
 160         (dwordU,wordU): Moved typedefs to opcode/cr16.h
 161         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
 162
 163 For older changes see ChangeLog-2012
 164 \f
 165 Copyright (C) 2013 Free Software Foundation, Inc.
 166
 167 Copying and distribution of this file, with or without modification,
 168 are permitted in any medium without royalty provided the copyright
 169 notice and this notice are preserved.
 170
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