1 2008-08-01 H.J. Lu <hongjiu.lu@intel.com>
3 * i386-reg.tbl: Use Dw2Inval on AVX registers.
4 * i386-tbl.h: Regenerated.
6 2008-07-30 Michael J. Eager <eager@eagercon.com>
8 * ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields.
9 * ppc-opc.c (powerpc_operands): Add Xilinx APU related operands.
10 (insert_sprg, PPC405): Use PPC_OPCODE_405.
11 (powerpc_opcodes): Add Xilinx APU related opcodes.
13 2008-07-30 Alan Modra <amodra@bigpond.net.au>
15 * bfin-dis.c, cris-dis.c, i386-dis.c, or32-opc.c: Silence gcc warnings.
17 2008-07-10 Richard Sandiford <rdsandiford@googlemail.com>
19 * mips-dis.c (_print_insn_mips): Use ELF_ST_IS_MIPS16.
21 2008-07-07 Adam Nemet <anemet@caviumnetworks.com>
23 * mips-opc.c (CP): New macro.
24 (mips_builtin_opcodes): Mark c0, c2 and c3 as CP. Add Octeon to the
25 membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0. Add dmfc2 and
26 dmtc2 Octeon instructions.
28 2008-07-07 Stan Shebs <stan@codesourcery.com>
30 * dis-init.c (init_disassemble_info): Init endian_code field.
31 * arm-dis.c (print_insn): Disassemble code according to
32 setting of endian_code.
33 (print_insn_big_arm): Detect when BE8 extension flag has been set.
35 2008-06-30 Richard Sandiford <rdsandiford@googlemail.com>
37 * mips-dis.c (_print_insn_mips): Use bfd_asymbol_flavour to check
40 2008-06-25 Peter Bergner <bergner@vnet.ibm.com>
42 * ppc-dis.c (powerpc_init_dialect): Handle -M464.
43 (print_ppc_disassembler_options): Likewise.
44 * ppc-opc.c (PPC464): Define.
45 (powerpc_opcodes): Add mfdcrux and mtdcrux.
47 2008-06-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
49 * configure: Regenerate.
51 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
53 * ppc-dis.c (print_insn_powerpc): Update prototye to use new
55 (struct dis_private): New.
56 (POWERPC_DIALECT): New define.
57 (powerpc_dialect): Renamed to...
58 (powerpc_init_dialect): This. Update to use ppc_cpu_t and
60 (print_insn_big_powerpc): Update for using structure in
62 (print_insn_little_powerpc): Likewise.
63 (operand_value_powerpc): Change type of dialect param to ppc_cpu_t.
64 (skip_optional_operands): Likewise.
65 (print_insn_powerpc): Likewise. Remove initialization of dialect.
66 * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp,
67 extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe,
68 extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr,
69 extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm,
70 insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe,
71 insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs,
72 insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect
73 param to be of type ppc_cpu_t. Update prototype.
75 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
77 * mips-dis.c (print_insn_args): Handle field descriptors +x, +p,
79 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions
80 baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs,
81 syncw, syncws, vm3mulu, vm0 and vmulu.
83 * mips-dis.c (print_insn_args): Handle field descriptor +Q.
84 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq,
87 2008-05-30 H.J. Lu <hongjiu.lu@intel.com>
89 * i386-opc.tbl: Add vmovd with 64bit operand.
90 * i386-tbl.h: Regenerated.
92 2008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>
94 * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format.
96 2008-05-22 H.J. Lu <hongjiu.lu@intel.com>
98 * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
99 * i386-tbl.h: Regenerated.
101 2008-05-22 H.J. Lu <hongjiu.lu@intel.com>
104 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss
105 into 32bit and 64bit. Remove Reg64|Qword and add
106 IgnoreSize|No_qSuf on 32bit version.
107 * i386-tbl.h: Regenerated.
109 2008-05-21 H.J. Lu <hongjiu.lu@intel.com>
111 * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
112 * i386-tbl.h: Regenerated.
114 2008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
116 * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.
118 2008-05-14 Alan Modra <amodra@bigpond.net.au>
120 * Makefile.am: Run "make dep-am".
121 * Makefile.in: Regenerate.
123 2008-05-02 H.J. Lu <hongjiu.lu@intel.com>
125 * i386-dis.c (MOVBE_Fixup): New.
127 (PREFIX_0F3880): Likewise.
128 (PREFIX_0F3881): Likewise.
129 (PREFIX_0F38F0): Updated.
130 (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
131 PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
132 (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
134 * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
136 (cpu_flags): Add CpuMovbe and CpuEPT.
138 * i386-opc.h (CpuMovbe): New.
141 (i386_cpu_flags): Add cpumovbe and cpuept.
143 * i386-opc.tbl: Add entries for movbe and EPT instructions.
144 * i386-init.h: Regenerated.
145 * i386-tbl.h: Likewise.
147 2008-04-29 Adam Nemet <anemet@caviumnetworks.com>
149 * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
150 the two drem and the two dremu macros.
152 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
154 * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
155 instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
156 cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
157 INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
159 2008-04-25 David S. Miller <davem@davemloft.net>
161 * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
162 instead of %sys_tick_cmpr, as suggested in architecture manuals.
164 2008-04-23 Paolo Bonzini <bonzini@gnu.org>
166 * aclocal.m4: Regenerate.
167 * configure: Regenerate.
169 2008-04-23 David S. Miller <davem@davemloft.net>
171 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
173 (prefetch_table): Add missing values.
175 2008-04-22 H.J. Lu <hongjiu.lu@intel.com>
177 * i386-gen.c (opcode_modifiers): Add NoAVX.
179 * i386-opc.h (NoAVX): New.
181 (i386_opcode_modifier): Add noavx.
183 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
184 instructions which don't have AVX equivalent.
185 * i386-tbl.h: Regenerated.
187 2008-04-18 H.J. Lu <hongjiu.lu@intel.com>
189 * i386-dis.c (OP_VEX_FMA): New.
190 (OP_EX_VexImmW): Likewise.
192 (Vex128FMA): Likewise.
193 (EXVexImmW): Likewise.
194 (get_vex_imm8): Likewise.
195 (OP_EX_VexReg): Likewise.
196 (vex_i4_done): Renamed to ...
198 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
199 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
201 (print_insn): Updated.
202 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
203 (OP_REG_VexI4): Check invalid high registers.
205 2008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
206 Michael Meissner <michael.meissner@amd.com>
208 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
209 * i386-tbl.h: Regenerate from i386-opc.tbl.
211 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
213 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
214 accept Power E500MC instructions.
215 (print_ppc_disassembler_options): Document -Me500mc.
216 * ppc-opc.c (DUIS, DUI, T): New.
217 (XRT, XRTRA): Likewise.
219 (powerpc_opcodes): Add new Power E500MC instructions.
221 2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
223 * s390-dis.c (init_disasm): Evaluate disassembler_options.
224 (print_s390_disassembler_options): New function.
225 * disassemble.c (disassembler_usage): Invoke
226 print_s390_disassembler_options.
228 2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
230 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
231 of local variables used for mnemonic parsing: prefix, suffix and
234 2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
236 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
237 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
238 (s390_crb_extensions): New extensions table.
239 (insertExpandedMnemonic): Handle '$' tag.
240 * s390-opc.txt: Remove conditional jump variants which can now
241 be expanded automatically.
242 Replace '*' tag with '$' in the compare and branch instructions.
244 2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
246 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
247 (PREFIX_VEX_3AXX): Likewis.
249 2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
251 * i386-opc.tbl: Remove 4 extra blank lines.
253 2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
255 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
256 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
257 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
258 * i386-opc.tbl: Likewise.
260 * i386-opc.h (CpuCLMUL): Renamed to ...
263 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
265 * i386-init.h: Regenerated.
267 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
269 * i386-dis.c (OP_E_register): New.
270 (OP_E_memory): Likewise.
272 (OP_EX_Vex): Likewise.
273 (OP_EX_VexW): Likewise.
274 (OP_XMM_Vex): Likewise.
275 (OP_XMM_VexW): Likewise.
276 (OP_REG_VexI4): Likewise.
277 (PCLMUL_Fixup): Likewise.
278 (VEXI4_Fixup): Likewise.
279 (VZERO_Fixup): Likewise.
280 (VCMP_Fixup): Likewise.
281 (VPERMIL2_Fixup): Likewise.
282 (rex_original): Likewise.
283 (rex_ignored): Likewise.
304 (VPERMIL2): Likewise.
305 (xmm_mode): Likewise.
306 (xmmq_mode): Likewise.
307 (ymmq_mode): Likewise.
308 (vex_mode): Likewise.
309 (vex128_mode): Likewise.
310 (vex256_mode): Likewise.
311 (USE_VEX_C4_TABLE): Likewise.
312 (USE_VEX_C5_TABLE): Likewise.
313 (USE_VEX_LEN_TABLE): Likewise.
314 (VEX_C4_TABLE): Likewise.
315 (VEX_C5_TABLE): Likewise.
316 (VEX_LEN_TABLE): Likewise.
317 (REG_VEX_XX): Likewise.
318 (MOD_VEX_XXX): Likewise.
319 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
320 (PREFIX_0F3A44): Likewise.
321 (PREFIX_0F3ADF): Likewise.
322 (PREFIX_VEX_XXX): Likewise.
324 (VEX_OF38): Likewise.
325 (VEX_OF3A): Likewise.
326 (VEX_LEN_XXX): Likewise.
328 (need_vex): Likewise.
329 (need_vex_reg): Likewise.
330 (vex_i4_done): Likewise.
331 (vex_table): Likewise.
332 (vex_len_table): Likewise.
333 (OP_REG_VexI4): Likewise.
334 (vex_cmp_op): Likewise.
335 (pclmul_op): Likewise.
336 (vpermil2_op): Likewise.
339 (PREFIX_0F38F0): Likewise.
340 (PREFIX_0F3A60): Likewise.
341 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
342 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
343 and PREFIX_VEX_XXX entries.
344 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
345 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
347 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
348 Add MOD_VEX_XXX entries.
349 (ckprefix): Initialize rex_original and rex_ignored. Store the
350 REX byte in rex_original.
351 (get_valid_dis386): Handle the implicit prefix in VEX prefix
352 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
353 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
354 calling get_valid_dis386. Use rex_original and rex_ignored when
356 (putop): Handle "XY".
357 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
359 (OP_E_extended): Updated to use OP_E_register and
361 (OP_XMM): Handle VEX.
363 (XMM_Fixup): Likewise.
364 (CMP_Fixup): Use ARRAY_SIZE.
366 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
367 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
368 (operand_type_init): Add OPERAND_TYPE_REGYMM and
369 OPERAND_TYPE_VEX_IMM4.
370 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
371 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
372 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
373 VexImmExt and SSE2AVX.
374 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
376 * i386-opc.h (CpuAVX): New.
378 (CpuCLMUL): Likewise.
389 (Vex3Sources): Likewise.
390 (VexImmExt): Likewise.
394 (Vex_Imm4): Likewise.
395 (Implicit1stXmm0): Likewise.
398 (ByteOkIntel): Likewise.
401 (Unspecified): Likewise.
403 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
404 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
405 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
406 vex3sources, veximmext and sse2avx.
407 (i386_operand_type): Add regymm, ymmword and vex_imm4.
409 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
411 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
413 * i386-init.h: Regenerated.
414 * i386-tbl.h: Likewise.
416 2008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
418 From Robin Getz <robin.getz@analog.com>
419 * bfin-dis.c (bu32): Typedef.
420 (enum const_forms_t): Add c_uimm32 and c_huimm32.
421 (constant_formats[]): Add uimm32 and huimm16.
426 (luimm16_val): Define.
427 (struct saved_state): Define.
428 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
429 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
430 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
432 (decode_LDIMMhalf_0): Print out the whole register value.
434 From Jie Zhang <jie.zhang@analog.com>
435 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
436 multiply and multiply-accumulate to data register instruction.
438 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
439 c_imm32, c_huimm32e): Define.
440 (constant_formats): Add flags for printing decimal, leading spaces, and
442 (comment, parallel): Add global flags in all disassembly.
443 (fmtconst): Take advantage of new flags, and print default in hex.
444 (fmtconst_val): Likewise.
445 (decode_macfunc): Be consistant with spaces, tabs, comments,
446 capitalization in disassembly, fix minor coding style issues.
447 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
448 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
449 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
450 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
451 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
452 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
453 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
454 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
455 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
456 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
457 _print_insn_bfin, print_insn_bfin): Likewise.
459 2008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
461 * aclocal.m4: Regenerate.
462 * configure: Likewise.
463 * Makefile.in: Likewise.
465 2008-03-13 Alan Modra <amodra@bigpond.net.au>
467 * Makefile.am: Run "make dep-am".
468 * Makefile.in: Regenerate.
469 * configure: Regenerate.
471 2008-03-07 Alan Modra <amodra@bigpond.net.au>
473 * ppc-opc.c (powerpc_opcodes): Order and format.
475 2008-03-01 H.J. Lu <hongjiu.lu@intel.com>
477 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
478 * i386-tbl.h: Regenerated.
480 2008-02-23 H.J. Lu <hongjiu.lu@intel.com>
482 * i386-opc.tbl: Disallow 16-bit near indirect branches for
484 * i386-tbl.h: Regenerated.
486 2008-02-21 Jan Beulich <jbeulich@novell.com>
488 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
489 and Fword for far indirect jmp. Allow Reg16 and Word for near
490 indirect jmp on x86-64. Disallow Fword for lcall.
491 * i386-tbl.h: Re-generate.
493 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
495 * cr16-opc.c (cr16_num_optab): Defined
497 2008-02-16 H.J. Lu <hongjiu.lu@intel.com>
499 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
500 * i386-init.h: Regenerated.
502 2008-02-14 Nick Clifton <nickc@redhat.com>
505 * configure.in (SHARED_LIBADD): Select the correct host specific
506 file extension for shared libraries.
507 * configure: Regenerate.
509 2008-02-13 Jan Beulich <jbeulich@novell.com>
511 * i386-opc.h (RegFlat): New.
512 * i386-reg.tbl (flat): Add.
513 * i386-tbl.h: Re-generate.
515 2008-02-13 Jan Beulich <jbeulich@novell.com>
517 * i386-dis.c (a_mode): New.
518 (cond_jump_mode): Adjust.
519 (Ma): Change to a_mode.
520 (intel_operand_size): Handle a_mode.
521 * i386-opc.tbl: Allow Dword and Qword for bound.
522 * i386-tbl.h: Re-generate.
524 2008-02-13 Jan Beulich <jbeulich@novell.com>
526 * i386-gen.c (process_i386_registers): Process new fields.
527 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
528 unsigned char. Add dw2_regnum and Dw2Inval.
529 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
531 * i386-tbl.h: Re-generate.
533 2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
535 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
536 * i386-init.h: Updated.
538 2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
540 * i386-gen.c (cpu_flags): Add CpuXsave.
542 * i386-opc.h (CpuXsave): New.
544 (i386_cpu_flags): Add cpuxsave.
546 * i386-dis.c (MOD_0FAE_REG_4): New.
547 (RM_0F01_REG_2): Likewise.
548 (MOD_0FAE_REG_5): Updated.
549 (RM_0F01_REG_3): Likewise.
550 (reg_table): Use MOD_0FAE_REG_4.
551 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
553 (rm_table): Add RM_0F01_REG_2.
555 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
556 * i386-init.h: Regenerated.
557 * i386-tbl.h: Likewise.
559 2008-02-11 Jan Beulich <jbeulich@novell.com>
561 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
562 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
563 * i386-tbl.h: Re-generate.
565 2008-02-04 H.J. Lu <hongjiu.lu@intel.com>
568 * configure: Regenerated.
570 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
572 * mips-dis.c: Update copyright.
573 (mips_arch_choices): Add Octeon.
574 * mips-opc.c: Update copyright.
576 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
578 2008-01-29 Alan Modra <amodra@bigpond.net.au>
580 * ppc-opc.c: Support optional L form mtmsr.
582 2008-01-24 H.J. Lu <hongjiu.lu@intel.com>
584 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
586 2008-01-23 H.J. Lu <hongjiu.lu@intel.com>
588 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
589 * i386-init.h: Regenerated.
591 2008-01-23 Tristan Gingold <gingold@adacore.com>
593 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
594 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
596 2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
598 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
599 (cpu_flags): Likewise.
601 * i386-opc.h (CpuMMX2): Removed.
604 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
605 * i386-init.h: Regenerated.
606 * i386-tbl.h: Likewise.
608 2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
610 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
612 * i386-init.h: Regenerated.
614 2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
616 * i386-opc.tbl: Use Qword on movddup.
617 * i386-tbl.h: Regenerated.
619 2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
621 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
622 * i386-tbl.h: Regenerated.
624 2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
626 * i386-dis.c (Mx): New.
627 (PREFIX_0FC3): Likewise.
628 (PREFIX_0FC7_REG_6): Updated.
629 (dis386_twobyte): Use PREFIX_0FC3.
630 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
631 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
634 2008-01-14 H.J. Lu <hongjiu.lu@intel.com>
636 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
637 (operand_types): Add Mem.
639 * i386-opc.h (IntelSyntax): New.
640 * i386-opc.h (Mem): New.
642 (Opcode_Modifier_Max): Updated.
643 (i386_opcode_modifier): Add intelsyntax.
644 (i386_operand_type): Add mem.
646 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
649 * i386-reg.tbl: Add size for accumulator.
651 * i386-init.h: Regenerated.
652 * i386-tbl.h: Likewise.
654 2008-01-13 H.J. Lu <hongjiu.lu@intel.com>
656 * i386-opc.h (Byte): Fix a typo.
658 2008-01-12 H.J. Lu <hongjiu.lu@intel.com>
661 * i386-gen.c (operand_type_init): Add Dword to
662 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
663 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
665 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
666 Xmmword, Unspecified and Anysize.
667 (set_bitfield): Make Mmword an alias of Qword. Make Oword
670 * i386-opc.h (CheckSize): Removed.
678 (i386_opcode_modifier): Remove checksize, byte, word, dword,
682 (Unspecified): Likewise.
684 (i386_operand_type): Add byte, word, dword, fword, qword,
685 tbyte xmmword, unspecified and anysize.
687 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
688 Tbyte, Xmmword, Unspecified and Anysize.
690 * i386-reg.tbl: Add size for accumulator.
692 * i386-init.h: Regenerated.
693 * i386-tbl.h: Likewise.
695 2008-01-10 H.J. Lu <hongjiu.lu@intel.com>
697 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
699 (reg_table): Updated.
700 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
701 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
703 2008-01-08 H.J. Lu <hongjiu.lu@intel.com>
705 * i386-gen.c (set_bitfield): Use fail () on error.
707 2008-01-08 H.J. Lu <hongjiu.lu@intel.com>
709 * i386-gen.c (lineno): New.
710 (filename): Likewise.
711 (set_bitfield): Report filename and line numer on error.
712 (process_i386_opcodes): Set filename and update lineno.
713 (process_i386_registers): Likewise.
715 2008-01-05 H.J. Lu <hongjiu.lu@intel.com>
717 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
720 * i386-opc.h (IntelMnemonic): Renamed to ..
722 (Opcode_Modifier_Max): Updated.
723 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
726 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
727 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
728 * i386-tbl.h: Regenerated.
730 2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
732 * i386-gen.c: Update copyright to 2008.
733 * i386-opc.h: Likewise.
734 * i386-opc.tbl: Likewise.
736 * i386-init.h: Regenerated.
737 * i386-tbl.h: Likewise.
739 2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
741 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
742 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
743 * i386-tbl.h: Regenerated.
745 2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
747 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
749 (cpu_flags): Likewise.
751 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
752 (CpuSSE4_2_Or_ABM): Likewise.
754 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
756 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
757 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
758 and CpuPadLock, respectively.
759 * i386-init.h: Regenerated.
760 * i386-tbl.h: Likewise.
762 2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
764 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
766 * i386-opc.h (No_xSuf): Removed.
767 (CheckSize): Updated.
769 * i386-tbl.h: Regenerated.
771 2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
773 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
774 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
776 (cpu_flags): Add CpuSSE4_2_Or_ABM.
778 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
780 (i386_cpu_flags): Add cpusse4_2_or_abm.
782 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
783 CpuABM|CpuSSE4_2 on popcnt.
784 * i386-init.h: Regenerated.
785 * i386-tbl.h: Likewise.
787 2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
789 * i386-opc.h: Update comments.
791 2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
793 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
794 * i386-opc.h: Likewise.
795 * i386-opc.tbl: Likewise.
797 2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
800 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
801 Byte, Word, Dword, QWord and Xmmword.
803 * i386-opc.h (No_xSuf): New.
804 (CheckSize): Likewise.
811 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
812 Dword, QWord and Xmmword.
814 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
816 * i386-tbl.h: Regenerated.
818 2008-01-02 Mark Kettenis <kettenis@gnu.org>
820 * m88k-dis.c (instructions): Fix fcvt.* instructions.
823 For older changes see ChangeLog-2007
829 version-control: never