opcodes/ChangeLog

   1 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
   2
   3         * arc-opc.c (insert_ra_chk): New function.
   4         (insert_rb_chk): Likewise.
   5         (insert_rad): Update text error message.
   6         (insert_rcd): Likewise.
   7         (insert_rhv2): Likewise.
   8         (insert_r0): Likewise.
   9         (insert_r1): Likewise.
  10         (insert_r2): Likewise.
  11         (insert_r3): Likewise.
  12         (insert_sp): Likewise.
  13         (insert_gp): Likewise.
  14         (insert_pcl): Likewise.
  15         (insert_blink): Likewise.
  16         (insert_ilink1): Likewise.
  17         (insert_ilink2): Likewise.
  18         (insert_ras): Likewise.
  19         (insert_rbs): Likewise.
  20         (insert_rcs): Likewise.
  21         (insert_simm3s): Likewise.
  22         (insert_rrange): Likewise.
  23         (insert_fpel): Likewise.
  24         (insert_blinkel): Likewise.
  25         (insert_pcel): Likewise.
  26         (insert_nps_3bit_dst): Likewise.
  27         (insert_nps_3bit_dst_short): Likewise.
  28         (insert_nps_3bit_src2_short): Likewise.
  29         (insert_nps_bitop_size_2b): Likewise.
  30         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
  31         (RA_CHK): Define.
  32         (RB): Adjust.
  33         (RB_CHK): Define.
  34         (RC): Adjust.
  35         * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
  36         * arc-tbl.h (div, divu): All instructions are DIVREM class.
  37         Change first insn argument to check for LP_COUNT usage.
  38         (rem): Likewise.
  39         (ld, ldd): All instructions are LOAD class.  Change first insn
  40         argument to check for LP_COUNT usage.
  41         (st, std): All instructions are STORE class.
  42         (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
  43         Change first insn argument to check for LP_COUNT usage.
  44         (mov): All instructions are MOVE class.  Change first insn
  45         argument to check for LP_COUNT usage.
  46
  47 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
  48
  49         * arc-dis.c (is_compatible_p): Remove function.
  50         (skip_this_opcode): Don't add any decoding class to decode list.
  51         Remove warning.
  52         (find_format_from_table): Go through all opcodes, and warn if we
  53         use a guessed mnemonic.
  54
  55 2016-11-28  Ramiro Polla  <ramiro@hex-rays.com>
  56             Amit Pawar  <amit.pawar@amd.com>
  57
  58         PR binutils/20637
  59         * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
  60         instructions.
  61
  62 2016-11-22  Ambrogino Modigliani  <ambrogino.modigliani@gmail.com>
  63
  64         * configure: Regenerate.
  65
  66 2016-11-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
  67
  68         * sparc-opc.c (HWS_V8): Definition moved from
  69         gas/config/tc-sparc.c.
  70         (HWS_V9): Likewise.
  71         (HWS_VA): Likewise.
  72         (HWS_VB): Likewise.
  73         (HWS_VC): Likewise.
  74         (HWS_VD): Likewise.
  75         (HWS_VE): Likewise.
  76         (HWS_VV): Likewise.
  77         (HWS_VM): Likewise.
  78         (HWS2_VM): Likewise.
  79         (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
  80         existing entries.
  81
  82 2016-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
  83
  84         * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
  85         instructions.
  86
  87 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  88
  89         * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
  90         (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
  91         (aarch64_opcode_table): Add fcmla and fcadd.
  92         (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
  93         * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
  94         * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
  95         * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
  96         * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
  97         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
  98         * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
  99         (operand_general_constraint_met_p): Rotate and index range check.
 100         (aarch64_print_operand): Handle rotate operand.
 101         * aarch64-asm-2.c: Regenerate.
 102         * aarch64-dis-2.c: Likewise.
 103         * aarch64-opc-2.c: Likewise.
 104
 105 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 106
 107         * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
 108         * aarch64-asm-2.c: Regenerate.
 109         * aarch64-dis-2.c: Regenerate.
 110         * aarch64-opc-2.c: Regenerate.
 111
 112 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 113
 114         * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
 115         (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
 116         * aarch64-asm-2.c: Regenerate.
 117         * aarch64-dis-2.c: Regenerate.
 118         * aarch64-opc-2.c: Regenerate.
 119
 120 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 121
 122         * aarch64-tbl.h (QL_X1NIL): New.
 123         (arch64_opcode_table): Add ldraa, ldrab.
 124         (AARCH64_OPERANDS): Add "ADDR_SIMM10".
 125         * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
 126         * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
 127         * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
 128         * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
 129         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
 130         * aarch64-opc.c (fields): Add data for FLD_S_simm10.
 131         (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
 132         (aarch64_print_operand): Likewise.
 133         * aarch64-asm-2.c: Regenerate.
 134         * aarch64-dis-2.c: Regenerate.
 135         * aarch64-opc-2.c: Regenerate.
 136
 137 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 138
 139         * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
 140         brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
 141         * aarch64-asm-2.c: Regenerate.
 142         * aarch64-dis-2.c: Regenerate.
 143         * aarch64-opc-2.c: Regenerate.
 144
 145 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 146
 147         * aarch64-tbl.h (arch64_opcode_table): Add pacga.
 148         (AARCH64_OPERANDS): Add Rm_SP.
 149         * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
 150         * aarch64-asm-2.c: Regenerate.
 151         * aarch64-dis-2.c: Regenerate.
 152         * aarch64-opc-2.c: Regenerate.
 153
 154 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 155
 156         * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
 157         autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
 158         autdzb, xpaci, xpacd.
 159         * aarch64-asm-2.c: Regenerate.
 160         * aarch64-dis-2.c: Regenerate.
 161         * aarch64-opc-2.c: Regenerate.
 162
 163 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 164
 165         * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
 166         apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
 167         apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
 168         (aarch64_sys_reg_supported_p): Add feature test for new registers.
 169
 170 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 171
 172         * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
 173         (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
 174         autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
 175         autibsp.
 176         * aarch64-asm-2.c: Regenerate.
 177         * aarch64-dis-2.c: Regenerate.
 178
 179 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 180
 181         * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
 182
 183 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 184
 185         PR binutils/20799
 186         * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
 187         * i386-dis.c (EdqwS): Removed.
 188         (dqw_swap_mode): Likewise.
 189         (intel_operand_size): Don't check dqw_swap_mode.
 190         (OP_E_register): Likewise.
 191         (OP_E_memory): Likewise.
 192         (OP_G): Likewise.
 193         (OP_EX): Likewise.
 194         * i386-opc.tbl: Remove "S" from EVEX vpextrw.
 195         * i386-tbl.h: Regerated.
 196
 197 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 198
 199         * i386-opc.tbl: Merge AVX512F vmovq.
 200         * i386-tbl.h: Regerated.
 201
 202 2016-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 203
 204         PR binutils/20701
 205         * i386-dis.c (THREE_BYTE_0F7A): Removed.
 206         (dis386_twobyte): Don't use THREE_BYTE_0F7A.
 207         (three_byte_table): Remove THREE_BYTE_0F7A.
 208
 209 2016-11-07  H.J. Lu  <hongjiu.lu@intel.com>
 210
 211         PR binutils/20775
 212         * i386-dis.c (FGRPd9_2): Replace 0 with 1.
 213         (FGRPd9_4): Replace 1 with 2.
 214         (FGRPd9_5): Replace 2 with 3.
 215         (FGRPd9_6): Replace 3 with 4.
 216         (FGRPd9_7): Replace 4 with 5.
 217         (FGRPda_5): Replace 5 with 6.
 218         (FGRPdb_4): Replace 6 with 7.
 219         (FGRPde_3): Replace 7 with 8.
 220         (FGRPdf_4): Replace 8 with 9.
 221         (fgrps): Add an entry for Bad_Opcode.
 222
 223 2016-11-04  Andrew Burgess  <andrew.burgess@embecosm.com>
 224
 225         * arc-opc.c (arc_flag_operands): Add F_DI14.
 226         (arc_flag_classes): Add C_DI14.
 227         * arc-nps400-tbl.h: Add new exc instructions.
 228
 229 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 230
 231         * arc-dis.c (arc_insn_length): Return length 8 for instructions with
 232         major opcode 0xa.
 233         * arc-nps-400-tbl.h: Add dcmac instruction.
 234         * arc-opc.c (arc_operands): Added operands for dcmac instruction.
 235         (insert_nps_rbdouble_64): Added.
 236         (extract_nps_rbdouble_64): Added.
 237         (insert_nps_proto_size): Added.
 238         (extract_nps_proto_size): Added.
 239
 240 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 241
 242         * arc-dis.c (struct arc_operand_iterator): Remove all fields
 243         relating to long instruction processing, add new limm field.
 244         (OPCODE): Rename to...
 245         (OPCODE_32BIT_INSN): ...this.
 246         (OPCODE_AC): Delete.
 247         (skip_this_opcode): Handle different instruction lengths, update
 248         macro name.
 249         (special_flag_p): Update parameter type.
 250         (find_format_from_table): Update for more instruction lengths.
 251         (find_format_long_instructions): Delete.
 252         (find_format): Update for more instruction lengths.
 253         (arc_insn_length): Likewise.
 254         (extract_operand_value): Update for more instruction lengths.
 255         (operand_iterator_next): Remove code relating to long
 256         instructions.
 257         (arc_opcode_to_insn_type): New function.
 258         (print_insn_arc):Update for more instructions lengths.
 259         * arc-ext.c (extInstruction_t): Change argument type.
 260         * arc-ext.h (extInstruction_t): Change argument type.
 261         * arc-fxi.h: Change type unsigned to unsigned long long
 262         extensively throughout.
 263         * arc-nps400-tbl.h: Add long instructions taken from
 264         arc_long_opcodes table in arc-opc.c.
 265         * arc-opc.c: Update parameter types on insert/extract handlers.
 266         (arc_long_opcodes): Delete.
 267         (arc_num_long_opcodes): Delete.
 268         (arc_opcode_len): Update for more instruction lengths.
 269
 270 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 271
 272         * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
 273
 274 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 275
 276         * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
 277         with arc_opcode_len.
 278         (find_format_long_instructions): Likewise.
 279         * arc-opc.c (arc_opcode_len): New function.
 280
 281 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 282
 283         * arc-nps400-tbl.h: Fix some instruction masks.
 284
 285 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 286
 287         * i386-dis.c (REG_82): Removed.
 288         (X86_64_82_REG_0): Likewise.
 289         (X86_64_82_REG_1): Likewise.
 290         (X86_64_82_REG_2): Likewise.
 291         (X86_64_82_REG_3): Likewise.
 292         (X86_64_82_REG_4): Likewise.
 293         (X86_64_82_REG_5): Likewise.
 294         (X86_64_82_REG_6): Likewise.
 295         (X86_64_82_REG_7): Likewise.
 296         (X86_64_82): New.
 297         (dis386): Use X86_64_82 instead of REG_82.
 298         (reg_table): Remove REG_82.
 299         (x86_64_table): Add X86_64_82.  Remove X86_64_82_REG_0,
 300         X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
 301         X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
 302         X86_64_82_REG_7.
 303
 304 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 305
 306         PR binutils/20754
 307         * i386-dis.c (REG_82): New.
 308         (X86_64_82_REG_0): Likewise.
 309         (X86_64_82_REG_1): Likewise.
 310         (X86_64_82_REG_2): Likewise.
 311         (X86_64_82_REG_3): Likewise.
 312         (X86_64_82_REG_4): Likewise.
 313         (X86_64_82_REG_5): Likewise.
 314         (X86_64_82_REG_6): Likewise.
 315         (X86_64_82_REG_7): Likewise.
 316         (dis386): Use REG_82.
 317         (reg_table): Add REG_82.
 318         (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
 319         X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
 320         X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
 321
 322 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 323
 324         * i386-dis.c (REG_82): Renamed to ...
 325         (REG_83): This.
 326         (dis386): Updated.
 327         (reg_table): Likewise.
 328
 329 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 330
 331         * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
 332         * i386-dis-evex.h (evex_table): Updated.
 333         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
 334         CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 335         (cpu_flags): Add CpuAVX512_4VNNIW.
 336         * i386-opc.h (enum): (AVX512_4VNNIW): New.
 337         (i386_cpu_flags): Add cpuavx512_4vnniw.
 338         * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
 339         * i386-init.h: Regenerate.
 340         * i386-tbl.h: Ditto.
 341
 342 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 343
 344         * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
 345         PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
 346         * i386-dis-evex.h (evex_table): Updated.
 347         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
 348         CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 349         (cpu_flags): Add CpuAVX512_4FMAPS.
 350         (opcode_modifiers): Add ImplicitQuadGroup modifier.
 351         * i386-opc.h (AVX512_4FMAP): New.
 352         (i386_cpu_flags): Add cpuavx512_4fmaps.
 353         (ImplicitQuadGroup): New.
 354         (i386_opcode_modifier): Add implicitquadgroup.
 355         * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
 356         * i386-init.h: Regenerate.
 357         * i386-tbl.h: Ditto.
 358
 359 2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
 360             Andrew Waterman <andrew@sifive.com>
 361
 362         Add support for RISC-V architecture.
 363         * configure.ac: Add entry for bfd_riscv_arch.
 364         * configure: Regenerate.
 365         * disassemble.c (disassembler): Add support for riscv.
 366         (disassembler_usage): Likewise.
 367         * riscv-dis.c: New file.
 368         * riscv-opc.c: New file.
 369
 370 2016-10-21  H.J. Lu  <hongjiu.lu@intel.com>
 371
 372         * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
 373         (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
 374         (rm_table): Update the RM_0FAE_REG_7 entry.
 375         * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
 376         (cpu_flags): Remove CpuPCOMMIT.
 377         * i386-opc.h (CpuPCOMMIT): Removed.
 378         (i386_cpu_flags): Remove cpupcommit.
 379         * i386-opc.tbl: Remove pcommit.
 380         * i386-init.h: Regenerated.
 381         * i386-tbl.h: Likewise.
 382
 383 2016-10-20  H.J. Lu  <hongjiu.lu@intel.com>
 384
 385         PR binutis/20705
 386         * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
 387         the highest bit in VEX.vvvv for the 3-byte VEX prefix in
 388         32-bit mode.  Don't check vex.register_specifier in 32-bit
 389         mode.
 390         (OP_VEX): Check for invalid mask registers.
 391
 392 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 393
 394         PR binutis/20699
 395         * i386-dis.c (OP_E_memory): Check addr32flag in stead of
 396         sizeflag.
 397
 398 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 399
 400         PR binutis/20704
 401         * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
 402
 403 2016-10-18  Maciej W. Rozycki  <macro@imgtec.com>
 404
 405         * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
 406         local variable to `index_regno'.
 407
 408 2016-10-17  Cupertino Miranda  <cmiranda@synopsys.com>
 409
 410         * arc-tbl.h: Removed any "inv.+" instructions from the table.
 411
 412 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
 413
 414         * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
 415         usage on ISA basis.
 416
 417 2016-10-11  Jiong Wang  <jiong.wang@arm.com>
 418
 419         PR target/20666
 420         * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
 421
 422 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
 423
 424         PR target/20667
 425         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
 426         available.
 427
 428 2016-10-07  Alan Modra  <amodra@gmail.com>
 429
 430         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
 431
 432 2016-10-06  Alan Modra  <amodra@gmail.com>
 433
 434         * aarch64-opc.c: Spell fall through comments consistently.
 435         * i386-dis.c: Likewise.
 436         * aarch64-dis.c: Add missing fall through comments.
 437         * aarch64-opc.c: Likewise.
 438         * arc-dis.c: Likewise.
 439         * arm-dis.c: Likewise.
 440         * i386-dis.c: Likewise.
 441         * m68k-dis.c: Likewise.
 442         * mep-asm.c: Likewise.
 443         * ns32k-dis.c: Likewise.
 444         * sh-dis.c: Likewise.
 445         * tic4x-dis.c: Likewise.
 446         * tic6x-dis.c: Likewise.
 447         * vax-dis.c: Likewise.
 448
 449 2016-10-06  Alan Modra  <amodra@gmail.com>
 450
 451         * arc-ext.c (create_map): Add missing break.
 452         * msp430-decode.opc (encode_as): Likewise.
 453         * msp430-decode.c: Regenerate.
 454
 455 2016-10-06  Alan Modra  <amodra@gmail.com>
 456
 457         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
 458         * crx-dis.c (print_insn_crx): Likewise.
 459
 460 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 461
 462         PR binutils/20657
 463         * i386-dis.c (putop): Don't assign alt twice.
 464
 465 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
 466
 467         PR target/20553
 468         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
 469
 470 2016-09-29  Alan Modra  <amodra@gmail.com>
 471
 472         * ppc-opc.c (L): Make compulsory.
 473         (LOPT): New, optional form of L.
 474         (HTM_R): Define as LOPT.
 475         (L0, L1): Delete.
 476         (L32OPT): New, optional for 32-bit L.
 477         (L2OPT): New, 2-bit L for dcbf.
 478         (SVC_LEC): Update.
 479         (L2): Define.
 480         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
 481         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
 482         <dcbf>: Use L2OPT.
 483         <tlbiel, tlbie>: Use LOPT.
 484         <wclr, wclrall>: Use L2.
 485
 486 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
 487
 488         * Makefile.in: Regenerate.
 489         * configure: Likewise.
 490
 491 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 492
 493         * arc-ext-tbl.h (EXTINSN2OPF): Define.
 494         (EXTINSN2OP): Use EXTINSN2OPF.
 495         (bspeekm, bspop, modapp): New extension instructions.
 496         * arc-opc.c (F_DNZ_ND): Define.
 497         (F_DNZ_D): Likewise.
 498         (F_SIZEB1): Changed.
 499         (C_DNZ_D): Define.
 500         (C_HARD): Changed.
 501         * arc-tbl.h (dbnz): New instruction.
 502         (prealloc): Allow it for ARC EM.
 503         (xbfu): Likewise.
 504
 505 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 506
 507         * aarch64-opc.c (print_immediate_offset_address): Print spaces
 508         after commas in addresses.
 509         (aarch64_print_operand): Likewise.
 510
 511 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 512
 513         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
 514         rather than "should be" or "expected to be" in error messages.
 515
 516 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 517
 518         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
 519         (print_mnemonic_name): ...here.
 520         (print_comment): New function.
 521         (print_aarch64_insn): Call it.
 522         * aarch64-opc.c (aarch64_conds): Add SVE names.
 523         (aarch64_print_operand): Print alternative condition names in
 524         a comment.
 525
 526 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 527
 528         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 529         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 530         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 531         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 532         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 533         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 534         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 535         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 536         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 537         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 538         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 539         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 540         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 541         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 542         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 543         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 544         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 545         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 546         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 547         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 548         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 549         (aarch64_feature_sve): New variable.
 550         (SVE): New macro.
 551         (_SVE_INSN): Likewise.
 552         (aarch64_opcode_table): Add SVE instructions.
 553         * aarch64-opc.h (extract_fields): Declare.
 554         * aarch64-opc-2.c: Regenerate.
 555         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 556         * aarch64-asm-2.c: Regenerate.
 557         * aarch64-dis.c (extract_fields): Make global.
 558         (do_misc_decoding): Handle the new SVE aarch64_ops.
 559         * aarch64-dis-2.c: Regenerate.
 560
 561 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 562
 563         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 564         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 565         aarch64_field_kinds.
 566         * aarch64-opc.c (fields): Add corresponding entries.
 567         * aarch64-asm.c (aarch64_get_variant): New function.
 568         (aarch64_encode_variant_using_iclass): Likewise.
 569         (aarch64_opcode_encode): Call it.
 570         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 571         (aarch64_opcode_decode): Call it.
 572
 573 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 574
 575         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 576         and FP register operands.
 577         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 578         (FLD_SVE_Vn): New aarch64_field_kinds.
 579         * aarch64-opc.c (fields): Add corresponding entries.
 580         (aarch64_print_operand): Handle the new SVE core and FP register
 581         operands.
 582         * aarch64-opc-2.c: Regenerate.
 583         * aarch64-asm-2.c: Likewise.
 584         * aarch64-dis-2.c: Likewise.
 585
 586 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 587
 588         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 589         immediate operands.
 590         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 591         * aarch64-opc.c (fields): Add corresponding entry.
 592         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 593         operands.
 594         (aarch64_print_operand): Likewise.
 595         * aarch64-opc-2.c: Regenerate.
 596         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 597         (ins_sve_float_zero_one): New inserters.
 598         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 599         (aarch64_ins_sve_float_half_two): Likewise.
 600         (aarch64_ins_sve_float_zero_one): Likewise.
 601         * aarch64-asm-2.c: Regenerate.
 602         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 603         (ext_sve_float_zero_one): New extractors.
 604         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 605         (aarch64_ext_sve_float_half_two): Likewise.
 606         (aarch64_ext_sve_float_zero_one): Likewise.
 607         * aarch64-dis-2.c: Regenerate.
 608
 609 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 610
 611         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 612         integer immediate operands.
 613         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 614         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 615         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 616         * aarch64-opc.c (fields): Add corresponding entries.
 617         (operand_general_constraint_met_p): Handle the new SVE integer
 618         immediate operands.
 619         (aarch64_print_operand): Likewise.
 620         (aarch64_sve_dupm_mov_immediate_p): New function.
 621         * aarch64-opc-2.c: Regenerate.
 622         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 623         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 624         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 625         (aarch64_ins_limm): ...here.
 626         (aarch64_ins_inv_limm): New function.
 627         (aarch64_ins_sve_aimm): Likewise.
 628         (aarch64_ins_sve_asimm): Likewise.
 629         (aarch64_ins_sve_limm_mov): Likewise.
 630         (aarch64_ins_sve_shlimm): Likewise.
 631         (aarch64_ins_sve_shrimm): Likewise.
 632         * aarch64-asm-2.c: Regenerate.
 633         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 634         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 635         * aarch64-dis.c (decode_limm): New function, split out from...
 636         (aarch64_ext_limm): ...here.
 637         (aarch64_ext_inv_limm): New function.
 638         (decode_sve_aimm): Likewise.
 639         (aarch64_ext_sve_aimm): Likewise.
 640         (aarch64_ext_sve_asimm): Likewise.
 641         (aarch64_ext_sve_limm_mov): Likewise.
 642         (aarch64_top_bit): Likewise.
 643         (aarch64_ext_sve_shlimm): Likewise.
 644         (aarch64_ext_sve_shrimm): Likewise.
 645         * aarch64-dis-2.c: Regenerate.
 646
 647 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 648
 649         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 650         operands.
 651         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 652         the AARCH64_MOD_MUL_VL entry.
 653         (value_aligned_p): Cope with non-power-of-two alignments.
 654         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 655         (print_immediate_offset_address): Likewise.
 656         (aarch64_print_operand): Likewise.
 657         * aarch64-opc-2.c: Regenerate.
 658         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 659         (ins_sve_addr_ri_s9xvl): New inserters.
 660         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 661         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 662         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 663         * aarch64-asm-2.c: Regenerate.
 664         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 665         (ext_sve_addr_ri_s9xvl): New extractors.
 666         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 667         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 668         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 669         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 670         * aarch64-dis-2.c: Regenerate.
 671
 672 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 673
 674         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 675         address operands.
 676         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 677         (FLD_SVE_xs_22): New aarch64_field_kinds.
 678         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 679         (get_operand_specific_data): New function.
 680         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 681         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 682         (operand_general_constraint_met_p): Handle the new SVE address
 683         operands.
 684         (sve_reg): New array.
 685         (get_addr_sve_reg_name): New function.
 686         (aarch64_print_operand): Handle the new SVE address operands.
 687         * aarch64-opc-2.c: Regenerate.
 688         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 689         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 690         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 691         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 692         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 693         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 694         (aarch64_ins_sve_addr_zi_u5): Likewise.
 695         (aarch64_ins_sve_addr_zz): Likewise.
 696         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 697         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 698         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 699         * aarch64-asm-2.c: Regenerate.
 700         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 701         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 702         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 703         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 704         (aarch64_ext_sve_addr_ri_u6): Likewise.
 705         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 706         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 707         (aarch64_ext_sve_addr_zi_u5): Likewise.
 708         (aarch64_ext_sve_addr_zz): Likewise.
 709         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 710         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 711         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 712         * aarch64-dis-2.c: Regenerate.
 713
 714 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 715
 716         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 717         AARCH64_OPND_SVE_PATTERN_SCALED.
 718         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 719         * aarch64-opc.c (fields): Add a corresponding entry.
 720         (set_multiplier_out_of_range_error): New function.
 721         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 722         (operand_general_constraint_met_p): Handle
 723         AARCH64_OPND_SVE_PATTERN_SCALED.
 724         (print_register_offset_address): Use PRIi64 to print the
 725         shift amount.
 726         (aarch64_print_operand): Likewise.  Handle
 727         AARCH64_OPND_SVE_PATTERN_SCALED.
 728         * aarch64-opc-2.c: Regenerate.
 729         * aarch64-asm.h (ins_sve_scale): New inserter.
 730         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 731         * aarch64-asm-2.c: Regenerate.
 732         * aarch64-dis.h (ext_sve_scale): New inserter.
 733         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 734         * aarch64-dis-2.c: Regenerate.
 735
 736 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 737
 738         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 739         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 740         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 741         (FLD_SVE_prfop): Likewise.
 742         * aarch64-opc.c: Include libiberty.h.
 743         (aarch64_sve_pattern_array): New variable.
 744         (aarch64_sve_prfop_array): Likewise.
 745         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 746         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 747         AARCH64_OPND_SVE_PRFOP.
 748         * aarch64-asm-2.c: Regenerate.
 749         * aarch64-dis-2.c: Likewise.
 750         * aarch64-opc-2.c: Likewise.
 751
 752 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 753
 754         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 755         AARCH64_OPND_QLF_P_[ZM].
 756         (aarch64_print_operand): Print /z and /m where appropriate.
 757
 758 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 759
 760         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 761         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 762         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 763         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 764         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 765         * aarch64-opc.c (fields): Add corresponding entries here.
 766         (operand_general_constraint_met_p): Check that SVE register lists
 767         have the correct length.  Check the ranges of SVE index registers.
 768         Check for cases where p8-p15 are used in 3-bit predicate fields.
 769         (aarch64_print_operand): Handle the new SVE operands.
 770         * aarch64-opc-2.c: Regenerate.
 771         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 772         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 773         (aarch64_ins_sve_reglist): Likewise.
 774         * aarch64-asm-2.c: Regenerate.
 775         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 776         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 777         (aarch64_ext_sve_reglist): Likewise.
 778         * aarch64-dis-2.c: Regenerate.
 779
 780 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 781
 782         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 783         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 784         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 785         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 786         tied operands.
 787
 788 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 789
 790         * aarch64-opc.c (get_offset_int_reg_name): New function.
 791         (print_immediate_offset_address): Likewise.
 792         (print_register_offset_address): Take the base and offset
 793         registers as parameters.
 794         (aarch64_print_operand): Update caller accordingly.  Use
 795         print_immediate_offset_address.
 796
 797 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 798
 799         * aarch64-opc.c (BANK): New macro.
 800         (R32, R64): Take a register number as argument
 801         (int_reg): Use BANK.
 802
 803 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 804
 805         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 806         (aarch64_print_operand): Update accordingly.
 807
 808 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 809
 810         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 811         for FPIMM.
 812         * aarch64-asm.h (ins_fpimm): New inserter.
 813         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 814         * aarch64-asm-2.c: Regenerate.
 815         * aarch64-dis.h (ext_fpimm): New extractor.
 816         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 817         (aarch64_ext_fpimm): New function.
 818         * aarch64-dis-2.c: Regenerate.
 819
 820 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 821
 822         * aarch64-asm.c: Include libiberty.h.
 823         (insert_fields): New function.
 824         (aarch64_ins_imm): Use it.
 825         * aarch64-dis.c (extract_fields): New function.
 826         (aarch64_ext_imm): Use it.
 827
 828 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 829
 830         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 831         with an esize parameter.
 832         (operand_general_constraint_met_p): Update accordingly.
 833         Fix misindented code.
 834         * aarch64-asm.c (aarch64_ins_limm): Update call to
 835         aarch64_logical_immediate_p.
 836
 837 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 838
 839         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 840
 841 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 842
 843         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 844
 845 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 846
 847         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 848
 849 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 850
 851         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 852         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 853         xor3>: Delete mnemonics.
 854         <cp_abort>: Rename mnemonic from ...
 855         <cpabort>: ...to this.
 856         <setb>: Change to a X form instruction.
 857         <sync>: Change to 1 operand form.
 858         <copy>: Delete mnemonic.
 859         <copy_first>: Rename mnemonic from ...
 860         <copy>: ...to this.
 861         <paste, paste.>: Delete mnemonics.
 862         <paste_last>: Rename mnemonic from ...
 863         <paste.>: ...to this.
 864
 865 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 866
 867         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 868
 869 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 870
 871         * s390-mkopc.c (main): Support alternate arch strings.
 872
 873 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 874
 875         * s390-opc.txt: Fix kmctr instruction type.
 876
 877 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 878
 879         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 880         * i386-init.h: Regenerated.
 881
 882 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 883
 884         * opcodes/arc-dis.c (print_insn_arc): Changed.
 885
 886 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 887
 888         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 889         camellia_fl.
 890
 891 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 892
 893         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 894         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 895         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 896
 897 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 898
 899         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 900         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 901         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 902         PREFIX_MOD_3_0FAE_REG_4.
 903         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 904         PREFIX_MOD_3_0FAE_REG_4.
 905         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 906         (cpu_flags): Add CpuPTWRITE.
 907         * i386-opc.h (CpuPTWRITE): New.
 908         (i386_cpu_flags): Add cpuptwrite.
 909         * i386-opc.tbl: Add ptwrite instruction.
 910         * i386-init.h: Regenerated.
 911         * i386-tbl.h: Likewise.
 912
 913 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 914
 915         * arc-dis.h: Wrap around in extern "C".
 916
 917 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 918
 919         * aarch64-tbl.h (V8_2_INSN): New macro.
 920         (aarch64_opcode_table): Use it.
 921
 922 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 923
 924         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 925         CORE_INSN, __FP_INSN and SIMD_INSN.
 926
 927 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 928
 929         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 930         (aarch64_opcode_table): Update uses accordingly.
 931
 932 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 933         Kwok Cheung Yeung  <kcy@codesourcery.com>
 934
 935         opcodes/
 936         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 937         'e_cmplwi' to 'e_cmpli' instead.
 938         (OPVUPRT, OPVUPRT_MASK): Define.
 939         (powerpc_opcodes): Add E200Z4 insns.
 940         (vle_opcodes): Add context save/restore insns.
 941
 942 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 943
 944         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 945         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 946         "j".
 947
 948 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 949
 950         * arc-nps400-tbl.h: Change block comments to GNU format.
 951         * arc-dis.c: Add new globals addrtypenames,
 952         addrtypenames_max, and addtypeunknown.
 953         (get_addrtype): New function.
 954         (print_insn_arc): Print colons and address types when
 955         required.
 956         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 957         define insert and extract functions for all address types.
 958         (arc_operands): Add operands for colon and all address
 959         types.
 960         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 961         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 962         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 963         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 964         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 965         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 966
 967 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 968
 969         * configure: Regenerated.
 970
 971 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 972
 973         * arc-dis.c (skipclass): New structure.
 974         (decodelist): New variable.
 975         (is_compatible_p): New function.
 976         (new_element): Likewise.
 977         (skip_class_p): Likewise.
 978         (find_format_from_table): Use skip_class_p function.
 979         (find_format): Decode first the extension instructions.
 980         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 981         e_flags.
 982         (parse_option): New function.
 983         (parse_disassembler_options): Likewise.
 984         (print_arc_disassembler_options): Likewise.
 985         (print_insn_arc): Use parse_disassembler_options function.  Proper
 986         select ARCv2 cpu variant.
 987         * disassemble.c (disassembler_usage): Add ARC disassembler
 988         options.
 989
 990 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 991
 992         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 993         annotation from the "nal" entry and reorder it beyond "bltzal".
 994
 995 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 996
 997         * sparc-opc.c (ldtxa): New macro.
 998         (sparc_opcodes): Use the macro defined above to add entries for
 999         the LDTXA instructions.
1000         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1001         instruction.
1002
1003 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
1004
1005         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1006         and "jmpc".
1007
1008 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1009
1010         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1011         (movzb): Adjust to cover all permitted suffixes.
1012         (movzw): New.
1013         * i386-tbl.h: Re-generate.
1014
1015 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1016
1017         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1018         (lgdt): Remove Tbyte from non-64-bit variant.
1019         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1020         xsaves64, xsavec64): Remove Disp16.
1021         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1022         Remove Disp32S from non-64-bit variants. Remove Disp16 from
1023         64-bit variants.
1024         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1025         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1026         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1027         64-bit variants.
1028         * i386-tbl.h: Re-generate.
1029
1030 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1031
1032         * i386-opc.tbl (xlat): Remove RepPrefixOk.
1033         * i386-tbl.h: Re-generate.
1034
1035 2016-06-30  Yao Qi  <yao.qi@linaro.org>
1036
1037         * arm-dis.c (print_insn): Fix typo in comment.
1038
1039 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
1040
1041         * aarch64-opc.c (operand_general_constraint_met_p): Check the
1042         range of ldst_elemlist operands.
1043         (print_register_list): Use PRIi64 to print the index.
1044         (aarch64_print_operand): Likewise.
1045
1046 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1047
1048         * mcore-opc.h: Remove sentinal.
1049         * mcore-dis.c (print_insn_mcore): Adjust.
1050
1051 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
1052
1053         * arc-opc.c: Correct description of availability of NPS400
1054         features.
1055
1056 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
1057
1058         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1059         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1060         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1061         xor3>: New mnemonics.
1062         <setb>: Change to a VX form instruction.
1063         (insert_sh6): Add support for rldixor.
1064         (extract_sh6): Likewise.
1065
1066 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1067
1068         * arc-ext.h: Wrap in extern C.
1069
1070 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
1071
1072         * arc-dis.c (arc_insn_length): Add comment on instruction length.
1073         Use same method for determining instruction length on ARC700 and
1074         NPS-400.
1075         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1076         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1077         with the NPS400 subclass.
1078         * arc-opc.c: Likewise.
1079
1080 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1081
1082         * sparc-opc.c (rdasr): New macro.
1083         (wrasr): Likewise.
1084         (rdpr): Likewise.
1085         (wrpr): Likewise.
1086         (rdhpr): Likewise.
1087         (wrhpr): Likewise.
1088         (sparc_opcodes): Use the macros above to fix and expand the
1089         definition of read/write instructions from/to
1090         asr/privileged/hyperprivileged instructions.
1091         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1092         %hva_mask_nz.  Prefer softint_set and softint_clear over
1093         set_softint and clear_softint.
1094         (print_insn_sparc): Support %ver in Rd.
1095
1096 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1097
1098         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1099         architecture according to the hardware capabilities they require.
1100
1101 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1102
1103         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1104         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1105         bfd_mach_sparc_v9{c,d,e,v,m}.
1106         * sparc-opc.c (MASK_V9C): Define.
1107         (MASK_V9D): Likewise.
1108         (MASK_V9E): Likewise.
1109         (MASK_V9V): Likewise.
1110         (MASK_V9M): Likewise.
1111         (v6): Add MASK_V9{C,D,E,V,M}.
1112         (v6notlet): Likewise.
1113         (v7): Likewise.
1114         (v8): Likewise.
1115         (v9): Likewise.
1116         (v9andleon): Likewise.
1117         (v9a): Likewise.
1118         (v9b): Likewise.
1119         (v9c): Define.
1120         (v9d): Likewise.
1121         (v9e): Likewise.
1122         (v9v): Likewise.
1123         (v9m): Likewise.
1124         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1125
1126 2016-06-15  Nick Clifton  <nickc@redhat.com>
1127
1128         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1129         constants to match expected behaviour.
1130         (nds32_parse_opcode): Likewise.  Also for whitespace.
1131
1132 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
1133
1134         * arc-opc.c (extract_rhv1): Extract value from insn.
1135
1136 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1137
1138         * arc-nps400-tbl.h: Add ldbit instruction.
1139         * arc-opc.c: Add flag classes required for ldbit.
1140
1141 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1142
1143         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1144         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1145         support the above instructions.
1146
1147 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1148
1149         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1150         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1151         csma, cbba, zncv, and hofs.
1152         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1153         support the above instructions.
1154
1155 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1156
1157         * arc-nps400-tbl.h: Add andab and orab instructions.
1158
1159 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1160
1161         * arc-nps400-tbl.h: Add addl-like instructions.
1162
1163 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1164
1165         * arc-nps400-tbl.h: Add mxb and imxb instructions.
1166
1167 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1168
1169         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1170         instructions.
1171
1172 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1173
1174         * s390-dis.c (option_use_insn_len_bits_p): New file scope
1175         variable.
1176         (init_disasm): Handle new command line option "insnlength".
1177         (print_s390_disassembler_options): Mention new option in help
1178         output.
1179         (print_insn_s390): Use the encoded insn length when dumping
1180         unknown instructions.
1181
1182 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
1183
1184         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1185          to the address and set as symbol address for LDS/ STS immediate operands.
1186
1187 2016-06-07  Alan Modra  <amodra@gmail.com>
1188
1189         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
1190         cpu for "vle" to e500.
1191         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1192         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1193         (PPCNONE): Delete, substitute throughout.
1194         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
1195         except for major opcode 4 and 31.
1196         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1197
1198 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
1199
1200         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1201         ARM_EXT_RAS in relevant entries.
1202
1203 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
1204
1205         PR binutils/20196
1206         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1207         opcodes for E6500.
1208
1209 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
1210
1211         PR binutis/18386
1212         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1213         (indir_v_mode): New.
1214         Add comments for '&'.
1215         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1216         (putop): Handle '&'.
1217         (intel_operand_size): Handle indir_v_mode.
1218         (OP_E_register): Likewise.
1219         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
1220         64-bit indirect call/jmp for AMD64.
1221         * i386-tbl.h: Regenerated
1222
1223 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1224
1225         * arc-dis.c (struct arc_operand_iterator): New structure.
1226         (find_format_from_table): All the old content from find_format,
1227         with some minor adjustments, and parameter renaming.
1228         (find_format_long_instructions): New function.
1229         (find_format): Rewritten.
1230         (arc_insn_length): Add LSB parameter.
1231         (extract_operand_value): New function.
1232         (operand_iterator_next): New function.
1233         (print_insn_arc): Use new functions to find opcode, and iterator
1234         over operands.
1235         * arc-opc.c (insert_nps_3bit_dst_short): New function.
1236         (extract_nps_3bit_dst_short): New function.
1237         (insert_nps_3bit_src2_short): New function.
1238         (extract_nps_3bit_src2_short): New function.
1239         (insert_nps_bitop1_size): New function.
1240         (extract_nps_bitop1_size): New function.
1241         (insert_nps_bitop2_size): New function.
1242         (extract_nps_bitop2_size): New function.
1243         (insert_nps_bitop_mod4_msb): New function.
1244         (extract_nps_bitop_mod4_msb): New function.
1245         (insert_nps_bitop_mod4_lsb): New function.
1246         (extract_nps_bitop_mod4_lsb): New function.
1247         (insert_nps_bitop_dst_pos3_pos4): New function.
1248         (extract_nps_bitop_dst_pos3_pos4): New function.
1249         (insert_nps_bitop_ins_ext): New function.
1250         (extract_nps_bitop_ins_ext): New function.
1251         (arc_operands): Add new operands.
1252         (arc_long_opcodes): New global array.
1253         (arc_num_long_opcodes): New global.
1254         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1255
1256 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1257
1258         * nds32-asm.h: Add extern "C".
1259         * sh-opc.h: Likewise.
1260
1261 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
1262
1263         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1264         0,b,limm to the rflt instruction.
1265
1266 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1267
1268         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1269         constant.
1270
1271 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
1272
1273         PR gas/20145
1274         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1275         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1276         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1277         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1278         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1279         * i386-init.h: Regenerated.
1280
1281 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1282
1283         PR gas/20145
1284         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
1285         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
1286         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1287         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1288         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
1289         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1290         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1291         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
1292         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1293         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1294         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
1295         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
1296         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
1297         CpuRegMask for AVX512.
1298         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1299         and CpuRegMask.
1300         (set_bitfield_from_cpu_flag_init): New function.
1301         (set_bitfield): Remove const on f.  Call
1302         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1303         * i386-opc.h (CpuRegMMX): New.
1304         (CpuRegXMM): Likewise.
1305         (CpuRegYMM): Likewise.
1306         (CpuRegZMM): Likewise.
1307         (CpuRegMask): Likewise.
1308         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1309         and cpuregmask.
1310         * i386-init.h: Regenerated.
1311         * i386-tbl.h: Likewise.
1312
1313 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1314
1315         PR gas/20154
1316         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1317         (opcode_modifiers): Add AMD64 and Intel64.
1318         (main): Properly verify CpuMax.
1319         * i386-opc.h (CpuAMD64): Removed.
1320         (CpuIntel64): Likewise.
1321         (CpuMax): Set to CpuNo64.
1322         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1323         (AMD64): New.
1324         (Intel64): Likewise.
1325         (i386_opcode_modifier): Add amd64 and intel64.
1326         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1327         on call and jmp.
1328         * i386-init.h: Regenerated.
1329         * i386-tbl.h: Likewise.
1330
1331 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1332
1333         PR gas/20154
1334         * i386-gen.c (main): Fail if CpuMax is incorrect.
1335         * i386-opc.h (CpuMax): Set to CpuIntel64.
1336         * i386-tbl.h: Regenerated.
1337
1338 2016-05-27  Nick Clifton  <nickc@redhat.com>
1339
1340         PR target/20150
1341         * msp430-dis.c (msp430dis_read_two_bytes): New function.
1342         (msp430dis_opcode_unsigned): New function.
1343         (msp430dis_opcode_signed): New function.
1344         (msp430_singleoperand): Use the new opcode reading functions.
1345         Only disassenmble bytes if they were successfully read.
1346         (msp430_doubleoperand): Likewise.
1347         (msp430_branchinstr): Likewise.
1348         (msp430x_callx_instr): Likewise.
1349         (print_insn_msp430): Check that it is safe to read bytes before
1350         attempting disassembly.  Use the new opcode reading functions.
1351
1352 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
1353
1354         * ppc-opc.c (CY): New define.  Document it.
1355         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1356
1357 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1358
1359         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1360         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1361         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
1362         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1363         CPU_ANY_AVX_FLAGS.
1364         * i386-init.h: Regenerated.
1365
1366 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1367
1368         PR gas/20141
1369         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1370         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1371         * i386-init.h: Regenerated.
1372
1373 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1374
1375         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1376         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
1377         * i386-init.h: Regenerated.
1378
1379 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1380
1381         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1382         information.
1383         (print_insn_arc): Set insn_type information.
1384         * arc-opc.c (C_CC): Add F_CLASS_COND.
1385         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1386         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1387         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1388         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1389         (brne, brne_s, jeq_s, jne_s): Likewise.
1390
1391 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1392
1393         * arc-tbl.h (neg): New instruction variant.
1394
1395 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
1396
1397         * arc-dis.c (find_format, find_format, get_auxreg)
1398         (print_insn_arc): Changed.
1399         * arc-ext.h (INSERT_XOP): Likewise.
1400
1401 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1402
1403         * tic54x-dis.c (sprint_mmr): Adjust.
1404         * tic54x-opc.c: Likewise.
1405
1406 2016-05-19  Alan Modra  <amodra@gmail.com>
1407
1408         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1409
1410 2016-05-19  Alan Modra  <amodra@gmail.com>
1411
1412         * ppc-opc.c: Formatting.
1413         (NSISIGNOPT): Define.
1414         (powerpc_opcodes <subis>): Use NSISIGNOPT.
1415
1416 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
1417
1418         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1419         replacing references to `micromips_ase' throughout.
1420         (_print_insn_mips): Don't use file-level microMIPS annotation to
1421         determine the disassembly mode with the symbol table.
1422
1423 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1424
1425         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1426
1427 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1428
1429         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1430         mips64r6.
1431         * mips-opc.c (D34): New macro.
1432         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1433
1434 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1435
1436         * i386-dis.c (prefix_table): Add RDPID instruction.
1437         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1438         (cpu_flags): Add RDPID bitfield.
1439         * i386-opc.h (enum): Add RDPID element.
1440         (i386_cpu_flags): Add RDPID field.
1441         * i386-opc.tbl: Add RDPID instruction.
1442         * i386-init.h: Regenerate.
1443         * i386-tbl.h: Regenerate.
1444
1445 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1446
1447         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1448         branch type of a symbol.
1449         (print_insn): Likewise.
1450
1451 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1452
1453         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1454         Mainline Security Extensions instructions.
1455         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1456         Extensions instructions.
1457         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1458         instructions.
1459         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1460         special registers.
1461
1462 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1463
1464         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1465
1466 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1467
1468         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1469         (arcExtMap_genOpcode): Likewise.
1470         * arc-opc.c (arg_32bit_rc): Define new variable.
1471         (arg_32bit_u6): Likewise.
1472         (arg_32bit_limm): Likewise.
1473
1474 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1475
1476         * aarch64-gen.c (VERIFIER): Define.
1477         * aarch64-opc.c (VERIFIER): Define.
1478         (verify_ldpsw): Use static linkage.
1479         * aarch64-opc.h (verify_ldpsw): Remove.
1480         * aarch64-tbl.h: Use VERIFIER for verifiers.
1481
1482 2016-04-28  Nick Clifton  <nickc@redhat.com>
1483
1484         PR target/19722
1485         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1486         * aarch64-opc.c (verify_ldpsw): New function.
1487         * aarch64-opc.h (verify_ldpsw): New prototype.
1488         * aarch64-tbl.h: Add initialiser for verifier field.
1489         (LDPSW): Set verifier to verify_ldpsw.
1490
1491 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1492
1493         PR binutils/19983
1494         PR binutils/19984
1495         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1496         smaller than address size.
1497
1498 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1499
1500         * alpha-dis.c: Regenerate.
1501         * crx-dis.c: Likewise.
1502         * disassemble.c: Likewise.
1503         * epiphany-opc.c: Likewise.
1504         * fr30-opc.c: Likewise.
1505         * frv-opc.c: Likewise.
1506         * ip2k-opc.c: Likewise.
1507         * iq2000-opc.c: Likewise.
1508         * lm32-opc.c: Likewise.
1509         * lm32-opinst.c: Likewise.
1510         * m32c-opc.c: Likewise.
1511         * m32r-opc.c: Likewise.
1512         * m32r-opinst.c: Likewise.
1513         * mep-opc.c: Likewise.
1514         * mt-opc.c: Likewise.
1515         * or1k-opc.c: Likewise.
1516         * or1k-opinst.c: Likewise.
1517         * tic80-opc.c: Likewise.
1518         * xc16x-opc.c: Likewise.
1519         * xstormy16-opc.c: Likewise.
1520
1521 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1522
1523         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1524         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1525         calcsd, and calcxd instructions.
1526         * arc-opc.c (insert_nps_bitop_size): Delete.
1527         (extract_nps_bitop_size): Delete.
1528         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1529         (extract_nps_qcmp_m3): Define.
1530         (extract_nps_qcmp_m2): Define.
1531         (extract_nps_qcmp_m1): Define.
1532         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1533         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1534         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1535         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1536         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1537         NPS_QCMP_M3.
1538
1539 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1540
1541         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1542
1543 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1544
1545         * Makefile.in: Regenerated with automake 1.11.6.
1546         * aclocal.m4: Likewise.
1547
1548 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1549
1550         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1551         instructions.
1552         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1553         (extract_nps_cmem_uimm16): New function.
1554         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1555
1556 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1557
1558         * arc-dis.c (arc_insn_length): New function.
1559         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1560         (find_format): Change insnLen parameter to unsigned.
1561
1562 2016-04-13  Nick Clifton  <nickc@redhat.com>
1563
1564         PR target/19937
1565         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1566         the LD.B and LD.BU instructions.
1567
1568 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1569
1570         * arc-dis.c (find_format): Check for extension flags.
1571         (print_flags): New function.
1572         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1573         .extAuxRegister.
1574         * arc-ext.c (arcExtMap_coreRegName): Use
1575         LAST_EXTENSION_CORE_REGISTER.
1576         (arcExtMap_coreReadWrite): Likewise.
1577         (dump_ARC_extmap): Update printing.
1578         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1579         (arc_aux_regs): Add cpu field.
1580         * arc-regs.h: Add cpu field, lower case name aux registers.
1581
1582 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1583
1584         * arc-tbl.h: Add rtsc, sleep with no arguments.
1585
1586 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1587
1588         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1589         Initialize.
1590         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1591         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1592         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1593         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1594         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1595         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1596         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1597         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1598         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1599         (arc_opcode arc_opcodes): Null terminate the array.
1600         (arc_num_opcodes): Remove.
1601         * arc-ext.h (INSERT_XOP): Define.
1602         (extInstruction_t): Likewise.
1603         (arcExtMap_instName): Delete.
1604         (arcExtMap_insn): New function.
1605         (arcExtMap_genOpcode): Likewise.
1606         * arc-ext.c (ExtInstruction): Remove.
1607         (create_map): Zero initialize instruction fields.
1608         (arcExtMap_instName): Remove.
1609         (arcExtMap_insn): New function.
1610         (dump_ARC_extmap): More info while debuging.
1611         (arcExtMap_genOpcode): New function.
1612         * arc-dis.c (find_format): New function.
1613         (print_insn_arc): Use find_format.
1614         (arc_get_disassembler): Enable dump_ARC_extmap only when
1615         debugging.
1616
1617 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1618
1619         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1620         instruction bits out.
1621
1622 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1623
1624         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1625         * arc-opc.c (arc_flag_operands): Add new flags.
1626         (arc_flag_classes): Add new classes.
1627
1628 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1629
1630         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1631
1632 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1633
1634         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1635         encode1, rflt, crc16, and crc32 instructions.
1636         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1637         (arc_flag_classes): Add C_NPS_R.
1638         (insert_nps_bitop_size_2b): New function.
1639         (extract_nps_bitop_size_2b): Likewise.
1640         (insert_nps_bitop_uimm8): Likewise.
1641         (extract_nps_bitop_uimm8): Likewise.
1642         (arc_operands): Add new operand entries.
1643
1644 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1645
1646         * arc-regs.h: Add a new subclass field.  Add double assist
1647         accumulator register values.
1648         * arc-tbl.h: Use DPA subclass to mark the double assist
1649         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1650         * arc-opc.c (RSP): Define instead of SP.
1651         (arc_aux_regs): Add the subclass field.
1652
1653 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1654
1655         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1656
1657 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1658
1659         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1660         NPS_R_SRC1.
1661
1662 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1663
1664         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1665         issues.  No functional changes.
1666
1667 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1668
1669         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1670         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1671         (RTT): Remove duplicate.
1672         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1673         (PCT_CONFIG*): Remove.
1674         (D1L, D1H, D2H, D2L): Define.
1675
1676 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1677
1678         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1679
1680 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1681
1682         * arc-tbl.h (invld07): Remove.
1683         * arc-ext-tbl.h: New file.
1684         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1685         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1686
1687 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1688
1689         Fix -Wstack-usage warnings.
1690         * aarch64-dis.c (print_operands): Substitute size.
1691         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1692
1693 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1694
1695         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1696         to get a proper diagnostic when an invalid ASR register is used.
1697
1698 2016-03-22  Nick Clifton  <nickc@redhat.com>
1699
1700         * configure: Regenerate.
1701
1702 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1703
1704         * arc-nps400-tbl.h: New file.
1705         * arc-opc.c: Add top level comment.
1706         (insert_nps_3bit_dst): New function.
1707         (extract_nps_3bit_dst): New function.
1708         (insert_nps_3bit_src2): New function.
1709         (extract_nps_3bit_src2): New function.
1710         (insert_nps_bitop_size): New function.
1711         (extract_nps_bitop_size): New function.
1712         (arc_flag_operands): Add nps400 entries.
1713         (arc_flag_classes): Add nps400 entries.
1714         (arc_operands): Add nps400 entries.
1715         (arc_opcodes): Add nps400 include.
1716
1717 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1718
1719         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1720         the new class enum values.
1721
1722 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1723
1724         * arc-dis.c (print_insn_arc): Handle nps400.
1725
1726 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1727
1728         * arc-opc.c (BASE): Delete.
1729
1730 2016-03-18  Nick Clifton  <nickc@redhat.com>
1731
1732         PR target/19721
1733         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1734         of MOV insn that aliases an ORR insn.
1735
1736 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1737
1738         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1739
1740 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1741
1742         * mcore-opc.h: Add const qualifiers.
1743         * microblaze-opc.h (struct op_code_struct): Likewise.
1744         * sh-opc.h: Likewise.
1745         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1746         (tic4x_print_op): Likewise.
1747
1748 2016-03-02  Alan Modra  <amodra@gmail.com>
1749
1750         * or1k-desc.h: Regenerate.
1751         * fr30-ibld.c: Regenerate.
1752         * rl78-decode.c: Regenerate.
1753
1754 2016-03-01  Nick Clifton  <nickc@redhat.com>
1755
1756         PR target/19747
1757         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1758
1759 2016-02-24  Renlin Li  <renlin.li@arm.com>
1760
1761         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1762         (print_insn_coprocessor): Support fp16 instructions.
1763
1764 2016-02-24  Renlin Li  <renlin.li@arm.com>
1765
1766         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1767         vminnm, vrint(mpna).
1768
1769 2016-02-24  Renlin Li  <renlin.li@arm.com>
1770
1771         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1772         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1773
1774 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1775
1776         * i386-dis.c (print_insn): Parenthesize expression to prevent
1777         truncated addresses.
1778         (OP_J): Likewise.
1779
1780 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1781             Janek van Oirschot  <jvanoirs@synopsys.com>
1782
1783         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1784         variable.
1785
1786 2016-02-04  Nick Clifton  <nickc@redhat.com>
1787
1788         PR target/19561
1789         * msp430-dis.c (print_insn_msp430): Add a special case for
1790         decoding an RRC instruction with the ZC bit set in the extension
1791         word.
1792
1793 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1794
1795         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1796         * epiphany-ibld.c: Regenerate.
1797         * fr30-ibld.c: Regenerate.
1798         * frv-ibld.c: Regenerate.
1799         * ip2k-ibld.c: Regenerate.
1800         * iq2000-ibld.c: Regenerate.
1801         * lm32-ibld.c: Regenerate.
1802         * m32c-ibld.c: Regenerate.
1803         * m32r-ibld.c: Regenerate.
1804         * mep-ibld.c: Regenerate.
1805         * mt-ibld.c: Regenerate.
1806         * or1k-ibld.c: Regenerate.
1807         * xc16x-ibld.c: Regenerate.
1808         * xstormy16-ibld.c: Regenerate.
1809
1810 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1811
1812         * epiphany-dis.c: Regenerated from latest cpu files.
1813
1814 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1815
1816         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1817         test bit.
1818
1819 2016-01-25  Renlin Li  <renlin.li@arm.com>
1820
1821         * arm-dis.c (mapping_symbol_for_insn): New function.
1822         (find_ifthen_state): Call mapping_symbol_for_insn().
1823
1824 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1825
1826         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1827         of MSR UAO immediate operand.
1828
1829 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1830
1831         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1832         instruction support.
1833
1834 2016-01-17  Alan Modra  <amodra@gmail.com>
1835
1836         * configure: Regenerate.
1837
1838 2016-01-14  Nick Clifton  <nickc@redhat.com>
1839
1840         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1841         instructions that can support stack pointer operations.
1842         * rl78-decode.c: Regenerate.
1843         * rl78-dis.c: Fix display of stack pointer in MOVW based
1844         instructions.
1845
1846 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1847
1848         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1849         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1850         erxtatus_el1 and erxaddr_el1.
1851
1852 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1853
1854         * arm-dis.c (arm_opcodes): Add "esb".
1855         (thumb_opcodes): Likewise.
1856
1857 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1858
1859         * ppc-opc.c <xscmpnedp>: Delete.
1860         <xvcmpnedp>: Likewise.
1861         <xvcmpnedp.>: Likewise.
1862         <xvcmpnesp>: Likewise.
1863         <xvcmpnesp.>: Likewise.
1864
1865 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1866
1867         PR gas/13050
1868         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1869         addition to ISA_A.
1870
1871 2016-01-01  Alan Modra  <amodra@gmail.com>
1872
1873         Update year range in copyright notice of all files.
1874
1875 For older changes see ChangeLog-2015
1876 \f
1877 Copyright (C) 2016 Free Software Foundation, Inc.
1878
1879 Copying and distribution of this file, with or without modification,
1880 are permitted in any medium without royalty provided the copyright
1881 notice and this notice are preserved.
1882
1883 Local Variables:
1884 mode: change-log
1885 left-margin: 8
1886 fill-column: 74
1887 version-control: never
1888 End: