opcodes/ChangeLog

   1 2013-10-13  Sandra Loosemore  <sandra@codesourcery.com>
   2
   3         * nios2-opc.c (nios2_builtin_reg): Use "sstatus" rather than "ba"
   4         as the primary name of r30.
   5
   6 2013-10-12  Jan Beulich <jbeulich@suse.com>
   7
   8         * i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
   9         default case.
  10         (OP_E_register): Move v_bnd_mode alongside m_mode.
  11         * i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants.
  12         Drop Reg16 and Disp16. Add NoRex64.
  13         (bndmk, bndmov, bndldx, bndstx): Drop Disp16.
  14         * i386-tbl.h: Re-generate.
  15
  16 2013-10-10  Sean Keys <skeys@ipdatasys.com>
  17
  18         * xgate-opc.c (xgate_opcode): Remove short_hand field from opcode
  19         table.
  20         * xgate-dis.c (print_insn): Refactor to work with table change.
  21
  22 2013-10-10  Roland McGrath  <mcgrathr@google.com>
  23
  24         * i386-dis.c (oappend_maybe_intel): New function.
  25         (OP_ST, OP_STi, append_seg, OP_I, OP_I64, OP_sI, OP_ESreg): Use it.
  26         (OP_C, OP_T, CMP_Fixup, OP_EX_VexImmW): Likewise.
  27         (VCMP_Fixup, VPCMP_Fixup, PCLMUL_Fixup): Likewise.
  28
  29         * cr16-opc.c (REG): Cast NAME to 'reg' enum type to suppress
  30         possible compiler warnings when the union's initializer is
  31         actually meant for the 'preg' enum typed member.
  32         * crx-opc.c (REG): Likewise.
  33
  34         * v850-dis.c (v850_cacheop_codes, v850_prefop_codes):
  35         Remove duplicate const qualifier.
  36
  37 2013-10-08  Jan Beulich <jbeulich@suse.com>
  38
  39         * i386-opc.tbl (invlpg): Use Anysize instead of Unspecified.
  40         (clflush): Use Anysize instead of Byte|Unspecified.
  41         (prefetch*): Likewise.
  42         * i386-tbl.h: Re-generate.
  43
  44 2013-10-07  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
  45
  46         * micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0.
  47
  48 2013-09-30  H.J. Lu  <hongjiu.lu@intel.com>
  49
  50         * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.
  51         * i386-init.h: Regenerated.
  52
  53 2013-09-30  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
  54
  55         * i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS.
  56         * i386-init.h: Regenerated.
  57
  58 2013-09-20  Alan Modra  <amodra@gmail.com>
  59
  60         * configure: Regenerate.
  61
  62 2013-09-17  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
  63
  64         * s390-opc.txt (clih): Make the immediate unsigned.
  65
  66 2013-09-04  Roland McGrath  <mcgrathr@google.com>
  67
  68         PR gas/15914
  69         * arm-dis.c (arm_opcodes): Add udf.
  70         (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
  71         (thumb32_opcodes): Add udf.w.
  72         (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
  73
  74 2013-09-02  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  75
  76         * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
  77         For the load fp integer instructions only the suppression flag was
  78         new with z196 version.
  79
  80 2013-08-28  Nick Clifton  <nickc@redhat.com>
  81
  82         * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
  83         immediate is not suitable for the 32-bit ABI.
  84
  85 2013-08-23  Maciej W. Rozycki  <macro@codesourcery.com>
  86
  87         * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
  88         replacing NODS.
  89
  90 2013-08-23  Yuri Chornoivan  <yurchor@ukr.net>
  91
  92         PR binutils/15834
  93         * aarch64-asm.c: Fix typos.
  94         * aarch64-dis.c: Likewise.
  95         * msp430-dis.c: Likewise.
  96
  97 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
  98
  99         * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
 100         macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
 101         Use +H rather than +C for the real "dext".
 102         * mips-opc.c (mips_builtin_opcodes): Likewise.
 103
 104 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
 105
 106         * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
 107         * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
 108         and OPTIONAL_MAPPED_REG.
 109         * mips-opc.c (decode_mips_operand): Likewise.
 110         * mips16-opc.c (decode_mips16_operand): Likewise.
 111         * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
 112
 113 2013-08-19  H.J. Lu  <hongjiu.lu@intel.com>
 114
 115         * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
 116         (PREFIX_EVEX_0F3A3F): Likewise.
 117         * i386-dis-evex.h (evex_table): Updated.
 118
 119 2013-08-06  Jürgen Urban  <JuergenUrban@gmx.de>
 120
 121         * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
 122         VCLIPW.
 123
 124 2013-08-05  Eric Botcazou  <ebotcazou@adacore.com>
 125             Konrad Eisele  <konrad@gaisler.com>
 126
 127         * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
 128         bfd_mach_sparc.
 129         * sparc-opc.c (MASK_LEON): Define.
 130         (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
 131         (letandleon): New macro.
 132         (v9andleon): Likewise.
 133         (sparc_opc): Add leon.
 134         (umac): Enable for letandleon.
 135         (smac): Likewise.
 136         (casa): Enable for v9andleon.
 137         (cas): Likewise.
 138         (casl): Likewise.
 139
 140 2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
 141             Richard Sandiford  <rdsandiford@googlemail.com>
 142
 143         * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
 144         OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
 145         (print_vu0_channel): New function.
 146         (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
 147         (print_insn_args): Handle '#'.
 148         (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
 149         * mips-opc.c (mips_vu0_channel_mask): New constant.
 150         (decode_mips_operand): Handle new VU0 operand types.
 151         (VU0, VU0CH): New macros.
 152         (mips_builtin_opcodes): Add VU0 opcodes.  Use "+7" rather than "E"
 153         for LQC2 and SQC2.  Use "+9" rather than "G" for EE CFC2 and CTC2.
 154         Use "+6" rather than "G" for QMFC2 and QMTC2.
 155
 156 2013-08-03  Richard Sandiford  <rdsandiford@googlemail.com>
 157
 158         * mips-formats.h (PCREL): Reorder parameters and update the definition
 159         to match new mips_pcrel_operand layout.
 160         (JUMP, JALX, BRANCH): Update accordingly.
 161         * mips16-opc.c (decode_mips16_operand): Likewise.
 162
 163 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 164
 165         * micromips-opc.c (WR_s): Delete.
 166
 167 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 168
 169         * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
 170         New macros.
 171         (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
 172         (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
 173         (mips_builtin_opcodes): Use the new position-based read-write flags
 174         instead of field-based ones.  Use UDI for "udi..." instructions.
 175         * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
 176         New macros.
 177         (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
 178         (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
 179         (WR_SP, RD_16): New macros.
 180         (RD_SP): Redefine as an INSN2_* flag.
 181         (MOD_SP): Redefine in terms of RD_SP and WR_SP.
 182         (mips16_opcodes): Use the new position-based read-write flags
 183         instead of field-based ones.  Use RD_16 for "nop".  Move RD_SP to
 184         pinfo2 field.
 185         * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
 186         New macros.
 187         (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
 188         (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
 189         (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
 190         (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
 191         (micromips_opcodes): Use the new position-based read-write flags
 192         instead of field-based ones.
 193         * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
 194         (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
 195         of field-based flags.
 196
 197 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 198
 199         * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
 200         (WR_SP): Replace with...
 201         (MOD_SP): ...this.
 202         (mips16_opcodes): Update accordingly.
 203         * mips-dis.c (print_insn_mips16): Likewise.
 204
 205 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 206
 207         * mips16-opc.c (mips16_opcodes): Reformat.
 208
 209 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 210
 211         * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
 212         for operands that are hard-coded to $0.
 213         * micromips-opc.c (micromips_opcodes): Likewise.
 214
 215 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 216
 217         * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
 218         for the single-operand forms of JALR and JALR.HB.
 219         * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
 220         and JALRS.HB.
 221
 222 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 223
 224         * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
 225         instructions.  Fix them to use WR_MACC instead of WR_CC and
 226         add missing RD_MACCs.
 227
 228 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 229
 230         * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
 231
 232 2013-07-29  Peter Bergner <bergner@vnet.ibm.com>
 233
 234         * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
 235
 236 2013-07-26  Sergey Guriev  <sergey.s.guriev@intel.com>
 237             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 238             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 239             Sergey Lega  <sergey.s.lega@intel.com>
 240             Anna Tikhonova  <anna.tikhonova@intel.com>
 241             Ilya Tocar  <ilya.tocar@intel.com>
 242             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 243             Ilya Verbin  <ilya.verbin@intel.com>
 244             Kirill Yukhin  <kirill.yukhin@intel.com>
 245             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 246
 247         * i386-dis-evex.h: New.
 248         * i386-dis.c (OP_Rounding): New.
 249         (VPCMP_Fixup): New.
 250         (OP_Mask): New.
 251         (Rdq): New.
 252         (XMxmmq): New.
 253         (EXdScalarS): New.
 254         (EXymm): New.
 255         (EXEvexHalfBcstXmmq): New.
 256         (EXxmm_mdq): New.
 257         (EXEvexXGscat): New.
 258         (EXEvexXNoBcst): New.
 259         (VPCMP): New.
 260         (EXxEVexR): New.
 261         (EXxEVexS): New.
 262         (XMask): New.
 263         (MaskG): New.
 264         (MaskE): New.
 265         (MaskR): New.
 266         (MaskVex): New.
 267         (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
 268         evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
 269         evex_rounding_mode, evex_sae_mode, mask_mode.
 270         (USE_EVEX_TABLE): New.
 271         (EVEX_TABLE): New.
 272         (EVEX enum): New.
 273         (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
 274         REG_EVEX_0F38C7.
 275         (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
 276         MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
 277         MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
 278         MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 279         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,  MOD_EVEX_0F38C7_REG_5,
 280         MOD_EVEX_0F38C7_REG_6.
 281         (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 282         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
 283         PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 284         PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
 285         PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
 286         PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
 287         PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
 288         PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
 289         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
 290         PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
 291         PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
 292         PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
 293         PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
 294         PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
 295         PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
 296         PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
 297         PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
 298         PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
 299         PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
 300         PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
 301         PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
 302         PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
 303         PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
 304         PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
 305         PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
 306         PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
 307         PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
 308         PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
 309         PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
 310         PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
 311         PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
 312         PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
 313         PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
 314         PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
 315         PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
 316         PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
 317         PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
 318         PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
 319         PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
 320         PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
 321         PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
 322         PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
 323         PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
 324         PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
 325         PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
 326         PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
 327         PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
 328         PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
 329         PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
 330         PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
 331         PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
 332         PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
 333         PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
 334         PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
 335         PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
 336         PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
 337         PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
 338         PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
 339         PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
 340         PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
 341         PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
 342         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
 343         PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
 344         PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
 345         PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
 346         PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
 347         PREFIX_EVEX_0F3A00,  PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
 348         PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
 349         PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
 350         PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
 351         PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
 352         PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
 353         PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
 354         PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
 355         PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
 356         PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
 357         PREFIX_EVEX_0F3A55.
 358         (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
 359         VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
 360         VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
 361         VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
 362         VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
 363         VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
 364         VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
 365         VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
 366         VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
 367         VEX_W_0F3A32_P_2_LEN_0.
 368         (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
 369         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
 370         EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
 371         EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
 372         EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
 373         EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 374         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
 375         EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
 376         EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 377         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
 378         EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 379         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
 380         EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
 381         EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
 382         EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
 383         EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
 384         EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
 385         EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
 386         EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
 387         EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
 388         EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
 389         EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
 390         EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
 391         EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
 392         EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
 393         EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
 394         EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
 395         EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
 396         EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
 397         EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
 398         EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
 399         EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
 400         EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
 401         EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
 402         EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
 403         EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
 404         EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
 405         EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
 406         EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
 407         EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
 408         EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
 409         EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
 410         EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
 411         EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
 412         EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
 413         EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
 414         EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
 415         EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
 416         EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
 417         EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
 418         EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
 419         EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
 420         EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
 421         EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
 422         (struct vex): Add fields evex, r, v, mask_register_specifier,
 423         zeroing, ll, b.
 424         (intel_names_xmm): Add upper 16 registers.
 425         (att_names_xmm): Ditto.
 426         (intel_names_ymm): Ditto.
 427         (att_names_ymm): Ditto.
 428         (names_zmm): New.
 429         (intel_names_zmm): Ditto.
 430         (att_names_zmm): Ditto.
 431         (names_mask): Ditto.
 432         (intel_names_mask): Ditto.
 433         (att_names_mask): Ditto.
 434         (names_rounding): Ditto.
 435         (names_broadcast): Ditto.
 436         (x86_64_table): Add escape to evex-table.
 437         (reg_table): Include reg_table evex-entries from
 438         i386-dis-evex.h.  Fix prefetchwt1 instruction.
 439         (prefix_table): Add entries for new instructions.
 440         (vex_table): Ditto.
 441         (vex_len_table): Ditto.
 442         (vex_w_table): Ditto.
 443         (mod_table): Ditto.
 444         (get_valid_dis386): Properly handle new instructions.
 445         (print_insn): Handle zmm and mask registers, print mask operand.
 446         (intel_operand_size): Support EVEX, new modes and sizes.
 447         (OP_E_register): Handle new modes.
 448         (OP_E_memory): Ditto.
 449         (OP_G): Ditto.
 450         (OP_XMM): Ditto.
 451         (OP_EX): Ditto.
 452         (OP_VEX): Ditto.
 453         * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
 454         CPU_ANY_AVX_FLAGS.  Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
 455         CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 456         (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
 457         CpuAVX512PF and CpuVREX.
 458         (operand_type_init): Add OPERAND_TYPE_REGZMM,
 459         OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
 460         (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
 461         StaticRounding, SAE, Disp8MemShift, NoDefMask.
 462         (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
 463         * i386-init.h: Regenerate.
 464         * i386-opc.h (CpuAVX512F): New.
 465         (CpuAVX512CD): New.
 466         (CpuAVX512ER): New.
 467         (CpuAVX512PF): New.
 468         (CpuVREX): New.
 469         (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
 470         cpuavx512pf and cpuvrex fields.
 471         (VecSIB): Add VecSIB512.
 472         (EVex): New.
 473         (Masking): New.
 474         (VecESize): New.
 475         (Broadcast): New.
 476         (StaticRounding): New.
 477         (SAE): New.
 478         (Disp8MemShift): New.
 479         (NoDefMask): New.
 480         (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
 481         staticrounding, sae, disp8memshift and nodefmask.
 482         (RegZMM): New.
 483         (Zmmword): Ditto.
 484         (Vec_Disp8): Ditto.
 485         (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
 486         fields.
 487         (RegVRex): New.
 488         * i386-opc.tbl: Add AVX512 instructions.
 489         * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
 490         registers, mask registers.
 491         * i386-tbl.h: Regenerate.
 492
 493 2013-07-25  Aaro Koskinen  <aaro.koskinen@iki.fi>
 494
 495         PR gas/15220
 496         * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
 497         Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
 498
 499 2013-07-25  Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 500
 501         * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
 502         PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
 503         PREFIX_0F3ACC.
 504         (prefix_table): Updated.
 505         (three_byte_table): Likewise.
 506         * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
 507         (cpu_flags): Add CpuSHA.
 508         (i386_cpu_flags): Add cpusha.
 509         * i386-init.h: Regenerate.
 510         * i386-opc.h (CpuSHA): New.
 511         (CpuUnused): Restored.
 512         (i386_cpu_flags): Add cpusha.
 513         * i386-opc.tbl: Add SHA instructions.
 514         * i386-tbl.h: Regenerate.
 515
 516 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
 517             Kirill Yukhin  <kirill.yukhin@intel.com>
 518             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 519
 520         * i386-dis.c (BND_Fixup): New.
 521         (Ebnd): New.
 522         (Ev_bnd): New.
 523         (Gbnd): New.
 524         (BND): New.
 525         (v_bnd_mode): New.
 526         (bnd_mode): New.
 527         (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
 528         MOD_0F1B_PREFIX_1.
 529         (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
 530         (dis tables): Replace XX with BND for near branch and call
 531         instructions.
 532         (prefix_table): Add new entries.
 533         (mod_table): Likewise.
 534         (names_bnd): New.
 535         (intel_names_bnd): New.
 536         (att_names_bnd): New.
 537         (BND_PREFIX): New.
 538         (prefix_name): Handle BND_PREFIX.
 539         (print_insn): Initialize names_bnd.
 540         (intel_operand_size): Handle new modes.
 541         (OP_E_register): Likewise.
 542         (OP_E_memory): Likewise.
 543         (OP_G): Likewise.
 544         * i386-gen.c (cpu_flag_init): Add CpuMPX.
 545         (cpu_flags): Add CpuMPX.
 546         (operand_type_init): Add RegBND.
 547         (opcode_modifiers): Add BNDPrefixOk.
 548         (operand_types): Add RegBND.
 549         * i386-init.h: Regenerate.
 550         * i386-opc.h (CpuMPX): New.
 551         (CpuUnused): Comment out.
 552         (i386_cpu_flags): Add cpumpx.
 553         (BNDPrefixOk): New.
 554         (i386_opcode_modifier): Add bndprefixok.
 555         (RegBND): New.
 556         (i386_operand_type): Add regbnd.
 557         * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
 558         Add MPX instructions and bnd prefix.
 559         * i386-reg.tbl: Add bnd0-bnd3 registers.
 560         * i386-tbl.h: Regenerate.
 561
 562 2013-07-17  Richard Sandiford  <rdsandiford@googlemail.com>
 563
 564         * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
 565         ATTRIBUTE_UNUSED.
 566
 567 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 568
 569         * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
 570         special rules.
 571         * Makefile.in: Regenerate.
 572         * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
 573         all fields.  Reformat.
 574
 575 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 576
 577         * mips16-opc.c: Include mips-formats.h.
 578         (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
 579         static arrays.
 580         (decode_mips16_operand): New function.
 581         * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
 582         (print_insn_arg): Handle OP_ENTRY_EXIT list.
 583         Abort for OP_SAVE_RESTORE_LIST.
 584         (print_mips16_insn_arg): Change interface.  Use mips_operand
 585         structures.  Delete GET_OP_S.  Move GET_OP definition to...
 586         (print_insn_mips16): ...here.  Call init_print_arg_state.
 587         Update the call to print_mips16_insn_arg.
 588
 589 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 590
 591         * mips-formats.h: New file.
 592         * mips-opc.c: Include mips-formats.h.
 593         (reg_0_map): New static array.
 594         (decode_mips_operand): New function.
 595         * micromips-opc.c: Remove <stdio.h> include.  Include mips-formats.h.
 596         (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
 597         (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
 598         (int_c_map): New static arrays.
 599         (decode_micromips_operand): New function.
 600         * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
 601         (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
 602         (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
 603         (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
 604         (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
 605         (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
 606         (micromips_imm_b_map, micromips_imm_c_map): Delete.
 607         (print_reg): New function.
 608         (mips_print_arg_state): New structure.
 609         (init_print_arg_state, print_insn_arg): New functions.
 610         (print_insn_args): Change interface and use mips_operand structures.
 611         Delete GET_OP_S.  Move GET_OP definition to...
 612         (print_insn_mips): ...here.  Update the call to print_insn_args.
 613         (print_insn_micromips): Use print_insn_args.
 614
 615 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 616
 617         * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
 618         in macros.
 619
 620 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 621
 622         * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
 623         ADDA.S, MULA.S and SUBA.S.
 624
 625 2013-07-08  H.J. Lu  <hongjiu.lu@intel.com>
 626
 627         PR gas/13572
 628         * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
 629         * i386-tbl.h: Regenerated.
 630
 631 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 632
 633         * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros.  Move LD
 634         and SD A(B) macros up.
 635         * micromips-opc.c (micromips_opcodes): Likewise.
 636
 637 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 638
 639         * mips16-opc.c: Add entries for argumentless "entry" and "exit"
 640         instructions.
 641
 642 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 643
 644         * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
 645         MDMX-like instructions.
 646         * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
 647         printing "Q" operands for INSN_5400 instructions.
 648
 649 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 650
 651         * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
 652         "+S" for "cins".
 653         * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
 654         Combine cases.
 655
 656 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 657
 658         * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
 659         "jalx".
 660         * mips16-opc.c (mips16_opcodes): Likewise.
 661         * micromips-opc.c (micromips_opcodes): Likewise.
 662         * mips-dis.c (print_insn_args, print_mips16_insn_arg)
 663         (print_insn_mips16): Handle "+i".
 664         (print_insn_micromips): Likewise.  Conditionally preserve the
 665         ISA bit for "a" but not for "+i".
 666
 667 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 668
 669         * micromips-opc.c (WR_mhi): Rename to..
 670         (WR_mh): ...this.
 671         (micromips_opcodes): Update "movep" entry accordingly.  Replace
 672         "mh,mi" with "mh".
 673         * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
 674         (micromips_to_32_reg_h_map1): ...this.
 675         (micromips_to_32_reg_i_map): Rename to...
 676         (micromips_to_32_reg_h_map2): ...this.
 677         (print_micromips_insn): Remove "mi" case.  Print both registers
 678         in the pair for "mh".
 679
 680 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 681
 682         * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
 683         * micromips-opc.c (micromips_opcodes): Likewise.
 684         * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
 685         and "+T" handling.  Check for a "0" suffix when deciding whether to
 686         use coprocessor 0 names.  In that case, also check for ",H" selectors.
 687
 688 2013-07-05  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 689
 690         * s390-opc.c (J12_12, J24_24): New macros.
 691         (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
 692         (MASK_MII_UPI): Rename to MASK_MII_UPP.
 693         * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
 694
 695 2013-07-04  Alan Modra  <amodra@gmail.com>
 696
 697         * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
 698
 699 2013-06-26  Nick Clifton  <nickc@redhat.com>
 700
 701         * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
 702         field when checking for type 2 nop.
 703         * rx-decode.c: Regenerate.
 704
 705 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
 706
 707         * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
 708         and "movep" macros.
 709
 710 2013-06-24  Maciej W. Rozycki  <macro@codesourcery.com>
 711
 712         * mips-dis.c (is_mips16_plt_tail): New function.
 713         (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
 714         word.
 715         (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
 716
 717 2013-06-21  DJ Delorie  <dj@redhat.com>
 718
 719         * msp430-decode.opc: New.
 720         * msp430-decode.c: New/generated.
 721         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
 722         (MAINTAINER_CLEANFILES): Likewise.
 723         Add rule to build msp430-decode.c frommsp430decode.opc
 724         using the opc2c program.
 725         * Makefile.in: Regenerate.
 726         * configure.in: Add msp430-decode.lo to msp430 architecture files.
 727         * configure: Regenerate.
 728
 729 2013-06-20  Yufeng Zhang  <yufeng.zhang@arm.com>
 730
 731         * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
 732         (SYMTAB_AVAILABLE): Removed.
 733         (#include "elf/aarch64.h): Ditto.
 734
 735 2013-06-17  Catherine Moore  <clm@codesourcery.com>
 736             Maciej W. Rozycki  <macro@codesourcery.com>
 737             Chao-Ying Fu  <fu@mips.com>
 738
 739         * micromips-opc.c (EVA): Define.
 740         (TLBINV): Define.
 741         (micromips_opcodes): Add EVA opcodes.
 742         * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
 743         (print_insn_args): Handle EVA offsets.
 744         (print_insn_micromips): Likewise.
 745         * mips-opc.c (EVA): Define.
 746         (TLBINV): Define.
 747         (mips_builtin_opcodes): Add EVA opcodes.
 748
 749 2013-06-17  Alan Modra  <amodra@gmail.com>
 750
 751         * Makefile.am (mips-opc.lo): Add rules to create automatic
 752         dependency files.  Pass archdefs.
 753         (micromips-opc.lo, mips16-opc.lo): Likewise.
 754         * Makefile.in: Regenerate.
 755
 756 2013-06-14  DJ Delorie  <dj@redhat.com>
 757
 758         * rx-decode.opc (rx_decode_opcode): Bit operations on
 759         registers are 32-bit operations, not 8-bit operations.
 760         * rx-decode.c: Regenerate.
 761
 762 2013-06-13  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 763
 764         * micromips-opc.c (IVIRT): New define.
 765         (IVIRT64): New define.
 766         (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 767         tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
 768
 769         * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
 770         dmtgc0 to print cp0 names.
 771
 772 2013-06-09  Sandra Loosemore  <sandra@codesourcery.com>
 773
 774         * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
 775         argument.
 776
 777 2013-06-08  Catherine Moore  <clm@codesourcery.com>
 778             Richard Sandiford  <rdsandiford@googlemail.com>
 779
 780         * micromips-opc.c (D32, D33, MC): Update definitions.
 781         (micromips_opcodes):  Initialize ase field.
 782         * mips-dis.c (mips_arch_choice): Add ase field.
 783         (mips_arch_choices): Initialize ase field.
 784         (set_default_mips_dis_options): Declare and setup mips_ase.
 785         * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
 786         MT32, MC): Update definitions.
 787         (mips_builtin_opcodes): Initialize ase field.
 788
 789 2013-05-24  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 790
 791         * s390-opc.txt (flogr): Require a register pair destination.
 792
 793 2013-05-23  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 794
 795         * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
 796         instruction format.
 797
 798 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 799
 800         * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
 801
 802 2013-05-20  Peter Bergner <bergner@vnet.ibm.com>
 803
 804         * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
 805         * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
 806         XLS_MASK, PPCVSX2): New defines.
 807         (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
 808         fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
 809         mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
 810         mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
 811         mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
 812         vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
 813         vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
 814         vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
 815         vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
 816         vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
 817         vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
 818         vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
 819         vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
 820         vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
 821         xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
 822         xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
 823         xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
 824         xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
 825         <lxvx, stxvx>: New extended mnemonics.
 826
 827 2013-05-17  Alan Modra  <amodra@gmail.com>
 828
 829         * ia64-raw.tbl: Replace non-ASCII char.
 830         * ia64-waw.tbl: Likewise.
 831         * ia64-asmtab.c: Regenerate.
 832
 833 2013-05-15  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 834
 835         * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
 836         * i386-init.h: Regenerated.
 837
 838 2013-05-13  Yufeng Zhang  <yufeng.zhang@arm.com>
 839
 840         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
 841         * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
 842         check from [0, 255] to [-128, 255].
 843
 844 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 845
 846         * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
 847         Add INSN_VIRT and INSN_VIRT64 to mips64r2.
 848         (parse_mips_dis_option): Handle the virt option.
 849         (print_insn_args): Handle "+J".
 850         (print_mips_disassembler_options): Print out message about virt64.
 851         * mips-opc.c (IVIRT): New define.
 852         (IVIRT64): New define.
 853         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 854         tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
 855         Move rfe to the bottom as it conflicts with tlbgp.
 856
 857 2013-05-09  Alan Modra  <amodra@gmail.com>
 858
 859         * ppc-opc.c (extract_vlesi): Properly sign extend.
 860         (extract_vlensi): Likewise.  Comment reason for setting invalid.
 861
 862 2013-05-02  Nick Clifton  <nickc@redhat.com>
 863
 864         * msp430-dis.c: Add support for MSP430X instructions.
 865
 866 2013-04-24  Sandra Loosemore  <sandra@codesourcery.com>
 867
 868         * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
 869         to "eccinj".
 870
 871 2013-04-17  Wei-chen Wang  <cole945@gmail.com>
 872
 873         PR binutils/15369
 874         * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
 875         of CGEN_CPU_ENDIAN.
 876         (hash_insns_list): Likewise.
 877
 878 2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>
 879
 880         * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
 881         warning workaround.
 882
 883 2013-04-08  Jan Beulich <jbeulich@suse.com>
 884
 885         * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
 886         * i386-tbl.h: Re-generate.
 887
 888 2013-04-06  David S. Miller  <davem@davemloft.net>
 889
 890         * sparc-dis.c (compare_opcodes): When encountering multiple aliases
 891         of an opcode, prefer the one with F_PREFERRED set.
 892         * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
 893         lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
 894         ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
 895         mark existing mnenomics as aliases.  Add "cc" suffix to edge
 896         instructions generating condition codes, mark existing mnenomics
 897         as aliases.  Add "fp" prefix to VIS compare instructions, mark
 898         existing mnenomics as aliases.
 899
 900 2013-04-03  Nick Clifton  <nickc@redhat.com>
 901
 902         * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
 903         destination address by subtracting the operand from the current
 904         address.
 905         * v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
 906         a positive value in the insn.
 907         (extract_u16_loop): Do not negate the returned value.
 908         (D16_LOOP): Add V850_INVERSE_PCREL flag.
 909
 910         (ceilf.sw): Remove duplicate entry.
 911         (cvtf.hs): New entry.
 912         (cvtf.sh): Likewise.
 913         (fmaf.s): Likewise.
 914         (fmsf.s): Likewise.
 915         (fnmaf.s): Likewise.
 916         (fnmsf.s): Likewise.
 917         (maddf.s): Restrict to E3V5 architectures.
 918         (msubf.s): Likewise.
 919         (nmaddf.s): Likewise.
 920         (nmsubf.s): Likewise.
 921
 922 2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>
 923
 924         * i386-dis.c (get_sib): Add the sizeflag argument.  Properly
 925         check address mode.
 926         (print_insn): Pass sizeflag to get_sib.
 927
 928 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 929
 930         PR binutils/15068
 931         * tic6x-dis.c: Add support for displaying 16-bit insns.
 932
 933 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 934
 935         PR gas/15095
 936         * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
 937         individual msb and lsb halves in src1 & src2 fields.  Discard the
 938         src1 (lsb) value and only use src2 (msb), discarding bit 0, to
 939         follow what Ti SDK does in that case as any value in the src1
 940         field yields the same output with SDK disassembler.
 941
 942 2013-03-12  Michael Eager <eager@eagercon.com>
 943
 944         * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
 945
 946 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 947
 948         * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
 949
 950 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 951
 952         * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
 953
 954 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 955
 956         * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
 957
 958 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 959
 960         * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
 961         (thumb32_opcodes): Likewise.
 962         (print_insn_thumb32): Handle 'S' control char.
 963
 964 2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
 965
 966         * lm32-desc.c: Regenerate.
 967
 968 2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 969
 970         * i386-reg.tbl (riz): Add RegRex64.
 971         * i386-tbl.h: Regenerated.
 972
 973 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 974
 975         * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
 976         (aarch64_feature_crc): New static.
 977         (CRC): New macro.
 978         (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
 979         crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
 980         * aarch64-asm-2.c: Re-generate.
 981         * aarch64-dis-2.c: Ditto.
 982         * aarch64-opc-2.c: Ditto.
 983
 984 2013-02-27  Alan Modra  <amodra@gmail.com>
 985
 986         * rl78-decode.opc (rl78_decode_opcode): Fix typo.
 987         * rl78-decode.c: Regenerate.
 988
 989 2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
 990
 991         * rl78-decode.opc: Fix encoding of DIVWU insn.
 992         * rl78-decode.c: Regenerate.
 993
 994 2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 995
 996         PR gas/15159
 997         * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
 998
 999         * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
1000         (cpu_flags): Add CpuSMAP.
1001
1002         * i386-opc.h (CpuSMAP): New.
1003         (i386_cpu_flags): Add cpusmap.
1004
1005         * i386-opc.tbl: Add clac and stac.
1006
1007         * i386-init.h: Regenerated.
1008         * i386-tbl.h: Likewise.
1009
1010 2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
1011
1012         * metag-dis.c: Initialize outf->bytes_per_chunk to 4
1013         which also makes the disassembler output be in little
1014         endian like it should be.
1015
1016 2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
1017
1018         * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
1019         fields to NULL.
1020         (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
1021
1022 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
1023
1024         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
1025         section disassembled.
1026
1027 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1028
1029         * arm-dis.c: Update strht pattern.
1030
1031 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
1032
1033         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
1034         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
1035         trunc.w.s macro for EE.
1036
1037 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
1038             Andrew Jenner <andrew@codesourcery.com>
1039
1040         Based on patches from Altera Corporation.
1041
1042         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
1043         nios2-opc.c.
1044         * Makefile.in: Regenerated.
1045         * configure.in: Add case for bfd_nios2_arch.
1046         * configure: Regenerated.
1047         * disassemble.c (ARCH_nios2): Define.
1048         (disassembler): Add case for bfd_arch_nios2.
1049         * nios2-dis.c: New file.
1050         * nios2-opc.c: New file.
1051
1052 2013-02-04  Alan Modra  <amodra@gmail.com>
1053
1054         * po/POTFILES.in: Regenerate.
1055         * rl78-decode.c: Regenerate.
1056         * rx-decode.c: Regenerate.
1057
1058 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
1059
1060         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
1061         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
1062         * aarch64-asm.c (convert_xtl_to_shll): New function.
1063         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1064         calling convert_xtl_to_shll.
1065         * aarch64-dis.c (convert_shll_to_xtl): New function.
1066         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1067         calling convert_shll_to_xtl.
1068         * aarch64-gen.c: Update copyright year.
1069         * aarch64-asm-2.c: Re-generate.
1070         * aarch64-dis-2.c: Re-generate.
1071         * aarch64-opc-2.c: Re-generate.
1072
1073 2013-01-24  Nick Clifton  <nickc@redhat.com>
1074
1075         * v850-dis.c: Add support for e3v5 architecture.
1076         * v850-opc.c: Likewise.
1077
1078 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
1079
1080         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
1081         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
1082         * aarch64-opc.c (operand_general_constraint_met_p): For
1083         AARCH64_MOD_LSL, move the range check on the shift amount before the
1084         alignment check; change to call set_sft_amount_out_of_range_error
1085         instead of set_imm_out_of_range_error.
1086         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
1087         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
1088         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
1089         SIMD_IMM_SFT.
1090
1091 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
1092
1093         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
1094
1095         * i386-init.h: Regenerated.
1096         * i386-tbl.h: Likewise.
1097
1098 2013-01-15  Nick Clifton  <nickc@redhat.com>
1099
1100         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
1101         values.
1102         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1103
1104 2013-01-14  Will Newton <will.newton@imgtec.com>
1105
1106         * metag-dis.c (REG_WIDTH): Increase to 64.
1107
1108 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
1109
1110         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1111         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1112         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1113         (SH6): Update.
1114         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1115         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1116         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1117         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1118
1119 2013-01-10  Will Newton <will.newton@imgtec.com>
1120
1121         * Makefile.am: Add Meta.
1122         * configure.in: Add Meta.
1123         * disassemble.c: Add Meta support.
1124         * metag-dis.c: New file.
1125         * Makefile.in: Regenerate.
1126         * configure: Regenerate.
1127
1128 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1129
1130         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1131         (match_opcode): Rename to cr16_match_opcode.
1132
1133 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
1134
1135         * mips-dis.c: Add names for CP0 registers of r5900.
1136         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1137         instructions sq and lq.
1138         Add support for MIPS r5900 CPU.
1139         Add support for 128 bit MMI (Multimedia Instructions).
1140         Add support for EE instructions (Emotion Engine).
1141         Disable unsupported floating point instructions (64 bit and
1142         undefined compare operations).
1143         Enable instructions of MIPS ISA IV which are supported by r5900.
1144         Disable 64 bit co processor instructions.
1145         Disable 64 bit multiplication and division instructions.
1146         Disable instructions for co-processor 2 and 3, because these are
1147         not supported (preparation for later VU0 support (Vector Unit)).
1148         Disable cvt.w.s because this behaves like trunc.w.s and the
1149         correct execution can't be ensured on r5900.
1150         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1151         will confuse less developers and compilers.
1152
1153 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1154
1155         * aarch64-opc.c (aarch64_print_operand): Change to print
1156         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1157         in comment.
1158         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1159         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1160         OP_MOV_IMM_WIDE.
1161
1162 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1163
1164         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1165         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
1166
1167 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
1168
1169         * i386-gen.c (process_copyright): Update copyright year to 2013.
1170
1171 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1172
1173         * cr16-dis.c (match_opcode,make_instruction): Remove static
1174         declaration.
1175         (dwordU,wordU): Moved typedefs to opcode/cr16.h
1176         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
1177
1178 For older changes see ChangeLog-2012
1179 \f
1180 Copyright (C) 2013 Free Software Foundation, Inc.
1181
1182 Copying and distribution of this file, with or without modification,
1183 are permitted in any medium without royalty provided the copyright
1184 notice and this notice are preserved.
1185
1186 Local Variables:
1187 mode: change-log
1188 left-margin: 8
1189 fill-column: 74
1190 version-control: never
1191 End: