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MIPS16: Remove "extended" BREAK/SDBBP handling
[binutils-gdb.git] / opcodes / ChangeLog
1 2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
2
3 * mips16-opc.c (decode_mips16_operand) <'6'>: Remove extended
4 encoding support.
5
6 2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
7
8 * mips16-opc.c (mips16_opcodes): Set NODS in `pinfo' for
9 "extend".
10
11 2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
12
13 * mips-dis.c (set_default_mips_dis_options): Use
14 HAVE_BFD_MIPS_ELF_GET_ABIFLAGS rather than BFD64 to guard the
15 call to `bfd_mips_elf_get_abiflags'.
16 * configure.ac: Check for `bfd_mips_elf_get_abiflags' in BFD.
17 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add `libbfd.la'.
18 * aclocal.m4: Regenerate.
19 * configure: Regenerate.
20 * config.in: Regenerate.
21 * Makefile.in: Regenerate.
22
23 2016-12-23 Tristan Gingold <gingold@adacore.com>
24
25 * configure: Regenerate.
26
27 2016-12-23 Tristan Gingold <gingold@adacore.com>
28
29 * po/opcodes.pot: Regenerate.
30
31 2016-12-21 Andrew Waterman <andrew@sifive.com>
32
33 * riscv-opc.c (riscv_opcodes): Reorder jal and call entries.
34
35 2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
36
37 * mips-dis.c (mips_arch_choices): Use ISA_MIPS64 rather than
38 ISA_MIPS3 as the `isa' selection in the `bfd_mach_mips16' entry.
39 (print_insn_mips16): Check opcode entries for validity against
40 the ISA level and ASE set selected.
41
42 2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
43
44 * mips-dis.c (print_mips16_insn_arg): Always handle `extend' and
45 `insn' together, with `extend' as the high-order 16 bits.
46 (match_kind): New enum.
47 (print_insn_mips16): Rework for 32-bit instruction matching.
48 Do not dump EXTEND prefixes here.
49 * mips16-opc.c (mips16_opcodes): Move "extend" entry to the end.
50 Recode `match' and `mask' fields as 32-bit in absolute "jal" and
51 "jalx" entries.
52
53 2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
54
55 * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
56 than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu"
57 INSN_MACRO entries.
58
59 2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
60
61 * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
62 than I1 for the SP-relative "sd"/$ra entry (SDRASP minor
63 opcode).
64
65 2016-12-20 Andrew Waterman <andrew@sifive.com>
66
67 * riscv-opc.c (riscv_opcodes): Rename the "*.sc" instructions to
68 "*.aqrl".
69
70 2016-12-20 Andrew Waterman <andrew@sifive.com>
71
72 * riscv-opc.c (riscv_opcodes): Mark the rd* and csr* aliases as
73 INSN_ALIAS.
74
75 2016-12-20 Andrew Waterman <andrew@sifive.com>
76
77 * riscv-opc.c (riscv_opcodes): Change jr and jalr to "o(s)"
78 format.
79
80 2016-12-20 Andrew Waterman <andrew@sifive.com>
81
82 * riscv-dis.c (riscv_disassemble_insn): Default to the ELF's
83 XLEN when none is provided.
84
85 2016-12-20 Andrew Waterman <andrew@sifive.com>
86
87 * riscv-opc.c: Formatting fixes.
88
89 2016-12-20 Alan Modra <amodra@gmail.com>
90
91 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files.
92 * Makefile.in: Regenerate.
93 * po/POTFILES.in: Regenerate.
94
95 2016-12-19 Maciej W. Rozycki <macro@imgtec.com>
96
97 * mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]:
98 Only examine ELF file structures here.
99
100 2016-12-19 Maciej W. Rozycki <macro@imgtec.com>
101
102 * mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call
103 `bfd_mips_elf_get_abiflags' here.
104
105 2016-12-16 Nick Clifton <nickc@redhat.com>
106
107 * arm-dis.c (print_insn_thumb32): Fix compile time warning
108 computing value_in_comment.
109
110 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
111
112 * mips-dis.c (mips_convert_abiflags_ases): New function.
113 (set_default_mips_dis_options): Also infer ASE flags from ELF
114 file structures.
115
116 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
117
118 * mips-dis.c (set_default_mips_dis_options): Reorder ELF file
119 header flag interpretation code.
120
121 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
122
123 * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
124 `pinfo2' with SP-relative "sd" entries.
125
126 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
127
128 * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e
129 compact jumps.
130
131 2016-12-13 Renlin Li <renlin.li@arm.com>
132
133 * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
134 qualifier.
135 (operand_general_constraint_met_p): Remove case for CP_REG.
136 (aarch64_print_operand): Print CRn, CRm operand using imm field.
137 * aarch64-tbl.h (QL_SYS): Use CR qualifier.
138 (QL_SYSL): Likewise.
139 (aarch64_opcode_table): Change CRn, CRm operand class and type.
140 * aarch64-opc-2.c : Regenerate.
141 * aarch64-asm-2.c : Likewise.
142 * aarch64-dis-2.c : Likewise.
143
144 2016-12-12 Yao Qi <yao.qi@linaro.org>
145
146 * rx-dis.c: Include <setjmp.h>
147 (struct private): New.
148 (rx_get_byte): Check return value of read_memory_func, and
149 call memory_error_func and OPCODES_SIGLONGJMP on error.
150 (print_insn_rx): Call OPCODES_SIGSETJMP.
151
152 2016-12-12 Yao Qi <yao.qi@linaro.org>
153
154 * rl78-dis.c: Include <setjmp.h>.
155 (struct private): New.
156 (rl78_get_byte): Check return value of read_memory_func, and
157 call memory_error_func and OPCODES_SIGLONGJMP on error.
158 (print_insn_rl78_common): Call OPCODES_SIGJMP.
159
160 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
161
162 * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
163
164 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
165
166 * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
167 than UINT.
168
169 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
170
171 * mips-dis.c (print_insn_mips16): Use a tab rather than a space
172 to separate `extend' and its uninterpreted argument output.
173 Separate hexadecimal halves of undecoded extended instructions
174 output.
175
176 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
177
178 * mips-dis.c (print_mips16_insn_arg): Remove extraneous
179 indentation space across.
180
181 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
182
183 * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
184 adjustment for PC-relative operations following MIPS16e compact
185 jumps or undefined RR/J(AL)R(C) encodings.
186
187 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
188
189 * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
190 variable to `reglane_index'.
191
192 2016-12-08 Luis Machado <lgustavo@codesourcery.com>
193
194 * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
195
196 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
197
198 * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
199
200 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
201
202 * mips16-opc.c (mips16_opcodes): Update comment naming structure
203 members.
204
205 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
206
207 * mips-dis.c (print_mips_disassembler_options): Reformat output.
208
209 2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
210
211 * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
212 (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
213
214 2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
215
216 * arm-dis.c (coprocessor_opcodes): Add vjcvt.
217
218 2016-12-01 Nick Clifton <nickc@redhat.com>
219
220 PR binutils/20893
221 * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
222 opcode designator.
223
224 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
225
226 * arc-opc.c (insert_ra_chk): New function.
227 (insert_rb_chk): Likewise.
228 (insert_rad): Update text error message.
229 (insert_rcd): Likewise.
230 (insert_rhv2): Likewise.
231 (insert_r0): Likewise.
232 (insert_r1): Likewise.
233 (insert_r2): Likewise.
234 (insert_r3): Likewise.
235 (insert_sp): Likewise.
236 (insert_gp): Likewise.
237 (insert_pcl): Likewise.
238 (insert_blink): Likewise.
239 (insert_ilink1): Likewise.
240 (insert_ilink2): Likewise.
241 (insert_ras): Likewise.
242 (insert_rbs): Likewise.
243 (insert_rcs): Likewise.
244 (insert_simm3s): Likewise.
245 (insert_rrange): Likewise.
246 (insert_fpel): Likewise.
247 (insert_blinkel): Likewise.
248 (insert_pcel): Likewise.
249 (insert_nps_3bit_dst): Likewise.
250 (insert_nps_3bit_dst_short): Likewise.
251 (insert_nps_3bit_src2_short): Likewise.
252 (insert_nps_bitop_size_2b): Likewise.
253 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
254 (RA_CHK): Define.
255 (RB): Adjust.
256 (RB_CHK): Define.
257 (RC): Adjust.
258 * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
259 * arc-tbl.h (div, divu): All instructions are DIVREM class.
260 Change first insn argument to check for LP_COUNT usage.
261 (rem): Likewise.
262 (ld, ldd): All instructions are LOAD class. Change first insn
263 argument to check for LP_COUNT usage.
264 (st, std): All instructions are STORE class.
265 (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
266 Change first insn argument to check for LP_COUNT usage.
267 (mov): All instructions are MOVE class. Change first insn
268 argument to check for LP_COUNT usage.
269
270 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
271
272 * arc-dis.c (is_compatible_p): Remove function.
273 (skip_this_opcode): Don't add any decoding class to decode list.
274 Remove warning.
275 (find_format_from_table): Go through all opcodes, and warn if we
276 use a guessed mnemonic.
277
278 2016-11-28 Ramiro Polla <ramiro@hex-rays.com>
279 Amit Pawar <amit.pawar@amd.com>
280
281 PR binutils/20637
282 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
283 instructions.
284
285 2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
286
287 * configure: Regenerate.
288
289 2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
290
291 * sparc-opc.c (HWS_V8): Definition moved from
292 gas/config/tc-sparc.c.
293 (HWS_V9): Likewise.
294 (HWS_VA): Likewise.
295 (HWS_VB): Likewise.
296 (HWS_VC): Likewise.
297 (HWS_VD): Likewise.
298 (HWS_VE): Likewise.
299 (HWS_VV): Likewise.
300 (HWS_VM): Likewise.
301 (HWS2_VM): Likewise.
302 (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
303 existing entries.
304
305 2016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
306
307 * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
308 instructions.
309
310 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
311
312 * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
313 (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
314 (aarch64_opcode_table): Add fcmla and fcadd.
315 (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
316 * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
317 * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
318 * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
319 * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
320 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
321 * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
322 (operand_general_constraint_met_p): Rotate and index range check.
323 (aarch64_print_operand): Handle rotate operand.
324 * aarch64-asm-2.c: Regenerate.
325 * aarch64-dis-2.c: Likewise.
326 * aarch64-opc-2.c: Likewise.
327
328 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
329
330 * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
331 * aarch64-asm-2.c: Regenerate.
332 * aarch64-dis-2.c: Regenerate.
333 * aarch64-opc-2.c: Regenerate.
334
335 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
336
337 * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
338 (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
339 * aarch64-asm-2.c: Regenerate.
340 * aarch64-dis-2.c: Regenerate.
341 * aarch64-opc-2.c: Regenerate.
342
343 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
344
345 * aarch64-tbl.h (QL_X1NIL): New.
346 (arch64_opcode_table): Add ldraa, ldrab.
347 (AARCH64_OPERANDS): Add "ADDR_SIMM10".
348 * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
349 * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
350 * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
351 * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
352 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
353 * aarch64-opc.c (fields): Add data for FLD_S_simm10.
354 (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
355 (aarch64_print_operand): Likewise.
356 * aarch64-asm-2.c: Regenerate.
357 * aarch64-dis-2.c: Regenerate.
358 * aarch64-opc-2.c: Regenerate.
359
360 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
361
362 * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
363 brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
364 * aarch64-asm-2.c: Regenerate.
365 * aarch64-dis-2.c: Regenerate.
366 * aarch64-opc-2.c: Regenerate.
367
368 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
369
370 * aarch64-tbl.h (arch64_opcode_table): Add pacga.
371 (AARCH64_OPERANDS): Add Rm_SP.
372 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
373 * aarch64-asm-2.c: Regenerate.
374 * aarch64-dis-2.c: Regenerate.
375 * aarch64-opc-2.c: Regenerate.
376
377 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
378
379 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
380 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
381 autdzb, xpaci, xpacd.
382 * aarch64-asm-2.c: Regenerate.
383 * aarch64-dis-2.c: Regenerate.
384 * aarch64-opc-2.c: Regenerate.
385
386 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
387
388 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
389 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
390 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
391 (aarch64_sys_reg_supported_p): Add feature test for new registers.
392
393 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
394
395 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
396 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
397 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
398 autibsp.
399 * aarch64-asm-2.c: Regenerate.
400 * aarch64-dis-2.c: Regenerate.
401
402 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
403
404 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
405
406 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
407
408 PR binutils/20799
409 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
410 * i386-dis.c (EdqwS): Removed.
411 (dqw_swap_mode): Likewise.
412 (intel_operand_size): Don't check dqw_swap_mode.
413 (OP_E_register): Likewise.
414 (OP_E_memory): Likewise.
415 (OP_G): Likewise.
416 (OP_EX): Likewise.
417 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
418 * i386-tbl.h: Regerated.
419
420 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
421
422 * i386-opc.tbl: Merge AVX512F vmovq.
423 * i386-tbl.h: Regerated.
424
425 2016-11-08 H.J. Lu <hongjiu.lu@intel.com>
426
427 PR binutils/20701
428 * i386-dis.c (THREE_BYTE_0F7A): Removed.
429 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
430 (three_byte_table): Remove THREE_BYTE_0F7A.
431
432 2016-11-07 H.J. Lu <hongjiu.lu@intel.com>
433
434 PR binutils/20775
435 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
436 (FGRPd9_4): Replace 1 with 2.
437 (FGRPd9_5): Replace 2 with 3.
438 (FGRPd9_6): Replace 3 with 4.
439 (FGRPd9_7): Replace 4 with 5.
440 (FGRPda_5): Replace 5 with 6.
441 (FGRPdb_4): Replace 6 with 7.
442 (FGRPde_3): Replace 7 with 8.
443 (FGRPdf_4): Replace 8 with 9.
444 (fgrps): Add an entry for Bad_Opcode.
445
446 2016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
447
448 * arc-opc.c (arc_flag_operands): Add F_DI14.
449 (arc_flag_classes): Add C_DI14.
450 * arc-nps400-tbl.h: Add new exc instructions.
451
452 2016-11-03 Graham Markall <graham.markall@embecosm.com>
453
454 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
455 major opcode 0xa.
456 * arc-nps-400-tbl.h: Add dcmac instruction.
457 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
458 (insert_nps_rbdouble_64): Added.
459 (extract_nps_rbdouble_64): Added.
460 (insert_nps_proto_size): Added.
461 (extract_nps_proto_size): Added.
462
463 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
464
465 * arc-dis.c (struct arc_operand_iterator): Remove all fields
466 relating to long instruction processing, add new limm field.
467 (OPCODE): Rename to...
468 (OPCODE_32BIT_INSN): ...this.
469 (OPCODE_AC): Delete.
470 (skip_this_opcode): Handle different instruction lengths, update
471 macro name.
472 (special_flag_p): Update parameter type.
473 (find_format_from_table): Update for more instruction lengths.
474 (find_format_long_instructions): Delete.
475 (find_format): Update for more instruction lengths.
476 (arc_insn_length): Likewise.
477 (extract_operand_value): Update for more instruction lengths.
478 (operand_iterator_next): Remove code relating to long
479 instructions.
480 (arc_opcode_to_insn_type): New function.
481 (print_insn_arc):Update for more instructions lengths.
482 * arc-ext.c (extInstruction_t): Change argument type.
483 * arc-ext.h (extInstruction_t): Change argument type.
484 * arc-fxi.h: Change type unsigned to unsigned long long
485 extensively throughout.
486 * arc-nps400-tbl.h: Add long instructions taken from
487 arc_long_opcodes table in arc-opc.c.
488 * arc-opc.c: Update parameter types on insert/extract handlers.
489 (arc_long_opcodes): Delete.
490 (arc_num_long_opcodes): Delete.
491 (arc_opcode_len): Update for more instruction lengths.
492
493 2016-11-03 Graham Markall <graham.markall@embecosm.com>
494
495 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
496
497 2016-11-03 Graham Markall <graham.markall@embecosm.com>
498
499 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
500 with arc_opcode_len.
501 (find_format_long_instructions): Likewise.
502 * arc-opc.c (arc_opcode_len): New function.
503
504 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
505
506 * arc-nps400-tbl.h: Fix some instruction masks.
507
508 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
509
510 * i386-dis.c (REG_82): Removed.
511 (X86_64_82_REG_0): Likewise.
512 (X86_64_82_REG_1): Likewise.
513 (X86_64_82_REG_2): Likewise.
514 (X86_64_82_REG_3): Likewise.
515 (X86_64_82_REG_4): Likewise.
516 (X86_64_82_REG_5): Likewise.
517 (X86_64_82_REG_6): Likewise.
518 (X86_64_82_REG_7): Likewise.
519 (X86_64_82): New.
520 (dis386): Use X86_64_82 instead of REG_82.
521 (reg_table): Remove REG_82.
522 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
523 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
524 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
525 X86_64_82_REG_7.
526
527 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
528
529 PR binutils/20754
530 * i386-dis.c (REG_82): New.
531 (X86_64_82_REG_0): Likewise.
532 (X86_64_82_REG_1): Likewise.
533 (X86_64_82_REG_2): Likewise.
534 (X86_64_82_REG_3): Likewise.
535 (X86_64_82_REG_4): Likewise.
536 (X86_64_82_REG_5): Likewise.
537 (X86_64_82_REG_6): Likewise.
538 (X86_64_82_REG_7): Likewise.
539 (dis386): Use REG_82.
540 (reg_table): Add REG_82.
541 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
542 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
543 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
544
545 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
546
547 * i386-dis.c (REG_82): Renamed to ...
548 (REG_83): This.
549 (dis386): Updated.
550 (reg_table): Likewise.
551
552 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
553
554 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
555 * i386-dis-evex.h (evex_table): Updated.
556 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
557 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
558 (cpu_flags): Add CpuAVX512_4VNNIW.
559 * i386-opc.h (enum): (AVX512_4VNNIW): New.
560 (i386_cpu_flags): Add cpuavx512_4vnniw.
561 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
562 * i386-init.h: Regenerate.
563 * i386-tbl.h: Ditto.
564
565 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
566
567 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
568 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
569 * i386-dis-evex.h (evex_table): Updated.
570 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
571 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
572 (cpu_flags): Add CpuAVX512_4FMAPS.
573 (opcode_modifiers): Add ImplicitQuadGroup modifier.
574 * i386-opc.h (AVX512_4FMAP): New.
575 (i386_cpu_flags): Add cpuavx512_4fmaps.
576 (ImplicitQuadGroup): New.
577 (i386_opcode_modifier): Add implicitquadgroup.
578 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
579 * i386-init.h: Regenerate.
580 * i386-tbl.h: Ditto.
581
582 2016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
583 Andrew Waterman <andrew@sifive.com>
584
585 Add support for RISC-V architecture.
586 * configure.ac: Add entry for bfd_riscv_arch.
587 * configure: Regenerate.
588 * disassemble.c (disassembler): Add support for riscv.
589 (disassembler_usage): Likewise.
590 * riscv-dis.c: New file.
591 * riscv-opc.c: New file.
592
593 2016-10-21 H.J. Lu <hongjiu.lu@intel.com>
594
595 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
596 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
597 (rm_table): Update the RM_0FAE_REG_7 entry.
598 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
599 (cpu_flags): Remove CpuPCOMMIT.
600 * i386-opc.h (CpuPCOMMIT): Removed.
601 (i386_cpu_flags): Remove cpupcommit.
602 * i386-opc.tbl: Remove pcommit.
603 * i386-init.h: Regenerated.
604 * i386-tbl.h: Likewise.
605
606 2016-10-20 H.J. Lu <hongjiu.lu@intel.com>
607
608 PR binutis/20705
609 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
610 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
611 32-bit mode. Don't check vex.register_specifier in 32-bit
612 mode.
613 (OP_VEX): Check for invalid mask registers.
614
615 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
616
617 PR binutis/20699
618 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
619 sizeflag.
620
621 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
622
623 PR binutis/20704
624 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
625
626 2016-10-18 Maciej W. Rozycki <macro@imgtec.com>
627
628 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
629 local variable to `index_regno'.
630
631 2016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
632
633 * arc-tbl.h: Removed any "inv.+" instructions from the table.
634
635 2016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
636
637 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
638 usage on ISA basis.
639
640 2016-10-11 Jiong Wang <jiong.wang@arm.com>
641
642 PR target/20666
643 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
644
645 2016-10-07 Jiong Wang <jiong.wang@arm.com>
646
647 PR target/20667
648 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
649 available.
650
651 2016-10-07 Alan Modra <amodra@gmail.com>
652
653 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
654
655 2016-10-06 Alan Modra <amodra@gmail.com>
656
657 * aarch64-opc.c: Spell fall through comments consistently.
658 * i386-dis.c: Likewise.
659 * aarch64-dis.c: Add missing fall through comments.
660 * aarch64-opc.c: Likewise.
661 * arc-dis.c: Likewise.
662 * arm-dis.c: Likewise.
663 * i386-dis.c: Likewise.
664 * m68k-dis.c: Likewise.
665 * mep-asm.c: Likewise.
666 * ns32k-dis.c: Likewise.
667 * sh-dis.c: Likewise.
668 * tic4x-dis.c: Likewise.
669 * tic6x-dis.c: Likewise.
670 * vax-dis.c: Likewise.
671
672 2016-10-06 Alan Modra <amodra@gmail.com>
673
674 * arc-ext.c (create_map): Add missing break.
675 * msp430-decode.opc (encode_as): Likewise.
676 * msp430-decode.c: Regenerate.
677
678 2016-10-06 Alan Modra <amodra@gmail.com>
679
680 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
681 * crx-dis.c (print_insn_crx): Likewise.
682
683 2016-09-30 H.J. Lu <hongjiu.lu@intel.com>
684
685 PR binutils/20657
686 * i386-dis.c (putop): Don't assign alt twice.
687
688 2016-09-29 Jiong Wang <jiong.wang@arm.com>
689
690 PR target/20553
691 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
692
693 2016-09-29 Alan Modra <amodra@gmail.com>
694
695 * ppc-opc.c (L): Make compulsory.
696 (LOPT): New, optional form of L.
697 (HTM_R): Define as LOPT.
698 (L0, L1): Delete.
699 (L32OPT): New, optional for 32-bit L.
700 (L2OPT): New, 2-bit L for dcbf.
701 (SVC_LEC): Update.
702 (L2): Define.
703 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
704 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
705 <dcbf>: Use L2OPT.
706 <tlbiel, tlbie>: Use LOPT.
707 <wclr, wclrall>: Use L2.
708
709 2016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
710
711 * Makefile.in: Regenerate.
712 * configure: Likewise.
713
714 2016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
715
716 * arc-ext-tbl.h (EXTINSN2OPF): Define.
717 (EXTINSN2OP): Use EXTINSN2OPF.
718 (bspeekm, bspop, modapp): New extension instructions.
719 * arc-opc.c (F_DNZ_ND): Define.
720 (F_DNZ_D): Likewise.
721 (F_SIZEB1): Changed.
722 (C_DNZ_D): Define.
723 (C_HARD): Changed.
724 * arc-tbl.h (dbnz): New instruction.
725 (prealloc): Allow it for ARC EM.
726 (xbfu): Likewise.
727
728 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
729
730 * aarch64-opc.c (print_immediate_offset_address): Print spaces
731 after commas in addresses.
732 (aarch64_print_operand): Likewise.
733
734 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
735
736 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
737 rather than "should be" or "expected to be" in error messages.
738
739 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
740
741 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
742 (print_mnemonic_name): ...here.
743 (print_comment): New function.
744 (print_aarch64_insn): Call it.
745 * aarch64-opc.c (aarch64_conds): Add SVE names.
746 (aarch64_print_operand): Print alternative condition names in
747 a comment.
748
749 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
750
751 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
752 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
753 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
754 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
755 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
756 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
757 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
758 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
759 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
760 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
761 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
762 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
763 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
764 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
765 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
766 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
767 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
768 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
769 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
770 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
771 (OP_SVE_XWU, OP_SVE_XXU): New macros.
772 (aarch64_feature_sve): New variable.
773 (SVE): New macro.
774 (_SVE_INSN): Likewise.
775 (aarch64_opcode_table): Add SVE instructions.
776 * aarch64-opc.h (extract_fields): Declare.
777 * aarch64-opc-2.c: Regenerate.
778 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
779 * aarch64-asm-2.c: Regenerate.
780 * aarch64-dis.c (extract_fields): Make global.
781 (do_misc_decoding): Handle the new SVE aarch64_ops.
782 * aarch64-dis-2.c: Regenerate.
783
784 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
785
786 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
787 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
788 aarch64_field_kinds.
789 * aarch64-opc.c (fields): Add corresponding entries.
790 * aarch64-asm.c (aarch64_get_variant): New function.
791 (aarch64_encode_variant_using_iclass): Likewise.
792 (aarch64_opcode_encode): Call it.
793 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
794 (aarch64_opcode_decode): Call it.
795
796 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
797
798 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
799 and FP register operands.
800 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
801 (FLD_SVE_Vn): New aarch64_field_kinds.
802 * aarch64-opc.c (fields): Add corresponding entries.
803 (aarch64_print_operand): Handle the new SVE core and FP register
804 operands.
805 * aarch64-opc-2.c: Regenerate.
806 * aarch64-asm-2.c: Likewise.
807 * aarch64-dis-2.c: Likewise.
808
809 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
810
811 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
812 immediate operands.
813 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
814 * aarch64-opc.c (fields): Add corresponding entry.
815 (operand_general_constraint_met_p): Handle the new SVE FP immediate
816 operands.
817 (aarch64_print_operand): Likewise.
818 * aarch64-opc-2.c: Regenerate.
819 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
820 (ins_sve_float_zero_one): New inserters.
821 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
822 (aarch64_ins_sve_float_half_two): Likewise.
823 (aarch64_ins_sve_float_zero_one): Likewise.
824 * aarch64-asm-2.c: Regenerate.
825 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
826 (ext_sve_float_zero_one): New extractors.
827 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
828 (aarch64_ext_sve_float_half_two): Likewise.
829 (aarch64_ext_sve_float_zero_one): Likewise.
830 * aarch64-dis-2.c: Regenerate.
831
832 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
833
834 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
835 integer immediate operands.
836 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
837 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
838 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
839 * aarch64-opc.c (fields): Add corresponding entries.
840 (operand_general_constraint_met_p): Handle the new SVE integer
841 immediate operands.
842 (aarch64_print_operand): Likewise.
843 (aarch64_sve_dupm_mov_immediate_p): New function.
844 * aarch64-opc-2.c: Regenerate.
845 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
846 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
847 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
848 (aarch64_ins_limm): ...here.
849 (aarch64_ins_inv_limm): New function.
850 (aarch64_ins_sve_aimm): Likewise.
851 (aarch64_ins_sve_asimm): Likewise.
852 (aarch64_ins_sve_limm_mov): Likewise.
853 (aarch64_ins_sve_shlimm): Likewise.
854 (aarch64_ins_sve_shrimm): Likewise.
855 * aarch64-asm-2.c: Regenerate.
856 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
857 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
858 * aarch64-dis.c (decode_limm): New function, split out from...
859 (aarch64_ext_limm): ...here.
860 (aarch64_ext_inv_limm): New function.
861 (decode_sve_aimm): Likewise.
862 (aarch64_ext_sve_aimm): Likewise.
863 (aarch64_ext_sve_asimm): Likewise.
864 (aarch64_ext_sve_limm_mov): Likewise.
865 (aarch64_top_bit): Likewise.
866 (aarch64_ext_sve_shlimm): Likewise.
867 (aarch64_ext_sve_shrimm): Likewise.
868 * aarch64-dis-2.c: Regenerate.
869
870 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
871
872 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
873 operands.
874 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
875 the AARCH64_MOD_MUL_VL entry.
876 (value_aligned_p): Cope with non-power-of-two alignments.
877 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
878 (print_immediate_offset_address): Likewise.
879 (aarch64_print_operand): Likewise.
880 * aarch64-opc-2.c: Regenerate.
881 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
882 (ins_sve_addr_ri_s9xvl): New inserters.
883 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
884 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
885 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
886 * aarch64-asm-2.c: Regenerate.
887 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
888 (ext_sve_addr_ri_s9xvl): New extractors.
889 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
890 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
891 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
892 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
893 * aarch64-dis-2.c: Regenerate.
894
895 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
896
897 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
898 address operands.
899 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
900 (FLD_SVE_xs_22): New aarch64_field_kinds.
901 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
902 (get_operand_specific_data): New function.
903 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
904 FLD_SVE_xs_14 and FLD_SVE_xs_22.
905 (operand_general_constraint_met_p): Handle the new SVE address
906 operands.
907 (sve_reg): New array.
908 (get_addr_sve_reg_name): New function.
909 (aarch64_print_operand): Handle the new SVE address operands.
910 * aarch64-opc-2.c: Regenerate.
911 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
912 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
913 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
914 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
915 (aarch64_ins_sve_addr_rr_lsl): Likewise.
916 (aarch64_ins_sve_addr_rz_xtw): Likewise.
917 (aarch64_ins_sve_addr_zi_u5): Likewise.
918 (aarch64_ins_sve_addr_zz): Likewise.
919 (aarch64_ins_sve_addr_zz_lsl): Likewise.
920 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
921 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
922 * aarch64-asm-2.c: Regenerate.
923 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
924 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
925 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
926 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
927 (aarch64_ext_sve_addr_ri_u6): Likewise.
928 (aarch64_ext_sve_addr_rr_lsl): Likewise.
929 (aarch64_ext_sve_addr_rz_xtw): Likewise.
930 (aarch64_ext_sve_addr_zi_u5): Likewise.
931 (aarch64_ext_sve_addr_zz): Likewise.
932 (aarch64_ext_sve_addr_zz_lsl): Likewise.
933 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
934 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
935 * aarch64-dis-2.c: Regenerate.
936
937 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
938
939 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
940 AARCH64_OPND_SVE_PATTERN_SCALED.
941 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
942 * aarch64-opc.c (fields): Add a corresponding entry.
943 (set_multiplier_out_of_range_error): New function.
944 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
945 (operand_general_constraint_met_p): Handle
946 AARCH64_OPND_SVE_PATTERN_SCALED.
947 (print_register_offset_address): Use PRIi64 to print the
948 shift amount.
949 (aarch64_print_operand): Likewise. Handle
950 AARCH64_OPND_SVE_PATTERN_SCALED.
951 * aarch64-opc-2.c: Regenerate.
952 * aarch64-asm.h (ins_sve_scale): New inserter.
953 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
954 * aarch64-asm-2.c: Regenerate.
955 * aarch64-dis.h (ext_sve_scale): New inserter.
956 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
957 * aarch64-dis-2.c: Regenerate.
958
959 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
960
961 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
962 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
963 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
964 (FLD_SVE_prfop): Likewise.
965 * aarch64-opc.c: Include libiberty.h.
966 (aarch64_sve_pattern_array): New variable.
967 (aarch64_sve_prfop_array): Likewise.
968 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
969 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
970 AARCH64_OPND_SVE_PRFOP.
971 * aarch64-asm-2.c: Regenerate.
972 * aarch64-dis-2.c: Likewise.
973 * aarch64-opc-2.c: Likewise.
974
975 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
976
977 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
978 AARCH64_OPND_QLF_P_[ZM].
979 (aarch64_print_operand): Print /z and /m where appropriate.
980
981 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
982
983 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
984 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
985 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
986 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
987 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
988 * aarch64-opc.c (fields): Add corresponding entries here.
989 (operand_general_constraint_met_p): Check that SVE register lists
990 have the correct length. Check the ranges of SVE index registers.
991 Check for cases where p8-p15 are used in 3-bit predicate fields.
992 (aarch64_print_operand): Handle the new SVE operands.
993 * aarch64-opc-2.c: Regenerate.
994 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
995 * aarch64-asm.c (aarch64_ins_sve_index): New function.
996 (aarch64_ins_sve_reglist): Likewise.
997 * aarch64-asm-2.c: Regenerate.
998 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
999 * aarch64-dis.c (aarch64_ext_sve_index): New function.
1000 (aarch64_ext_sve_reglist): Likewise.
1001 * aarch64-dis-2.c: Regenerate.
1002
1003 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1004
1005 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
1006 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
1007 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
1008 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
1009 tied operands.
1010
1011 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1012
1013 * aarch64-opc.c (get_offset_int_reg_name): New function.
1014 (print_immediate_offset_address): Likewise.
1015 (print_register_offset_address): Take the base and offset
1016 registers as parameters.
1017 (aarch64_print_operand): Update caller accordingly. Use
1018 print_immediate_offset_address.
1019
1020 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1021
1022 * aarch64-opc.c (BANK): New macro.
1023 (R32, R64): Take a register number as argument
1024 (int_reg): Use BANK.
1025
1026 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1027
1028 * aarch64-opc.c (print_register_list): Add a prefix parameter.
1029 (aarch64_print_operand): Update accordingly.
1030
1031 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1032
1033 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
1034 for FPIMM.
1035 * aarch64-asm.h (ins_fpimm): New inserter.
1036 * aarch64-asm.c (aarch64_ins_fpimm): New function.
1037 * aarch64-asm-2.c: Regenerate.
1038 * aarch64-dis.h (ext_fpimm): New extractor.
1039 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
1040 (aarch64_ext_fpimm): New function.
1041 * aarch64-dis-2.c: Regenerate.
1042
1043 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1044
1045 * aarch64-asm.c: Include libiberty.h.
1046 (insert_fields): New function.
1047 (aarch64_ins_imm): Use it.
1048 * aarch64-dis.c (extract_fields): New function.
1049 (aarch64_ext_imm): Use it.
1050
1051 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1052
1053 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
1054 with an esize parameter.
1055 (operand_general_constraint_met_p): Update accordingly.
1056 Fix misindented code.
1057 * aarch64-asm.c (aarch64_ins_limm): Update call to
1058 aarch64_logical_immediate_p.
1059
1060 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1061
1062 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
1063
1064 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1065
1066 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
1067
1068 2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
1069
1070 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
1071
1072 2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
1073
1074 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
1075 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
1076 xor3>: Delete mnemonics.
1077 <cp_abort>: Rename mnemonic from ...
1078 <cpabort>: ...to this.
1079 <setb>: Change to a X form instruction.
1080 <sync>: Change to 1 operand form.
1081 <copy>: Delete mnemonic.
1082 <copy_first>: Rename mnemonic from ...
1083 <copy>: ...to this.
1084 <paste, paste.>: Delete mnemonics.
1085 <paste_last>: Rename mnemonic from ...
1086 <paste.>: ...to this.
1087
1088 2016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
1089
1090 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
1091
1092 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1093
1094 * s390-mkopc.c (main): Support alternate arch strings.
1095
1096 2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
1097
1098 * s390-opc.txt: Fix kmctr instruction type.
1099
1100 2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
1101
1102 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
1103 * i386-init.h: Regenerated.
1104
1105 2016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
1106
1107 * opcodes/arc-dis.c (print_insn_arc): Changed.
1108
1109 2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
1110
1111 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
1112 camellia_fl.
1113
1114 2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
1115
1116 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
1117 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
1118 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
1119
1120 2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
1121
1122 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
1123 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
1124 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
1125 PREFIX_MOD_3_0FAE_REG_4.
1126 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
1127 PREFIX_MOD_3_0FAE_REG_4.
1128 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
1129 (cpu_flags): Add CpuPTWRITE.
1130 * i386-opc.h (CpuPTWRITE): New.
1131 (i386_cpu_flags): Add cpuptwrite.
1132 * i386-opc.tbl: Add ptwrite instruction.
1133 * i386-init.h: Regenerated.
1134 * i386-tbl.h: Likewise.
1135
1136 2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
1137
1138 * arc-dis.h: Wrap around in extern "C".
1139
1140 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1141
1142 * aarch64-tbl.h (V8_2_INSN): New macro.
1143 (aarch64_opcode_table): Use it.
1144
1145 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1146
1147 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
1148 CORE_INSN, __FP_INSN and SIMD_INSN.
1149
1150 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1151
1152 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
1153 (aarch64_opcode_table): Update uses accordingly.
1154
1155 2016-07-25 Andrew Jenner <andrew@codesourcery.com>
1156 Kwok Cheung Yeung <kcy@codesourcery.com>
1157
1158 opcodes/
1159 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
1160 'e_cmplwi' to 'e_cmpli' instead.
1161 (OPVUPRT, OPVUPRT_MASK): Define.
1162 (powerpc_opcodes): Add E200Z4 insns.
1163 (vle_opcodes): Add context save/restore insns.
1164
1165 2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
1166
1167 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
1168 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
1169 "j".
1170
1171 2016-07-27 Graham Markall <graham.markall@embecosm.com>
1172
1173 * arc-nps400-tbl.h: Change block comments to GNU format.
1174 * arc-dis.c: Add new globals addrtypenames,
1175 addrtypenames_max, and addtypeunknown.
1176 (get_addrtype): New function.
1177 (print_insn_arc): Print colons and address types when
1178 required.
1179 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1180 define insert and extract functions for all address types.
1181 (arc_operands): Add operands for colon and all address
1182 types.
1183 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1184 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1185 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1186 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1187 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1188 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1189
1190 2016-07-21 H.J. Lu <hongjiu.lu@intel.com>
1191
1192 * configure: Regenerated.
1193
1194 2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
1195
1196 * arc-dis.c (skipclass): New structure.
1197 (decodelist): New variable.
1198 (is_compatible_p): New function.
1199 (new_element): Likewise.
1200 (skip_class_p): Likewise.
1201 (find_format_from_table): Use skip_class_p function.
1202 (find_format): Decode first the extension instructions.
1203 (print_insn_arc): Select either ARCEM or ARCHS based on elf
1204 e_flags.
1205 (parse_option): New function.
1206 (parse_disassembler_options): Likewise.
1207 (print_arc_disassembler_options): Likewise.
1208 (print_insn_arc): Use parse_disassembler_options function. Proper
1209 select ARCv2 cpu variant.
1210 * disassemble.c (disassembler_usage): Add ARC disassembler
1211 options.
1212
1213 2016-07-13 Maciej W. Rozycki <macro@imgtec.com>
1214
1215 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1216 annotation from the "nal" entry and reorder it beyond "bltzal".
1217
1218 2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
1219
1220 * sparc-opc.c (ldtxa): New macro.
1221 (sparc_opcodes): Use the macro defined above to add entries for
1222 the LDTXA instructions.
1223 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1224 instruction.
1225
1226 2016-07-07 James Bowman <james.bowman@ftdichip.com>
1227
1228 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1229 and "jmpc".
1230
1231 2016-07-01 Jan Beulich <jbeulich@suse.com>
1232
1233 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1234 (movzb): Adjust to cover all permitted suffixes.
1235 (movzw): New.
1236 * i386-tbl.h: Re-generate.
1237
1238 2016-07-01 Jan Beulich <jbeulich@suse.com>
1239
1240 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1241 (lgdt): Remove Tbyte from non-64-bit variant.
1242 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1243 xsaves64, xsavec64): Remove Disp16.
1244 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1245 Remove Disp32S from non-64-bit variants. Remove Disp16 from
1246 64-bit variants.
1247 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1248 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1249 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1250 64-bit variants.
1251 * i386-tbl.h: Re-generate.
1252
1253 2016-07-01 Jan Beulich <jbeulich@suse.com>
1254
1255 * i386-opc.tbl (xlat): Remove RepPrefixOk.
1256 * i386-tbl.h: Re-generate.
1257
1258 2016-06-30 Yao Qi <yao.qi@linaro.org>
1259
1260 * arm-dis.c (print_insn): Fix typo in comment.
1261
1262 2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
1263
1264 * aarch64-opc.c (operand_general_constraint_met_p): Check the
1265 range of ldst_elemlist operands.
1266 (print_register_list): Use PRIi64 to print the index.
1267 (aarch64_print_operand): Likewise.
1268
1269 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1270
1271 * mcore-opc.h: Remove sentinal.
1272 * mcore-dis.c (print_insn_mcore): Adjust.
1273
1274 2016-06-23 Graham Markall <graham.markall@embecosm.com>
1275
1276 * arc-opc.c: Correct description of availability of NPS400
1277 features.
1278
1279 2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
1280
1281 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1282 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1283 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1284 xor3>: New mnemonics.
1285 <setb>: Change to a VX form instruction.
1286 (insert_sh6): Add support for rldixor.
1287 (extract_sh6): Likewise.
1288
1289 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1290
1291 * arc-ext.h: Wrap in extern C.
1292
1293 2016-06-21 Graham Markall <graham.markall@embecosm.com>
1294
1295 * arc-dis.c (arc_insn_length): Add comment on instruction length.
1296 Use same method for determining instruction length on ARC700 and
1297 NPS-400.
1298 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1299 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1300 with the NPS400 subclass.
1301 * arc-opc.c: Likewise.
1302
1303 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1304
1305 * sparc-opc.c (rdasr): New macro.
1306 (wrasr): Likewise.
1307 (rdpr): Likewise.
1308 (wrpr): Likewise.
1309 (rdhpr): Likewise.
1310 (wrhpr): Likewise.
1311 (sparc_opcodes): Use the macros above to fix and expand the
1312 definition of read/write instructions from/to
1313 asr/privileged/hyperprivileged instructions.
1314 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1315 %hva_mask_nz. Prefer softint_set and softint_clear over
1316 set_softint and clear_softint.
1317 (print_insn_sparc): Support %ver in Rd.
1318
1319 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1320
1321 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1322 architecture according to the hardware capabilities they require.
1323
1324 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1325
1326 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1327 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1328 bfd_mach_sparc_v9{c,d,e,v,m}.
1329 * sparc-opc.c (MASK_V9C): Define.
1330 (MASK_V9D): Likewise.
1331 (MASK_V9E): Likewise.
1332 (MASK_V9V): Likewise.
1333 (MASK_V9M): Likewise.
1334 (v6): Add MASK_V9{C,D,E,V,M}.
1335 (v6notlet): Likewise.
1336 (v7): Likewise.
1337 (v8): Likewise.
1338 (v9): Likewise.
1339 (v9andleon): Likewise.
1340 (v9a): Likewise.
1341 (v9b): Likewise.
1342 (v9c): Define.
1343 (v9d): Likewise.
1344 (v9e): Likewise.
1345 (v9v): Likewise.
1346 (v9m): Likewise.
1347 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1348
1349 2016-06-15 Nick Clifton <nickc@redhat.com>
1350
1351 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1352 constants to match expected behaviour.
1353 (nds32_parse_opcode): Likewise. Also for whitespace.
1354
1355 2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
1356
1357 * arc-opc.c (extract_rhv1): Extract value from insn.
1358
1359 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1360
1361 * arc-nps400-tbl.h: Add ldbit instruction.
1362 * arc-opc.c: Add flag classes required for ldbit.
1363
1364 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1365
1366 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1367 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1368 support the above instructions.
1369
1370 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1371
1372 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1373 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1374 csma, cbba, zncv, and hofs.
1375 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1376 support the above instructions.
1377
1378 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1379
1380 * arc-nps400-tbl.h: Add andab and orab instructions.
1381
1382 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1383
1384 * arc-nps400-tbl.h: Add addl-like instructions.
1385
1386 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1387
1388 * arc-nps400-tbl.h: Add mxb and imxb instructions.
1389
1390 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1391
1392 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1393 instructions.
1394
1395 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1396
1397 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1398 variable.
1399 (init_disasm): Handle new command line option "insnlength".
1400 (print_s390_disassembler_options): Mention new option in help
1401 output.
1402 (print_insn_s390): Use the encoded insn length when dumping
1403 unknown instructions.
1404
1405 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1406
1407 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1408 to the address and set as symbol address for LDS/ STS immediate operands.
1409
1410 2016-06-07 Alan Modra <amodra@gmail.com>
1411
1412 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1413 cpu for "vle" to e500.
1414 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1415 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1416 (PPCNONE): Delete, substitute throughout.
1417 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1418 except for major opcode 4 and 31.
1419 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1420
1421 2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1422
1423 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1424 ARM_EXT_RAS in relevant entries.
1425
1426 2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1427
1428 PR binutils/20196
1429 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1430 opcodes for E6500.
1431
1432 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1433
1434 PR binutis/18386
1435 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1436 (indir_v_mode): New.
1437 Add comments for '&'.
1438 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1439 (putop): Handle '&'.
1440 (intel_operand_size): Handle indir_v_mode.
1441 (OP_E_register): Likewise.
1442 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1443 64-bit indirect call/jmp for AMD64.
1444 * i386-tbl.h: Regenerated
1445
1446 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1447
1448 * arc-dis.c (struct arc_operand_iterator): New structure.
1449 (find_format_from_table): All the old content from find_format,
1450 with some minor adjustments, and parameter renaming.
1451 (find_format_long_instructions): New function.
1452 (find_format): Rewritten.
1453 (arc_insn_length): Add LSB parameter.
1454 (extract_operand_value): New function.
1455 (operand_iterator_next): New function.
1456 (print_insn_arc): Use new functions to find opcode, and iterator
1457 over operands.
1458 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1459 (extract_nps_3bit_dst_short): New function.
1460 (insert_nps_3bit_src2_short): New function.
1461 (extract_nps_3bit_src2_short): New function.
1462 (insert_nps_bitop1_size): New function.
1463 (extract_nps_bitop1_size): New function.
1464 (insert_nps_bitop2_size): New function.
1465 (extract_nps_bitop2_size): New function.
1466 (insert_nps_bitop_mod4_msb): New function.
1467 (extract_nps_bitop_mod4_msb): New function.
1468 (insert_nps_bitop_mod4_lsb): New function.
1469 (extract_nps_bitop_mod4_lsb): New function.
1470 (insert_nps_bitop_dst_pos3_pos4): New function.
1471 (extract_nps_bitop_dst_pos3_pos4): New function.
1472 (insert_nps_bitop_ins_ext): New function.
1473 (extract_nps_bitop_ins_ext): New function.
1474 (arc_operands): Add new operands.
1475 (arc_long_opcodes): New global array.
1476 (arc_num_long_opcodes): New global.
1477 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1478
1479 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1480
1481 * nds32-asm.h: Add extern "C".
1482 * sh-opc.h: Likewise.
1483
1484 2016-06-01 Graham Markall <graham.markall@embecosm.com>
1485
1486 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1487 0,b,limm to the rflt instruction.
1488
1489 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1490
1491 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1492 constant.
1493
1494 2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1495
1496 PR gas/20145
1497 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1498 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1499 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1500 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1501 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1502 * i386-init.h: Regenerated.
1503
1504 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1505
1506 PR gas/20145
1507 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1508 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1509 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1510 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1511 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1512 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1513 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1514 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1515 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1516 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1517 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1518 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1519 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1520 CpuRegMask for AVX512.
1521 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1522 and CpuRegMask.
1523 (set_bitfield_from_cpu_flag_init): New function.
1524 (set_bitfield): Remove const on f. Call
1525 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1526 * i386-opc.h (CpuRegMMX): New.
1527 (CpuRegXMM): Likewise.
1528 (CpuRegYMM): Likewise.
1529 (CpuRegZMM): Likewise.
1530 (CpuRegMask): Likewise.
1531 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1532 and cpuregmask.
1533 * i386-init.h: Regenerated.
1534 * i386-tbl.h: Likewise.
1535
1536 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1537
1538 PR gas/20154
1539 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1540 (opcode_modifiers): Add AMD64 and Intel64.
1541 (main): Properly verify CpuMax.
1542 * i386-opc.h (CpuAMD64): Removed.
1543 (CpuIntel64): Likewise.
1544 (CpuMax): Set to CpuNo64.
1545 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1546 (AMD64): New.
1547 (Intel64): Likewise.
1548 (i386_opcode_modifier): Add amd64 and intel64.
1549 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1550 on call and jmp.
1551 * i386-init.h: Regenerated.
1552 * i386-tbl.h: Likewise.
1553
1554 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1555
1556 PR gas/20154
1557 * i386-gen.c (main): Fail if CpuMax is incorrect.
1558 * i386-opc.h (CpuMax): Set to CpuIntel64.
1559 * i386-tbl.h: Regenerated.
1560
1561 2016-05-27 Nick Clifton <nickc@redhat.com>
1562
1563 PR target/20150
1564 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1565 (msp430dis_opcode_unsigned): New function.
1566 (msp430dis_opcode_signed): New function.
1567 (msp430_singleoperand): Use the new opcode reading functions.
1568 Only disassenmble bytes if they were successfully read.
1569 (msp430_doubleoperand): Likewise.
1570 (msp430_branchinstr): Likewise.
1571 (msp430x_callx_instr): Likewise.
1572 (print_insn_msp430): Check that it is safe to read bytes before
1573 attempting disassembly. Use the new opcode reading functions.
1574
1575 2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1576
1577 * ppc-opc.c (CY): New define. Document it.
1578 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1579
1580 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1581
1582 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1583 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1584 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1585 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1586 CPU_ANY_AVX_FLAGS.
1587 * i386-init.h: Regenerated.
1588
1589 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1590
1591 PR gas/20141
1592 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1593 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1594 * i386-init.h: Regenerated.
1595
1596 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1597
1598 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1599 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1600 * i386-init.h: Regenerated.
1601
1602 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1603
1604 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1605 information.
1606 (print_insn_arc): Set insn_type information.
1607 * arc-opc.c (C_CC): Add F_CLASS_COND.
1608 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1609 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1610 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1611 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1612 (brne, brne_s, jeq_s, jne_s): Likewise.
1613
1614 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1615
1616 * arc-tbl.h (neg): New instruction variant.
1617
1618 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1619
1620 * arc-dis.c (find_format, find_format, get_auxreg)
1621 (print_insn_arc): Changed.
1622 * arc-ext.h (INSERT_XOP): Likewise.
1623
1624 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1625
1626 * tic54x-dis.c (sprint_mmr): Adjust.
1627 * tic54x-opc.c: Likewise.
1628
1629 2016-05-19 Alan Modra <amodra@gmail.com>
1630
1631 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1632
1633 2016-05-19 Alan Modra <amodra@gmail.com>
1634
1635 * ppc-opc.c: Formatting.
1636 (NSISIGNOPT): Define.
1637 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1638
1639 2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1640
1641 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1642 replacing references to `micromips_ase' throughout.
1643 (_print_insn_mips): Don't use file-level microMIPS annotation to
1644 determine the disassembly mode with the symbol table.
1645
1646 2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1647
1648 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1649
1650 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1651
1652 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1653 mips64r6.
1654 * mips-opc.c (D34): New macro.
1655 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1656
1657 2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1658
1659 * i386-dis.c (prefix_table): Add RDPID instruction.
1660 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1661 (cpu_flags): Add RDPID bitfield.
1662 * i386-opc.h (enum): Add RDPID element.
1663 (i386_cpu_flags): Add RDPID field.
1664 * i386-opc.tbl: Add RDPID instruction.
1665 * i386-init.h: Regenerate.
1666 * i386-tbl.h: Regenerate.
1667
1668 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1669
1670 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1671 branch type of a symbol.
1672 (print_insn): Likewise.
1673
1674 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1675
1676 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1677 Mainline Security Extensions instructions.
1678 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1679 Extensions instructions.
1680 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1681 instructions.
1682 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1683 special registers.
1684
1685 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1686
1687 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1688
1689 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1690
1691 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1692 (arcExtMap_genOpcode): Likewise.
1693 * arc-opc.c (arg_32bit_rc): Define new variable.
1694 (arg_32bit_u6): Likewise.
1695 (arg_32bit_limm): Likewise.
1696
1697 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1698
1699 * aarch64-gen.c (VERIFIER): Define.
1700 * aarch64-opc.c (VERIFIER): Define.
1701 (verify_ldpsw): Use static linkage.
1702 * aarch64-opc.h (verify_ldpsw): Remove.
1703 * aarch64-tbl.h: Use VERIFIER for verifiers.
1704
1705 2016-04-28 Nick Clifton <nickc@redhat.com>
1706
1707 PR target/19722
1708 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1709 * aarch64-opc.c (verify_ldpsw): New function.
1710 * aarch64-opc.h (verify_ldpsw): New prototype.
1711 * aarch64-tbl.h: Add initialiser for verifier field.
1712 (LDPSW): Set verifier to verify_ldpsw.
1713
1714 2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1715
1716 PR binutils/19983
1717 PR binutils/19984
1718 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1719 smaller than address size.
1720
1721 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1722
1723 * alpha-dis.c: Regenerate.
1724 * crx-dis.c: Likewise.
1725 * disassemble.c: Likewise.
1726 * epiphany-opc.c: Likewise.
1727 * fr30-opc.c: Likewise.
1728 * frv-opc.c: Likewise.
1729 * ip2k-opc.c: Likewise.
1730 * iq2000-opc.c: Likewise.
1731 * lm32-opc.c: Likewise.
1732 * lm32-opinst.c: Likewise.
1733 * m32c-opc.c: Likewise.
1734 * m32r-opc.c: Likewise.
1735 * m32r-opinst.c: Likewise.
1736 * mep-opc.c: Likewise.
1737 * mt-opc.c: Likewise.
1738 * or1k-opc.c: Likewise.
1739 * or1k-opinst.c: Likewise.
1740 * tic80-opc.c: Likewise.
1741 * xc16x-opc.c: Likewise.
1742 * xstormy16-opc.c: Likewise.
1743
1744 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1745
1746 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1747 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1748 calcsd, and calcxd instructions.
1749 * arc-opc.c (insert_nps_bitop_size): Delete.
1750 (extract_nps_bitop_size): Delete.
1751 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1752 (extract_nps_qcmp_m3): Define.
1753 (extract_nps_qcmp_m2): Define.
1754 (extract_nps_qcmp_m1): Define.
1755 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1756 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1757 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1758 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1759 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1760 NPS_QCMP_M3.
1761
1762 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1763
1764 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1765
1766 2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1767
1768 * Makefile.in: Regenerated with automake 1.11.6.
1769 * aclocal.m4: Likewise.
1770
1771 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1772
1773 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1774 instructions.
1775 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1776 (extract_nps_cmem_uimm16): New function.
1777 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1778
1779 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1780
1781 * arc-dis.c (arc_insn_length): New function.
1782 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1783 (find_format): Change insnLen parameter to unsigned.
1784
1785 2016-04-13 Nick Clifton <nickc@redhat.com>
1786
1787 PR target/19937
1788 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1789 the LD.B and LD.BU instructions.
1790
1791 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1792
1793 * arc-dis.c (find_format): Check for extension flags.
1794 (print_flags): New function.
1795 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1796 .extAuxRegister.
1797 * arc-ext.c (arcExtMap_coreRegName): Use
1798 LAST_EXTENSION_CORE_REGISTER.
1799 (arcExtMap_coreReadWrite): Likewise.
1800 (dump_ARC_extmap): Update printing.
1801 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1802 (arc_aux_regs): Add cpu field.
1803 * arc-regs.h: Add cpu field, lower case name aux registers.
1804
1805 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1806
1807 * arc-tbl.h: Add rtsc, sleep with no arguments.
1808
1809 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1810
1811 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1812 Initialize.
1813 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1814 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1815 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1816 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1817 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1818 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1819 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1820 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1821 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1822 (arc_opcode arc_opcodes): Null terminate the array.
1823 (arc_num_opcodes): Remove.
1824 * arc-ext.h (INSERT_XOP): Define.
1825 (extInstruction_t): Likewise.
1826 (arcExtMap_instName): Delete.
1827 (arcExtMap_insn): New function.
1828 (arcExtMap_genOpcode): Likewise.
1829 * arc-ext.c (ExtInstruction): Remove.
1830 (create_map): Zero initialize instruction fields.
1831 (arcExtMap_instName): Remove.
1832 (arcExtMap_insn): New function.
1833 (dump_ARC_extmap): More info while debuging.
1834 (arcExtMap_genOpcode): New function.
1835 * arc-dis.c (find_format): New function.
1836 (print_insn_arc): Use find_format.
1837 (arc_get_disassembler): Enable dump_ARC_extmap only when
1838 debugging.
1839
1840 2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1841
1842 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1843 instruction bits out.
1844
1845 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1846
1847 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1848 * arc-opc.c (arc_flag_operands): Add new flags.
1849 (arc_flag_classes): Add new classes.
1850
1851 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1852
1853 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1854
1855 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1856
1857 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1858 encode1, rflt, crc16, and crc32 instructions.
1859 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1860 (arc_flag_classes): Add C_NPS_R.
1861 (insert_nps_bitop_size_2b): New function.
1862 (extract_nps_bitop_size_2b): Likewise.
1863 (insert_nps_bitop_uimm8): Likewise.
1864 (extract_nps_bitop_uimm8): Likewise.
1865 (arc_operands): Add new operand entries.
1866
1867 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1868
1869 * arc-regs.h: Add a new subclass field. Add double assist
1870 accumulator register values.
1871 * arc-tbl.h: Use DPA subclass to mark the double assist
1872 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1873 * arc-opc.c (RSP): Define instead of SP.
1874 (arc_aux_regs): Add the subclass field.
1875
1876 2016-04-05 Jiong Wang <jiong.wang@arm.com>
1877
1878 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1879
1880 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
1881
1882 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1883 NPS_R_SRC1.
1884
1885 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1886
1887 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1888 issues. No functional changes.
1889
1890 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1891
1892 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1893 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1894 (RTT): Remove duplicate.
1895 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1896 (PCT_CONFIG*): Remove.
1897 (D1L, D1H, D2H, D2L): Define.
1898
1899 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1900
1901 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1902
1903 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1904
1905 * arc-tbl.h (invld07): Remove.
1906 * arc-ext-tbl.h: New file.
1907 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1908 * arc-opc.c (arc_opcodes): Add ext-tbl include.
1909
1910 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1911
1912 Fix -Wstack-usage warnings.
1913 * aarch64-dis.c (print_operands): Substitute size.
1914 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1915
1916 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1917
1918 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1919 to get a proper diagnostic when an invalid ASR register is used.
1920
1921 2016-03-22 Nick Clifton <nickc@redhat.com>
1922
1923 * configure: Regenerate.
1924
1925 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1926
1927 * arc-nps400-tbl.h: New file.
1928 * arc-opc.c: Add top level comment.
1929 (insert_nps_3bit_dst): New function.
1930 (extract_nps_3bit_dst): New function.
1931 (insert_nps_3bit_src2): New function.
1932 (extract_nps_3bit_src2): New function.
1933 (insert_nps_bitop_size): New function.
1934 (extract_nps_bitop_size): New function.
1935 (arc_flag_operands): Add nps400 entries.
1936 (arc_flag_classes): Add nps400 entries.
1937 (arc_operands): Add nps400 entries.
1938 (arc_opcodes): Add nps400 include.
1939
1940 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1941
1942 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1943 the new class enum values.
1944
1945 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1946
1947 * arc-dis.c (print_insn_arc): Handle nps400.
1948
1949 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1950
1951 * arc-opc.c (BASE): Delete.
1952
1953 2016-03-18 Nick Clifton <nickc@redhat.com>
1954
1955 PR target/19721
1956 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1957 of MOV insn that aliases an ORR insn.
1958
1959 2016-03-16 Jiong Wang <jiong.wang@arm.com>
1960
1961 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1962
1963 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1964
1965 * mcore-opc.h: Add const qualifiers.
1966 * microblaze-opc.h (struct op_code_struct): Likewise.
1967 * sh-opc.h: Likewise.
1968 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1969 (tic4x_print_op): Likewise.
1970
1971 2016-03-02 Alan Modra <amodra@gmail.com>
1972
1973 * or1k-desc.h: Regenerate.
1974 * fr30-ibld.c: Regenerate.
1975 * rl78-decode.c: Regenerate.
1976
1977 2016-03-01 Nick Clifton <nickc@redhat.com>
1978
1979 PR target/19747
1980 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1981
1982 2016-02-24 Renlin Li <renlin.li@arm.com>
1983
1984 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1985 (print_insn_coprocessor): Support fp16 instructions.
1986
1987 2016-02-24 Renlin Li <renlin.li@arm.com>
1988
1989 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1990 vminnm, vrint(mpna).
1991
1992 2016-02-24 Renlin Li <renlin.li@arm.com>
1993
1994 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1995 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1996
1997 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1998
1999 * i386-dis.c (print_insn): Parenthesize expression to prevent
2000 truncated addresses.
2001 (OP_J): Likewise.
2002
2003 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
2004 Janek van Oirschot <jvanoirs@synopsys.com>
2005
2006 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
2007 variable.
2008
2009 2016-02-04 Nick Clifton <nickc@redhat.com>
2010
2011 PR target/19561
2012 * msp430-dis.c (print_insn_msp430): Add a special case for
2013 decoding an RRC instruction with the ZC bit set in the extension
2014 word.
2015
2016 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
2017
2018 * cgen-ibld.in (insert_normal): Rework calculation of shift.
2019 * epiphany-ibld.c: Regenerate.
2020 * fr30-ibld.c: Regenerate.
2021 * frv-ibld.c: Regenerate.
2022 * ip2k-ibld.c: Regenerate.
2023 * iq2000-ibld.c: Regenerate.
2024 * lm32-ibld.c: Regenerate.
2025 * m32c-ibld.c: Regenerate.
2026 * m32r-ibld.c: Regenerate.
2027 * mep-ibld.c: Regenerate.
2028 * mt-ibld.c: Regenerate.
2029 * or1k-ibld.c: Regenerate.
2030 * xc16x-ibld.c: Regenerate.
2031 * xstormy16-ibld.c: Regenerate.
2032
2033 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
2034
2035 * epiphany-dis.c: Regenerated from latest cpu files.
2036
2037 2016-02-01 Michael McConville <mmcco@mykolab.com>
2038
2039 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
2040 test bit.
2041
2042 2016-01-25 Renlin Li <renlin.li@arm.com>
2043
2044 * arm-dis.c (mapping_symbol_for_insn): New function.
2045 (find_ifthen_state): Call mapping_symbol_for_insn().
2046
2047 2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
2048
2049 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
2050 of MSR UAO immediate operand.
2051
2052 2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
2053
2054 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
2055 instruction support.
2056
2057 2016-01-17 Alan Modra <amodra@gmail.com>
2058
2059 * configure: Regenerate.
2060
2061 2016-01-14 Nick Clifton <nickc@redhat.com>
2062
2063 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
2064 instructions that can support stack pointer operations.
2065 * rl78-decode.c: Regenerate.
2066 * rl78-dis.c: Fix display of stack pointer in MOVW based
2067 instructions.
2068
2069 2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
2070
2071 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
2072 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
2073 erxtatus_el1 and erxaddr_el1.
2074
2075 2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
2076
2077 * arm-dis.c (arm_opcodes): Add "esb".
2078 (thumb_opcodes): Likewise.
2079
2080 2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
2081
2082 * ppc-opc.c <xscmpnedp>: Delete.
2083 <xvcmpnedp>: Likewise.
2084 <xvcmpnedp.>: Likewise.
2085 <xvcmpnesp>: Likewise.
2086 <xvcmpnesp.>: Likewise.
2087
2088 2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
2089
2090 PR gas/13050
2091 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
2092 addition to ISA_A.
2093
2094 2016-01-01 Alan Modra <amodra@gmail.com>
2095
2096 Update year range in copyright notice of all files.
2097
2098 For older changes see ChangeLog-2015
2099 \f
2100 Copyright (C) 2016 Free Software Foundation, Inc.
2101
2102 Copying and distribution of this file, with or without modification,
2103 are permitted in any medium without royalty provided the copyright
2104 notice and this notice are preserved.
2105
2106 Local Variables:
2107 mode: change-log
2108 left-margin: 8
2109 fill-column: 74
2110 version-control: never
2111 End: