opcodes/ChangeLog

   1 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
   2
   3         * s390-dis.c (option_use_insn_len_bits_p): New file scope
   4         variable.
   5         (init_disasm): Handle new command line option "insnlength".
   6         (print_s390_disassembler_options): Mention new option in help
   7         output.
   8         (print_insn_s390): Use the encoded insn length when dumping
   9         unknown instructions.
  10
  11 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
  12
  13         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
  14          to the address and set as symbol address for LDS/ STS immediate operands.
  15
  16 2016-06-07  Alan Modra  <amodra@gmail.com>
  17
  18         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
  19         cpu for "vle" to e500.
  20         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
  21         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
  22         (PPCNONE): Delete, substitute throughout.
  23         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
  24         except for major opcode 4 and 31.
  25         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
  26
  27 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
  28
  29         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
  30         ARM_EXT_RAS in relevant entries.
  31
  32 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
  33
  34         PR binutils/20196
  35         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
  36         opcodes for E6500.
  37
  38 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
  39
  40         PR binutis/18386
  41         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
  42         (indir_v_mode): New.
  43         Add comments for '&'.
  44         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
  45         (putop): Handle '&'.
  46         (intel_operand_size): Handle indir_v_mode.
  47         (OP_E_register): Likewise.
  48         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
  49         64-bit indirect call/jmp for AMD64.
  50         * i386-tbl.h: Regenerated
  51
  52 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
  53
  54         * arc-dis.c (struct arc_operand_iterator): New structure.
  55         (find_format_from_table): All the old content from find_format,
  56         with some minor adjustments, and parameter renaming.
  57         (find_format_long_instructions): New function.
  58         (find_format): Rewritten.
  59         (arc_insn_length): Add LSB parameter.
  60         (extract_operand_value): New function.
  61         (operand_iterator_next): New function.
  62         (print_insn_arc): Use new functions to find opcode, and iterator
  63         over operands.
  64         * arc-opc.c (insert_nps_3bit_dst_short): New function.
  65         (extract_nps_3bit_dst_short): New function.
  66         (insert_nps_3bit_src2_short): New function.
  67         (extract_nps_3bit_src2_short): New function.
  68         (insert_nps_bitop1_size): New function.
  69         (extract_nps_bitop1_size): New function.
  70         (insert_nps_bitop2_size): New function.
  71         (extract_nps_bitop2_size): New function.
  72         (insert_nps_bitop_mod4_msb): New function.
  73         (extract_nps_bitop_mod4_msb): New function.
  74         (insert_nps_bitop_mod4_lsb): New function.
  75         (extract_nps_bitop_mod4_lsb): New function.
  76         (insert_nps_bitop_dst_pos3_pos4): New function.
  77         (extract_nps_bitop_dst_pos3_pos4): New function.
  78         (insert_nps_bitop_ins_ext): New function.
  79         (extract_nps_bitop_ins_ext): New function.
  80         (arc_operands): Add new operands.
  81         (arc_long_opcodes): New global array.
  82         (arc_num_long_opcodes): New global.
  83         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
  84
  85 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
  86
  87         * nds32-asm.h: Add extern "C".
  88         * sh-opc.h: Likewise.
  89
  90 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
  91
  92         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
  93         0,b,limm to the rflt instruction.
  94
  95 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
  96
  97         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
  98         constant.
  99
 100 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
 101
 102         PR gas/20145
 103         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
 104         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
 105         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
 106         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
 107         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
 108         * i386-init.h: Regenerated.
 109
 110 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 111
 112         PR gas/20145
 113         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
 114         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
 115         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
 116         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
 117         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
 118         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
 119         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
 120         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
 121         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
 122         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
 123         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
 124         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
 125         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
 126         CpuRegMask for AVX512.
 127         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
 128         and CpuRegMask.
 129         (set_bitfield_from_cpu_flag_init): New function.
 130         (set_bitfield): Remove const on f.  Call
 131         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
 132         * i386-opc.h (CpuRegMMX): New.
 133         (CpuRegXMM): Likewise.
 134         (CpuRegYMM): Likewise.
 135         (CpuRegZMM): Likewise.
 136         (CpuRegMask): Likewise.
 137         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
 138         and cpuregmask.
 139         * i386-init.h: Regenerated.
 140         * i386-tbl.h: Likewise.
 141
 142 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 143
 144         PR gas/20154
 145         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
 146         (opcode_modifiers): Add AMD64 and Intel64.
 147         (main): Properly verify CpuMax.
 148         * i386-opc.h (CpuAMD64): Removed.
 149         (CpuIntel64): Likewise.
 150         (CpuMax): Set to CpuNo64.
 151         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 152         (AMD64): New.
 153         (Intel64): Likewise.
 154         (i386_opcode_modifier): Add amd64 and intel64.
 155         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 156         on call and jmp.
 157         * i386-init.h: Regenerated.
 158         * i386-tbl.h: Likewise.
 159
 160 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 161
 162         PR gas/20154
 163         * i386-gen.c (main): Fail if CpuMax is incorrect.
 164         * i386-opc.h (CpuMax): Set to CpuIntel64.
 165         * i386-tbl.h: Regenerated.
 166
 167 2016-05-27  Nick Clifton  <nickc@redhat.com>
 168
 169         PR target/20150
 170         * msp430-dis.c (msp430dis_read_two_bytes): New function.
 171         (msp430dis_opcode_unsigned): New function.
 172         (msp430dis_opcode_signed): New function.
 173         (msp430_singleoperand): Use the new opcode reading functions.
 174         Only disassenmble bytes if they were successfully read.
 175         (msp430_doubleoperand): Likewise.
 176         (msp430_branchinstr): Likewise.
 177         (msp430x_callx_instr): Likewise.
 178         (print_insn_msp430): Check that it is safe to read bytes before
 179         attempting disassembly.  Use the new opcode reading functions.
 180
 181 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
 182
 183         * ppc-opc.c (CY): New define.  Document it.
 184         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
 185
 186 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 187
 188         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
 189         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
 190         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
 191         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
 192         CPU_ANY_AVX_FLAGS.
 193         * i386-init.h: Regenerated.
 194
 195 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 196
 197         PR gas/20141
 198         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 199         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 200         * i386-init.h: Regenerated.
 201
 202 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 203
 204         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 205         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 206         * i386-init.h: Regenerated.
 207
 208 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 209
 210         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 211         information.
 212         (print_insn_arc): Set insn_type information.
 213         * arc-opc.c (C_CC): Add F_CLASS_COND.
 214         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 215         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 216         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 217         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 218         (brne, brne_s, jeq_s, jne_s): Likewise.
 219
 220 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 221
 222         * arc-tbl.h (neg): New instruction variant.
 223
 224 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 225
 226         * arc-dis.c (find_format, find_format, get_auxreg)
 227         (print_insn_arc): Changed.
 228         * arc-ext.h (INSERT_XOP): Likewise.
 229
 230 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 231
 232         * tic54x-dis.c (sprint_mmr): Adjust.
 233         * tic54x-opc.c: Likewise.
 234
 235 2016-05-19  Alan Modra  <amodra@gmail.com>
 236
 237         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
 238
 239 2016-05-19  Alan Modra  <amodra@gmail.com>
 240
 241         * ppc-opc.c: Formatting.
 242         (NSISIGNOPT): Define.
 243         (powerpc_opcodes <subis>): Use NSISIGNOPT.
 244
 245 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
 246
 247         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
 248         replacing references to `micromips_ase' throughout.
 249         (_print_insn_mips): Don't use file-level microMIPS annotation to
 250         determine the disassembly mode with the symbol table.
 251
 252 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
 253
 254         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
 255
 256 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
 257
 258         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
 259         mips64r6.
 260         * mips-opc.c (D34): New macro.
 261         (mips_builtin_opcodes): Define bposge32c for DSPr3.
 262
 263 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
 264
 265         * i386-dis.c (prefix_table): Add RDPID instruction.
 266         * i386-gen.c (cpu_flag_init): Add RDPID flag.
 267         (cpu_flags): Add RDPID bitfield.
 268         * i386-opc.h (enum): Add RDPID element.
 269         (i386_cpu_flags): Add RDPID field.
 270         * i386-opc.tbl: Add RDPID instruction.
 271         * i386-init.h: Regenerate.
 272         * i386-tbl.h: Regenerate.
 273
 274 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 275
 276         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
 277         branch type of a symbol.
 278         (print_insn): Likewise.
 279
 280 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 281
 282         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
 283         Mainline Security Extensions instructions.
 284         (thumb_opcodes): Add entries for narrow ARMv8-M Security
 285         Extensions instructions.
 286         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
 287         instructions.
 288         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
 289         special registers.
 290
 291 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
 292
 293         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
 294
 295 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
 296
 297         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
 298         (arcExtMap_genOpcode): Likewise.
 299         * arc-opc.c (arg_32bit_rc): Define new variable.
 300         (arg_32bit_u6): Likewise.
 301         (arg_32bit_limm): Likewise.
 302
 303 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 304
 305         * aarch64-gen.c (VERIFIER): Define.
 306         * aarch64-opc.c (VERIFIER): Define.
 307         (verify_ldpsw): Use static linkage.
 308         * aarch64-opc.h (verify_ldpsw): Remove.
 309         * aarch64-tbl.h: Use VERIFIER for verifiers.
 310
 311 2016-04-28  Nick Clifton  <nickc@redhat.com>
 312
 313         PR target/19722
 314         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
 315         * aarch64-opc.c (verify_ldpsw): New function.
 316         * aarch64-opc.h (verify_ldpsw): New prototype.
 317         * aarch64-tbl.h: Add initialiser for verifier field.
 318         (LDPSW): Set verifier to verify_ldpsw.
 319
 320 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
 321
 322         PR binutils/19983
 323         PR binutils/19984
 324         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
 325         smaller than address size.
 326
 327 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 328
 329         * alpha-dis.c: Regenerate.
 330         * crx-dis.c: Likewise.
 331         * disassemble.c: Likewise.
 332         * epiphany-opc.c: Likewise.
 333         * fr30-opc.c: Likewise.
 334         * frv-opc.c: Likewise.
 335         * ip2k-opc.c: Likewise.
 336         * iq2000-opc.c: Likewise.
 337         * lm32-opc.c: Likewise.
 338         * lm32-opinst.c: Likewise.
 339         * m32c-opc.c: Likewise.
 340         * m32r-opc.c: Likewise.
 341         * m32r-opinst.c: Likewise.
 342         * mep-opc.c: Likewise.
 343         * mt-opc.c: Likewise.
 344         * or1k-opc.c: Likewise.
 345         * or1k-opinst.c: Likewise.
 346         * tic80-opc.c: Likewise.
 347         * xc16x-opc.c: Likewise.
 348         * xstormy16-opc.c: Likewise.
 349
 350 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 351
 352         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
 353         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
 354         calcsd, and calcxd instructions.
 355         * arc-opc.c (insert_nps_bitop_size): Delete.
 356         (extract_nps_bitop_size): Delete.
 357         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
 358         (extract_nps_qcmp_m3): Define.
 359         (extract_nps_qcmp_m2): Define.
 360         (extract_nps_qcmp_m1): Define.
 361         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
 362         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
 363         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
 364         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
 365         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
 366         NPS_QCMP_M3.
 367
 368 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 369
 370         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
 371
 372 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 373
 374         * Makefile.in: Regenerated with automake 1.11.6.
 375         * aclocal.m4: Likewise.
 376
 377 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 378
 379         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
 380         instructions.
 381         * arc-opc.c (insert_nps_cmem_uimm16): New function.
 382         (extract_nps_cmem_uimm16): New function.
 383         (arc_operands): Add NPS_XLDST_UIMM16 operand.
 384
 385 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 386
 387         * arc-dis.c (arc_insn_length): New function.
 388         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
 389         (find_format): Change insnLen parameter to unsigned.
 390
 391 2016-04-13  Nick Clifton  <nickc@redhat.com>
 392
 393         PR target/19937
 394         * v850-opc.c (v850_opcodes): Correct masks for long versions of
 395         the LD.B and LD.BU instructions.
 396
 397 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 398
 399         * arc-dis.c (find_format): Check for extension flags.
 400         (print_flags): New function.
 401         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
 402         .extAuxRegister.
 403         * arc-ext.c (arcExtMap_coreRegName): Use
 404         LAST_EXTENSION_CORE_REGISTER.
 405         (arcExtMap_coreReadWrite): Likewise.
 406         (dump_ARC_extmap): Update printing.
 407         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
 408         (arc_aux_regs): Add cpu field.
 409         * arc-regs.h: Add cpu field, lower case name aux registers.
 410
 411 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 412
 413         * arc-tbl.h: Add rtsc, sleep with no arguments.
 414
 415 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 416
 417         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
 418         Initialize.
 419         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
 420         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
 421         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
 422         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
 423         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
 424         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
 425         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
 426         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
 427         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
 428         (arc_opcode arc_opcodes): Null terminate the array.
 429         (arc_num_opcodes): Remove.
 430         * arc-ext.h (INSERT_XOP): Define.
 431         (extInstruction_t): Likewise.
 432         (arcExtMap_instName): Delete.
 433         (arcExtMap_insn): New function.
 434         (arcExtMap_genOpcode): Likewise.
 435         * arc-ext.c (ExtInstruction): Remove.
 436         (create_map): Zero initialize instruction fields.
 437         (arcExtMap_instName): Remove.
 438         (arcExtMap_insn): New function.
 439         (dump_ARC_extmap): More info while debuging.
 440         (arcExtMap_genOpcode): New function.
 441         * arc-dis.c (find_format): New function.
 442         (print_insn_arc): Use find_format.
 443         (arc_get_disassembler): Enable dump_ARC_extmap only when
 444         debugging.
 445
 446 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
 447
 448         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
 449         instruction bits out.
 450
 451 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 452
 453         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
 454         * arc-opc.c (arc_flag_operands): Add new flags.
 455         (arc_flag_classes): Add new classes.
 456
 457 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 458
 459         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
 460
 461 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
 462
 463         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
 464         encode1, rflt, crc16, and crc32 instructions.
 465         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
 466         (arc_flag_classes): Add C_NPS_R.
 467         (insert_nps_bitop_size_2b): New function.
 468         (extract_nps_bitop_size_2b): Likewise.
 469         (insert_nps_bitop_uimm8): Likewise.
 470         (extract_nps_bitop_uimm8): Likewise.
 471         (arc_operands): Add new operand entries.
 472
 473 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
 474
 475         * arc-regs.h: Add a new subclass field.  Add double assist
 476         accumulator register values.
 477         * arc-tbl.h: Use DPA subclass to mark the double assist
 478         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
 479         * arc-opc.c (RSP): Define instead of SP.
 480         (arc_aux_regs): Add the subclass field.
 481
 482 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
 483
 484         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
 485
 486 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
 487
 488         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
 489         NPS_R_SRC1.
 490
 491 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
 492
 493         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
 494         issues.  No functional changes.
 495
 496 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
 497
 498         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
 499         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
 500         (RTT): Remove duplicate.
 501         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
 502         (PCT_CONFIG*): Remove.
 503         (D1L, D1H, D2H, D2L): Define.
 504
 505 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 506
 507         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
 508
 509 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 510
 511         * arc-tbl.h (invld07): Remove.
 512         * arc-ext-tbl.h: New file.
 513         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
 514         * arc-opc.c (arc_opcodes): Add ext-tbl include.
 515
 516 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
 517
 518         Fix -Wstack-usage warnings.
 519         * aarch64-dis.c (print_operands): Substitute size.
 520         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
 521
 522 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 523
 524         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
 525         to get a proper diagnostic when an invalid ASR register is used.
 526
 527 2016-03-22  Nick Clifton  <nickc@redhat.com>
 528
 529         * configure: Regenerate.
 530
 531 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 532
 533         * arc-nps400-tbl.h: New file.
 534         * arc-opc.c: Add top level comment.
 535         (insert_nps_3bit_dst): New function.
 536         (extract_nps_3bit_dst): New function.
 537         (insert_nps_3bit_src2): New function.
 538         (extract_nps_3bit_src2): New function.
 539         (insert_nps_bitop_size): New function.
 540         (extract_nps_bitop_size): New function.
 541         (arc_flag_operands): Add nps400 entries.
 542         (arc_flag_classes): Add nps400 entries.
 543         (arc_operands): Add nps400 entries.
 544         (arc_opcodes): Add nps400 include.
 545
 546 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 547
 548         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
 549         the new class enum values.
 550
 551 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 552
 553         * arc-dis.c (print_insn_arc): Handle nps400.
 554
 555 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 556
 557         * arc-opc.c (BASE): Delete.
 558
 559 2016-03-18  Nick Clifton  <nickc@redhat.com>
 560
 561         PR target/19721
 562         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
 563         of MOV insn that aliases an ORR insn.
 564
 565 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
 566
 567         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
 568
 569 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 570
 571         * mcore-opc.h: Add const qualifiers.
 572         * microblaze-opc.h (struct op_code_struct): Likewise.
 573         * sh-opc.h: Likewise.
 574         * tic4x-dis.c (tic4x_print_indirect): Likewise.
 575         (tic4x_print_op): Likewise.
 576
 577 2016-03-02  Alan Modra  <amodra@gmail.com>
 578
 579         * or1k-desc.h: Regenerate.
 580         * fr30-ibld.c: Regenerate.
 581         * rl78-decode.c: Regenerate.
 582
 583 2016-03-01  Nick Clifton  <nickc@redhat.com>
 584
 585         PR target/19747
 586         * rl78-dis.c (print_insn_rl78_common): Fix typo.
 587
 588 2016-02-24  Renlin Li  <renlin.li@arm.com>
 589
 590         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
 591         (print_insn_coprocessor): Support fp16 instructions.
 592
 593 2016-02-24  Renlin Li  <renlin.li@arm.com>
 594
 595         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
 596         vminnm, vrint(mpna).
 597
 598 2016-02-24  Renlin Li  <renlin.li@arm.com>
 599
 600         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
 601         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
 602
 603 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
 604
 605         * i386-dis.c (print_insn): Parenthesize expression to prevent
 606         truncated addresses.
 607         (OP_J): Likewise.
 608
 609 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
 610             Janek van Oirschot  <jvanoirs@synopsys.com>
 611
 612         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
 613         variable.
 614
 615 2016-02-04  Nick Clifton  <nickc@redhat.com>
 616
 617         PR target/19561
 618         * msp430-dis.c (print_insn_msp430): Add a special case for
 619         decoding an RRC instruction with the ZC bit set in the extension
 620         word.
 621
 622 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 623
 624         * cgen-ibld.in (insert_normal): Rework calculation of shift.
 625         * epiphany-ibld.c: Regenerate.
 626         * fr30-ibld.c: Regenerate.
 627         * frv-ibld.c: Regenerate.
 628         * ip2k-ibld.c: Regenerate.
 629         * iq2000-ibld.c: Regenerate.
 630         * lm32-ibld.c: Regenerate.
 631         * m32c-ibld.c: Regenerate.
 632         * m32r-ibld.c: Regenerate.
 633         * mep-ibld.c: Regenerate.
 634         * mt-ibld.c: Regenerate.
 635         * or1k-ibld.c: Regenerate.
 636         * xc16x-ibld.c: Regenerate.
 637         * xstormy16-ibld.c: Regenerate.
 638
 639 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 640
 641         * epiphany-dis.c: Regenerated from latest cpu files.
 642
 643 2016-02-01  Michael McConville  <mmcco@mykolab.com>
 644
 645         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
 646         test bit.
 647
 648 2016-01-25  Renlin Li  <renlin.li@arm.com>
 649
 650         * arm-dis.c (mapping_symbol_for_insn): New function.
 651         (find_ifthen_state): Call mapping_symbol_for_insn().
 652
 653 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
 654
 655         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
 656         of MSR UAO immediate operand.
 657
 658 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
 659
 660         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
 661         instruction support.
 662
 663 2016-01-17  Alan Modra  <amodra@gmail.com>
 664
 665         * configure: Regenerate.
 666
 667 2016-01-14  Nick Clifton  <nickc@redhat.com>
 668
 669         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
 670         instructions that can support stack pointer operations.
 671         * rl78-decode.c: Regenerate.
 672         * rl78-dis.c: Fix display of stack pointer in MOVW based
 673         instructions.
 674
 675 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
 676
 677         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
 678         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
 679         erxtatus_el1 and erxaddr_el1.
 680
 681 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
 682
 683         * arm-dis.c (arm_opcodes): Add "esb".
 684         (thumb_opcodes): Likewise.
 685
 686 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
 687
 688         * ppc-opc.c <xscmpnedp>: Delete.
 689         <xvcmpnedp>: Likewise.
 690         <xvcmpnedp.>: Likewise.
 691         <xvcmpnesp>: Likewise.
 692         <xvcmpnesp.>: Likewise.
 693
 694 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
 695
 696         PR gas/13050
 697         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
 698         addition to ISA_A.
 699
 700 2016-01-01  Alan Modra  <amodra@gmail.com>
 701
 702         Update year range in copyright notice of all files.
 703
 704 For older changes see ChangeLog-2015
 705 \f
 706 Copyright (C) 2016 Free Software Foundation, Inc.
 707
 708 Copying and distribution of this file, with or without modification,
 709 are permitted in any medium without royalty provided the copyright
 710 notice and this notice are preserved.
 711
 712 Local Variables:
 713 mode: change-log
 714 left-margin: 8
 715 fill-column: 74
 716 version-control: never
 717 End: