opcodes/ChangeLog

   1 2021-09-27  Nick Alcock  <nick.alcock@oracle.com>
   2
   3         * configure: Regenerate.
   4
   5 2021-09-25  Peter Bergner  <bergner@linux.ibm.com>
   6
   7         * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
   8         on POWER5 and later.
   9
  10 2021-09-20  Andrew Burgess  <andrew.burgess@embecosm.com>
  11
  12         * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
  13         before an unknown instruction, '%d' is replaced with the
  14         instruction length.
  15
  16 2021-09-02  Nick Clifton  <nickc@redhat.com>
  17
  18         PR 28292
  19         * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
  20         of BFD_RELOC_16.
  21
  22 2021-08-17  Shahab Vahedi <shahab@synopsys.com>
  23
  24         * arc-regs.h (DEF): Fix the register numbers.
  25
  26 2021-08-10  Nick Clifton  <nickc@redhat.com>
  27
  28         * po/sr.po: Updated Serbian translation.
  29
  30 2021-07-26  Chenghua Xu  <xuchenghua@loongson.cn>
  31
  32         * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
  33
  34 2021-06-07  Andreas Krebbel  <krebbel@linux.ibm.com>
  35
  36         * s390-opc.txt: Add qpaci.
  37
  38 2021-07-03  Nick Clifton  <nickc@redhat.com>
  39
  40         * configure: Regenerate.
  41         * po/opcodes.pot: Regenerate.
  42
  43 2021-07-03  Nick Clifton  <nickc@redhat.com>
  44
  45         * 2.37 release branch created.
  46
  47 2021-07-02  Alan Modra  <amodra@gmail.com>
  48
  49         * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
  50         (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
  51         (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
  52         (nds32_opcodes, nds32_operand_fields, nds32_keywords),
  53         (nds32_keyword_gpr): Move declarations to..
  54         * nds32-asm.h: ..here, constifying to match definitions.
  55
  56 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  57
  58         * Makefile.am (GUILE): New variable.
  59         (CGEN): Use $(GUILE).
  60         * Makefile.in: Regenerate.
  61
  62 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  63
  64         * mep-asm.c (macros): Mark static & const.
  65         (lookup_macro): Change return & m to const.
  66         (expand_macro): Change mac to const.
  67         (expand_string): Change pmacro to const.
  68
  69 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  70
  71         * nds32-asm.c (operand_fields): Rename to ...
  72         (nds32_operand_fields): ... this.
  73         (keyword_gpr): Rename to ...
  74         (nds32_keyword_gpr): ... this.
  75         (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
  76         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
  77         keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
  78         keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
  79         keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
  80         Mark static.
  81         (keywords): Rename to ...
  82         (nds32_keywords): ... this.
  83         * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
  84         keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
  85
  86 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  87
  88         * z80-dis.c (opc_ed): Make const.
  89         (pref_ed): Make p const.
  90
  91 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  92
  93         * microblaze-dis.c (get_field_special): Make op const.
  94         (read_insn_microblaze): Make opr & op const.  Rename opcodes to
  95         microblaze_opcodes.
  96         (print_insn_microblaze): Make op & pop const.
  97         (get_insn_microblaze): Make op const.  Rename opcodes to
  98         microblaze_opcodes.
  99         (microblaze_get_target_address): Likewise.
 100         * microblaze-opc.h (struct op_code_struct): Make const.
 101         Rename opcodes to microblaze_opcodes.
 102
 103 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 104
 105         * aarch64-gen.c (aarch64_opcode_table): Add const.
 106         * aarch64-tbl.h (aarch64_opcode_table): Likewise.
 107
 108 2021-06-22  Andrew Burgess  <andrew.burgess@embecosm.com>
 109
 110         * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
 111         available.
 112
 113 2021-06-22  Alan Modra  <amodra@gmail.com>
 114
 115         * pj-dis.c (print_insn_pj): Don't print trailing tab.  Do
 116         print separator for pcrel insns.
 117
 118 2021-06-19  Alan Modra  <amodra@gmail.com>
 119
 120         * vax-dis.c (print_insn_vax): Avoid pointer overflow.
 121
 122 2021-06-19  Alan Modra  <amodra@gmail.com>
 123
 124         * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
 125         entire buffer.
 126
 127 2021-06-17  Alan Modra  <amodra@gmail.com>
 128
 129         * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
 130         in table.
 131
 132 2021-06-03  Alan Modra  <amodra@gmail.com>
 133
 134         PR 1202
 135         * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
 136         Use unsigned int for inst.
 137
 138 2021-06-02  Shahab Vahedi  <shahab@synopsys.com>
 139
 140         * arc-dis.c (arc_option_arg_t): New enumeration.
 141         (arc_options): New variable.
 142         (disassembler_options_arc): New function.
 143         (print_arc_disassembler_options): Reimplement in terms of
 144         "disassembler_options_arc".
 145
 146 2021-05-29  Alan Modra  <amodra@gmail.com>
 147
 148         * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
 149         Don't special case PPC_OPCODE_RAW.
 150         (lookup_prefix): Likewise.
 151         (lookup_vle, lookup_spe2): Similarly.  Add dialect parameter and..
 152         (print_insn_powerpc): ..update caller.
 153         * ppc-opc.c (EXT): Define.
 154         (powerpc_opcodes): Mark extended mnemonics with EXT.
 155         (prefix_opcodes, vle_opcodes): Likewise.
 156         (XISEL, XISEL_MASK): Add cr field and simplify.
 157         (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
 158         all isel variants to where the base mnemonic belongs.  Sort dstt,
 159         dststt and dssall.
 160
 161 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 162
 163         * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
 164         COP3 opcode instructions.
 165
 166 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 167
 168         * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
 169         "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
 170         "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
 171         "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
 172         "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
 173         "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
 174         "cop2", and "cop3" entries.
 175
 176 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 177
 178         * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
 179         entries and associated comments.
 180
 181 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 182
 183         * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
 184         of "c0".
 185
 186 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 187
 188         * mips-dis.c (mips_cp1_names_mips): New variable.
 189         (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
 190         for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
 191         "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
 192         "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
 193         "r12000", "r14000", "r16000", "mips5", "loongson2e", and
 194         "loongson2f".
 195
 196 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 197
 198         * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
 199         handling code over to...
 200         <OP_REG_CONTROL>: ... this new case.
 201         * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
 202         (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
 203         "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
 204         replacing the `G' operand code with `g'.  Update "cftc1" and
 205         "cftc2" entries replacing the `E' operand code with `y'.
 206         * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
 207         (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
 208         entries replacing the `G' operand code with `g'.
 209
 210 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 211
 212         * mips-dis.c (mips_cp0_names_r3900): New variable.
 213         (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
 214         for "r3900".
 215
 216 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 217
 218         * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
 219         and "mtthc2" to using the `G' rather than `g' operand code for
 220         the coprocessor control register referred.
 221
 222 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 223
 224         * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
 225         entries with each other.
 226
 227 2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
 228
 229         * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
 230
 231 2021-05-25  Alan Modra  <amodra@gmail.com>
 232
 233         * cris-desc.c: Regenerate.
 234         * cris-desc.h: Regenerate.
 235         * cris-opc.h: Regenerate.
 236         * po/POTFILES.in: Regenerate.
 237
 238 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
 239
 240         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
 241         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
 242         (CGEN_CPUS): Add cris.
 243         (CRIS_DEPS): Define.
 244         (stamp-cris): New rule.
 245         * cgen.sh: Handle desc action.
 246         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
 247         * Makefile.in, configure: Regenerate.
 248
 249 2021-05-18  Job Noorman  <mtvec@pm.me>
 250
 251         PR 27814
 252         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
 253         the elf objects.
 254
 255 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
 256
 257         * arm-dis.c (mve_opcodes): Fix disassembly of
 258         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
 259         (is_mve_encoding_conflict): MVE vector loads should not match
 260         when P = W = 0.
 261         (is_mve_unpredictable): It's not unpredictable to use the same
 262         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
 263
 264 2021-05-11  Nick Clifton  <nickc@redhat.com>
 265
 266         PR 27840
 267         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
 268         the end of the code buffer.
 269
 270 2021-05-06  Stafford Horne  <shorne@gmail.com>
 271
 272         PR 21464
 273         * or1k-asm.c: Regenerate.
 274
 275 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
 276
 277         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
 278         info->insn_info_valid.
 279
 280 2021-04-26  Jan Beulich  <jbeulich@suse.com>
 281
 282         * i386-opc.tbl (lea): Add Optimize.
 283         * opcodes/i386-tbl.h: Re-generate.
 284
 285 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 286
 287         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
 288         of l32r fetch and display referenced literal value.
 289
 290 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 291
 292         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
 293         to 4 for literal disassembly.
 294
 295 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 296
 297         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
 298         for TLBI instruction.
 299
 300 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 301
 302         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
 303         DC instruction.
 304
 305 2021-04-19  Jan Beulich  <jbeulich@suse.com>
 306
 307         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
 308         "qualifier".
 309         (convert_mov_to_movewide): Add initializer for "value".
 310
 311 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 312
 313         * aarch64-opc.c: Add RME system registers.
 314
 315 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
 316
 317         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
 318         "addi d,CV,z" to "c.mv d,CV".
 319
 320 2021-04-12  Alan Modra  <amodra@gmail.com>
 321
 322         * configure.ac (--enable-checking): Add support.
 323         * config.in: Regenerate.
 324         * configure: Regenerate.
 325
 326 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
 327
 328         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
 329         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 330
 331 2021-04-09  Alan Modra  <amodra@gmail.com>
 332
 333         * ppc-dis.c (struct dis_private): Add "special".
 334         (POWERPC_DIALECT): Delete.  Replace uses with..
 335         (private_data): ..this.  New inline function.
 336         (disassemble_init_powerpc): Init "special" names.
 337         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 338         field of prefix instructions.
 339         (bsearch_reloc, print_got_plt): New functions.
 340         (print_insn_powerpc): For pcrel instructions, print target address
 341         and symbol if known, and decode plt and got loads too.
 342
 343 2021-04-08  Alan Modra  <amodra@gmail.com>
 344
 345         PR 27684
 346         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 347
 348 2021-04-08  Alan Modra  <amodra@gmail.com>
 349
 350         PR 27676
 351         * ppc-opc.c (DCBT_EO): Move earlier.
 352         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 353         (powerpc_operands): Add THCT and THDS entries.
 354         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 355
 356 2021-04-06  Alan Modra  <amodra@gmail.com>
 357
 358         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 359         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 360         symbol_at_address_func.
 361
 362 2021-04-05  Alan Modra  <amodra@gmail.com>
 363
 364         * configure.ac: Don't check for limits.h, string.h, strings.h or
 365         stdlib.h.
 366         (AC_ISC_POSIX): Don't invoke.
 367         * sysdep.h: Include stdlib.h and string.h unconditionally.
 368         * i386-opc.h: Include limits.h unconditionally.
 369         * wasm32-dis.c: Likewise.
 370         * cgen-opc.c: Don't include alloca-conf.h.
 371         * config.in: Regenerate.
 372         * configure: Regenerate.
 373
 374 2021-04-01  Martin Liska  <mliska@suse.cz>
 375
 376         * arm-dis.c (strneq): Remove strneq and use startswith.
 377         * cr16-dis.c (print_insn_cr16): Likewise.
 378         * score-dis.c (streq): Likewise.
 379         (strneq): Likewise.
 380         * score7-dis.c (strneq): Likewise.
 381
 382 2021-04-01  Alan Modra  <amodra@gmail.com>
 383
 384         PR 27675
 385         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 386
 387 2021-03-31  Alan Modra  <amodra@gmail.com>
 388
 389         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 390         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 391         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 392         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 393         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 394         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 395         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 396         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 397         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 398         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 399         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 400         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 401         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 402         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 403         and TRUE with true throughout.
 404
 405 2021-03-31  Alan Modra  <amodra@gmail.com>
 406
 407         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 408         * aarch64-dis.h: Likewise.
 409         * aarch64-opc.c: Likewise.
 410         * avr-dis.c: Likewise.
 411         * csky-dis.c: Likewise.
 412         * nds32-asm.c: Likewise.
 413         * nds32-dis.c: Likewise.
 414         * nfp-dis.c: Likewise.
 415         * riscv-dis.c: Likewise.
 416         * s12z-dis.c: Likewise.
 417         * wasm32-dis.c: Likewise.
 418
 419 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 420
 421         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 422         (i386_seg_prefixes): New.
 423         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 424         (i386_seg_prefixes): Declare.
 425
 426 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 427
 428         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 429
 430 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 431
 432         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 433         * i386-reg.tbl (st): Move down.
 434         (st(0)): Delete. Extend comment.
 435         * i386-tbl.h: Re-generate.
 436
 437 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 438
 439         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 440         (cmpsd): Move next to cmps.
 441         (movsd): Move next to movs.
 442         (cmpxchg16b): Move to separate section.
 443         (fisttp, fisttpll): Likewise.
 444         (monitor, mwait): Likewise.
 445         * i386-tbl.h: Re-generate.
 446
 447 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 448
 449         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 450         (vpsadbw): Add C.
 451         * i386-tbl.h: Re-generate.
 452
 453 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 454
 455         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 456         pclmul, gfni): New templates. Use them wherever possible. Move
 457         SSE4.1 pextrw into respective section.
 458         * i386-tbl.h: Re-generate.
 459
 460 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 461
 462         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 463         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 464         "length".
 465         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 466         Convert all of their uses to representation in opcode.
 467
 468 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 469
 470         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 471         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 472         value of None. Shrink operands to 3 bits.
 473
 474 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 475
 476         * i386-gen.c (process_i386_opcode_modifier): New parameter
 477         "space".
 478         (output_i386_opcode): New local variable "space". Adjust
 479         process_i386_opcode_modifier() invocation.
 480         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 481         invocation.
 482         * i386-tbl.h: Re-generate.
 483
 484 2021-03-29  Alan Modra  <amodra@gmail.com>
 485
 486         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 487         (fp_qualifier_p, get_data_pattern): Likewise.
 488         (aarch64_get_operand_modifier_from_value): Likewise.
 489         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 490         (operand_variant_qualifier_p): Likewise.
 491         (qualifier_value_in_range_constraint_p): Likewise.
 492         (aarch64_get_qualifier_esize): Likewise.
 493         (aarch64_get_qualifier_nelem): Likewise.
 494         (aarch64_get_qualifier_standard_value): Likewise.
 495         (get_lower_bound, get_upper_bound): Likewise.
 496         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 497         (aarch64_print_operand): Likewise.
 498         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 499         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 500         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 501         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 502         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 503         (print_insn_tic6x): Likewise.
 504
 505 2021-03-29  Alan Modra  <amodra@gmail.com>
 506
 507         * arc-dis.c (extract_operand_value): Correct NULL cast.
 508         * frv-opc.h: Regenerate.
 509
 510 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 511
 512         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 513         MMX form.
 514         * i386-tbl.h: Re-generate.
 515
 516 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 517
 518         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 519         immediate in br.n instruction.
 520
 521 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 522
 523         * i386-dis.c (XMGatherD, VexGatherD): New.
 524         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 525         (print_insn): Check masking for S/G insns.
 526         (OP_E_memory): New local variable check_gather. Extend mandatory
 527         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 528         Extend check for disallowed 16-bit addressing.
 529         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 530         if()s to switch(). Check register conflicts for (VEX-encoded)
 531         gathers. Drop no longer reachable cases.
 532         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 533         vgatherdp*.
 534
 535 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 536
 537         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 538         zeroing-masking without masking.
 539
 540 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 541
 542         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 543         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 544         single-operand forms as deprecated.
 545         * i386-tbl.h: Re-generate.
 546
 547 2021-03-25  Alan Modra  <amodra@gmail.com>
 548
 549         PR 27647
 550         * ppc-opc.c (XLOCB_MASK): Delete.
 551         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 552         XLBH_MASK.
 553         (powerpc_opcodes): Accept a BH field on all extended forms of
 554         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 555
 556 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 557
 558         * i386-gen.c (output_i386_opcode): Drop processing of
 559         opcode_length. Calculate length from base_opcode. Adjust prefix
 560         encoding determination.
 561         (process_i386_opcodes): Drop output of fake opcode_length.
 562         * i386-opc.h (struct insn_template): Drop opcode_length field.
 563         * i386-opc.tbl: Drop opcode length field from all templates.
 564         * i386-tbl.h: Re-generate.
 565
 566 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 567
 568         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 569         parameter "prefix". Drop local variable "regular_encoding".
 570         Record prefix setting / check for consistency.
 571         (output_i386_opcode): Parse opcode_length and base_opcode
 572         earlier. Derive prefix encoding. Drop no longer applicable
 573         consistency checking. Adjust process_i386_opcode_modifier()
 574         invocation.
 575         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 576         invocation.
 577         * i386-tbl.h: Re-generate.
 578
 579 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 580
 581         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 582         check.
 583         * i386-opc.h (Prefix_*): Move #define-s.
 584         * i386-opc.tbl: Move pseudo prefix enumerator values to
 585         extension opcode field. Introduce pseudopfx template.
 586         * i386-tbl.h: Re-generate.
 587
 588 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 589
 590         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 591         comment.
 592         * i386-tbl.h: Re-generate.
 593
 594 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 595
 596         * i386-opc.h (struct insn_template): Move cpu_flags field past
 597         opcode_modifier one.
 598         * i386-tbl.h: Re-generate.
 599
 600 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 601
 602         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 603         * i386-opc.h (OpcodeSpace): New enumerator.
 604         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 605         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 606         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 607         (struct i386_opcode_modifier): New field opcodespace. Shrink
 608         opcodeprefix field.
 609         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 610         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 611         OpcodePrefix uses.
 612         * i386-tbl.h: Re-generate.
 613
 614 2021-03-22  Martin Liska  <mliska@suse.cz>
 615
 616         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 617         * arc-dis.c (parse_option): Likewise.
 618         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 619         * cris-dis.c (print_with_operands): Likewise.
 620         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 621         * i386-dis.c (print_insn): Likewise.
 622         * ia64-gen.c (fetch_insn_class): Likewise.
 623         (parse_resource_users): Likewise.
 624         (in_iclass): Likewise.
 625         (lookup_specifier): Likewise.
 626         (insert_opcode_dependencies): Likewise.
 627         * mips-dis.c (parse_mips_ase_option): Likewise.
 628         (parse_mips_dis_option): Likewise.
 629         * s390-dis.c (disassemble_init_s390): Likewise.
 630         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 631
 632 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 633
 634         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 635
 636 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 637
 638         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 639         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 640
 641 2021-03-12  Alan Modra  <amodra@gmail.com>
 642
 643         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 644
 645 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 646
 647         * i386-dis.c (OP_XMM): Re-order checks.
 648
 649 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 650
 651         * i386-dis.c (putop): Drop need_vex check when also checking
 652         vex.evex.
 653         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 654         checking vex.b.
 655
 656 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 657
 658         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 659         checks. Move case label past broadcast check.
 660
 661 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 662
 663         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 664         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 665         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 666         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 667         EVEX_W_0F38C7_M_0_L_2): Delete.
 668         (REG_EVEX_0F38C7_M_0_L_2): New.
 669         (intel_operand_size): Handle VEX and EVEX the same for
 670         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 671         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 672         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 673         vex_vsib_q_w_d_mode uses.
 674         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 675         0F38A1, and 0F38A3 entries.
 676         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 677         entry.
 678         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 679         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 680         0F38A3 entries.
 681
 682 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 683
 684         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 685         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 686         MOD_VEX_0FXOP_09_12): Rename to ...
 687         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 688         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 689         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 690         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 691         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 692         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 693         (reg_table): Adjust comments.
 694         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 695         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 696         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 697         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 698         (vex_len_table): Adjust opcode 0A_12 entry.
 699         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 700         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 701         (rm_table): Move hreset entry.
 702
 703 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 704
 705         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 706         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 707         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 708         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 709         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 710         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 711         (get_valid_dis386): Also handle 512-bit vector length when
 712         vectoring into vex_len_table[].
 713         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 714         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 715         entries.
 716         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 717         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 718         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 719         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 720         entries.
 721
 722 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 723
 724         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 725         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 726         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 727         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 728         entries.
 729         * i386-dis-evex-len.h (evex_len_table): Likewise.
 730         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 731
 732 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 733
 734         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 735         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 736         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 737         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 738         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 739         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 740         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 741         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 742         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 743         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 744         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 745         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 746         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 747         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 748         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 749         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 750         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 751         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 752         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 753         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 754         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 755         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 756         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 757         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 758         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 759         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 760         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 761         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 762         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 763         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 764         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 765         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 766         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 767         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 768         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 769         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 770         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 771         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 772         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 773         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 774         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 775         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 776         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 777         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 778         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 779         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 780         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 781         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 782         EVEX_W_0F3A43_L_n): New.
 783         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 784         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 785         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 786         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 787         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 788         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 789         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 790         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 791         0F385B, 0F38C6, and 0F38C7 entries.
 792         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 793         0F38C6 and 0F38C7.
 794         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 795         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 796         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 797         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 798
 799 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 800
 801         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 802         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 803         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 804         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 805         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 806         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 807         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 808         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 809         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 810         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 811         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 812         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 813         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 814         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 815         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 816         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 817         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 818         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 819         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 820         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 821         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 822         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 823         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 824         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 825         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 826         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 827         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 828         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 829         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 830         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 831         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 832         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 833         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 834         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 835         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 836         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 837         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 838         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 839         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 840         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 841         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 842         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 843         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 844         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 845         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 846         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 847         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 848         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 849         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 850         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 851         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 852         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 853         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 854         VEX_W_0F99_P_2_LEN_0): Delete.
 855         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 856         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 857         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 858         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 859         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 860         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 861         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 862         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 863         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 864         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 865         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 866         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 867         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 868         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 869         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 870         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 871         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 872         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 873         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 874         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 875         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 876         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 877         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 878         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 879         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 880         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 881         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 882         (prefix_table): No longer link to vex_len_table[] for opcodes
 883         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 884         0F92, 0F93, 0F98, and 0F99.
 885         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 886         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 887         0F98, and 0F99.
 888         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 889         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 890         0F98, and 0F99.
 891         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 892         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 893         0F98, and 0F99.
 894         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 895         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 896         0F98, and 0F99.
 897
 898 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 899
 900         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 901         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 902         REG_VEX_0F73_M_0 respectively.
 903         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 904         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 905         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 906         MOD_VEX_0F73_REG_7): Delete.
 907         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 908         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 909         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 910         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 911         PREFIX_VEX_0F3AF0_L_0 respectively.
 912         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 913         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 914         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 915         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 916         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 917         VEX_LEN_0F38F7): New.
 918         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 919         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 920         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 921         0F38F3.
 922         (prefix_table): No longer link to vex_len_table[] for opcodes
 923         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 924         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 925         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 926         0F38F6, 0F38F7, and 0F3AF0.
 927         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 928         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 929         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 930         0F73.
 931
 932 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 933
 934         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 935         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 936         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 937         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 938         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 939         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 940         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 941         73.
 942         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 943         0F72, and 0F73.
 944         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 945         0F73.
 946
 947 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 948
 949         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 950         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 951         (reg_table): Don't link to mod_table[] where not needed. Add
 952         PREFIX_IGNORED to nop entries.
 953         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 954         (mod_table): Add nop entries next to prefetch ones. Drop
 955         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 956         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 957         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 958         PREFIX_OPCODE from endbr* entries.
 959         (get_valid_dis386): Also consider entry's name when zapping
 960         vindex.
 961         (print_insn): Handle PREFIX_IGNORED.
 962
 963 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 964
 965         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 966         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 967         element.
 968         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 969         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 970         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 971         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 972         (struct i386_opcode_modifier): Delete notrackprefixok,
 973         islockable, hleprefixok, and repprefixok fields. Add prefixok
 974         field.
 975         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 976         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 977         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 978         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 979         Replace HLEPrefixOk.
 980         * opcodes/i386-tbl.h: Re-generate.
 981
 982 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 983
 984         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 985         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 986         64-bit form.
 987         * opcodes/i386-tbl.h: Re-generate.
 988
 989 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 990
 991         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 992         for {} instead of {0}. Don't look for '0'.
 993         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 994         size specifiers.
 995
 996 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 997
 998         PR 27158
 999         * riscv-dis.c (print_insn_args): Updated encoding macros.
1000         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
1001         (match_c_addi16sp): Updated encoding macros.
1002         (match_c_lui): Likewise.
1003         (match_c_lui_with_hint): Likewise.
1004         (match_c_addi4spn): Likewise.
1005         (match_c_slli): Likewise.
1006         (match_slli_as_c_slli): Likewise.
1007         (match_c_slli64): Likewise.
1008         (match_srxi_as_c_srxi): Likewise.
1009         (riscv_insn_types): Added .insn css/cl/cs.
1010
1011 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
1012
1013         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1014         (default_priv_spec): Updated type to riscv_spec_class.
1015         (parse_riscv_dis_option): Updated.
1016         * riscv-opc.c: Moved stuff and make the file tidy.
1017
1018 2021-02-17  Alan Modra  <amodra@gmail.com>
1019
1020         * wasm32-dis.c: Include limits.h.
1021         (CHAR_BIT): Provide backup define.
1022         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1023         Correct signed overflow checking.
1024
1025 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1026
1027         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1028         * i386-tbl.h: Re-generate.
1029
1030 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1031
1032         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1033         Oword.
1034         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1035
1036 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
1037
1038         * s390-mkopc.c (main): Accept arch14 as cpu string.
1039         * s390-opc.txt: Add new arch14 instructions.
1040
1041 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
1042
1043         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1044         favour of LIBINTL.
1045         * configure: Regenerated.
1046
1047 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
1048
1049         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1050         * tic54x-opc.c (regs): Rename to ...
1051         (tic54x_regs): ... this.
1052         (mmregs): Rename to ...
1053         (tic54x_mmregs): ... this.
1054         (condition_codes): Rename to ...
1055         (tic54x_condition_codes): ... this.
1056         (cc2_codes): Rename to ...
1057         (tic54x_cc2_codes): ... this.
1058         (cc3_codes): Rename to ...
1059         (tic54x_cc3_codes): ... this.
1060         (status_bits): Rename to ...
1061         (tic54x_status_bits): ... this.
1062         (misc_symbols): Rename to ...
1063         (tic54x_misc_symbols): ... this.
1064
1065 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
1066
1067         * riscv-opc.c (MASK_RVB_IMM): Removed.
1068         (riscv_opcodes): Removed zb* instructions.
1069         (riscv_ext_version_table): Removed versions for zb*.
1070
1071 2021-01-26  Alan Modra  <amodra@gmail.com>
1072
1073         * i386-gen.c (parse_template): Ensure entire template_instance
1074         is initialised.
1075
1076 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1077
1078         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1079         (riscv_fpr_names_abi): Likewise.
1080         (riscv_opcodes): Likewise.
1081         (riscv_insn_types): Likewise.
1082
1083 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1084
1085         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1086
1087 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1088
1089         * riscv-dis.c: Comments tidy and improvement.
1090         * riscv-opc.c: Likewise.
1091
1092 2021-01-13  Alan Modra  <amodra@gmail.com>
1093
1094         * Makefile.in: Regenerate.
1095
1096 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
1097
1098         PR binutils/26792
1099         * configure.ac: Use GNU_MAKE_JOBSERVER.
1100         * aclocal.m4: Regenerated.
1101         * configure: Likewise.
1102
1103 2021-01-12  Nick Clifton  <nickc@redhat.com>
1104
1105         * po/sr.po: Updated Serbian translation.
1106
1107 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
1108
1109         PR ld/27173
1110         * configure: Regenerated.
1111
1112 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1113
1114         * aarch64-asm-2.c: Regenerate.
1115         * aarch64-dis-2.c: Likewise.
1116         * aarch64-opc-2.c: Likewise.
1117         * aarch64-opc.c (aarch64_print_operand):
1118         Delete handling of AARCH64_OPND_CSRE_CSR.
1119         * aarch64-tbl.h (aarch64_feature_csre): Delete.
1120         (CSRE): Likewise.
1121         (_CSRE_INSN): Likewise.
1122         (aarch64_opcode_table): Delete csr.
1123
1124 2021-01-11  Nick Clifton  <nickc@redhat.com>
1125
1126         * po/de.po: Updated German translation.
1127         * po/fr.po: Updated French translation.
1128         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1129         * po/sv.po: Updated Swedish translation.
1130         * po/uk.po: Updated Ukranian translation.
1131
1132 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
1133
1134         * configure: Regenerated.
1135
1136 2021-01-09  Nick Clifton  <nickc@redhat.com>
1137
1138         * configure: Regenerate.
1139         * po/opcodes.pot: Regenerate.
1140
1141 2021-01-09  Nick Clifton  <nickc@redhat.com>
1142
1143         * 2.36 release branch crated.
1144
1145 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
1146
1147         * ppc-opc.c (insert_dw, (extract_dw): New functions.
1148         (DW, (XRC_MASK): Define.
1149         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1150
1151 2021-01-09  Alan Modra  <amodra@gmail.com>
1152
1153         * configure: Regenerate.
1154
1155 2021-01-08  Nick Clifton  <nickc@redhat.com>
1156
1157         * po/sv.po: Updated Swedish translation.
1158
1159 2021-01-08  Nick Clifton  <nickc@redhat.com>
1160
1161         PR 27129
1162         * aarch64-dis.c (determine_disassembling_preference): Move call to
1163         aarch64_match_operands_constraint outside of the assertion.
1164         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1165         Replace with a return of FALSE.
1166
1167         PR 27139
1168         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1169         core system register.
1170
1171 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
1172
1173         * configure: Regenerate.
1174
1175 2021-01-07  Nick Clifton  <nickc@redhat.com>
1176
1177         * po/fr.po: Updated French translation.
1178
1179 2021-01-07  Fredrik Noring  <noring@nocrew.org>
1180
1181         * m68k-opc.c (chkl): Change minimum architecture requirement to
1182         m68020.
1183
1184 2021-01-07  Philipp Tomsich  <prt@gnu.org>
1185
1186         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1187
1188 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
1189             Jim Wilson  <jimw@sifive.com>
1190             Andrew Waterman  <andrew@sifive.com>
1191             Maxim Blinov  <maxim.blinov@embecosm.com>
1192             Kito Cheng  <kito.cheng@sifive.com>
1193             Nelson Chu  <nelson.chu@sifive.com>
1194
1195         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1196         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1197
1198 2021-01-01  Alan Modra  <amodra@gmail.com>
1199
1200         Update year range in copyright notice of all files.
1201
1202 For older changes see ChangeLog-2020
1203 \f
1204 Copyright (C) 2021 Free Software Foundation, Inc.
1205
1206 Copying and distribution of this file, with or without modification,
1207 are permitted in any medium without royalty provided the copyright
1208 notice and this notice are preserved.
1209
1210 Local Variables:
1211 mode: change-log
1212 left-margin: 8
1213 fill-column: 74
1214 version-control: never
1215 End: