opcodes/ChangeLog

   1 2014-11-03  Nick Clifton  <nickc@redhat.com>
   2
   3         * po/fi.po: Updated Finnish translation.
   4
   5 2014-10-31  Andrew Pinski  <apinski@cavium.com>
   6             Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>
   7
   8         * mips-dis.c (mips_arch_choices): Add octeon3.
   9         * mips-opc.c (IOCT): Include INSN_OCTEON3.
  10         (IOCT2): Likewise.
  11         (IOCT3): New define.
  12         (IVIRT): New define.
  13         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
  14         tlbinv, tlbinvf, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp, tlti
  15         IVIRT instructions.
  16         Extend mtm0, mtm1, mtm2, mtp0, mtp1, mtp2 instructions to take another
  17         operand for IOCT3.
  18
  19 2014-10-29  Nick Clifton  <nickc@redhat.com>
  20
  21         * po/de.po: Updated German translation.
  22
  23 2014-10-23  Sandra Loosemore  <sandra@codesourcery.com>
  24
  25         * nios2-opc.c (nios2_builtin_regs): Add regtype field initializers.
  26         (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.  Use new
  27         MATCH_R1_<insn> and MASK_R1_<insn> macros in initializers.  Add
  28         size and format initializers.  Merge 'b' arguments into 'j'.
  29         (NIOS2_NUM_OPCODES): Adjust definition.
  30         (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
  31         (nios2_opcodes): Adjust.
  32         (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
  33         * nios2-dis.c (INSNLEN): Update comment.
  34         (nios2_hash_init, nios2_hash): Delete.
  35         (OPCODE_HASH_SIZE): New.
  36         (nios2_r1_extract_opcode): New.
  37         (nios2_disassembler_state): New.
  38         (nios2_r1_disassembler_state): New.
  39         (nios2_init_opcode_hash): Add state parameter.  Adjust to use it.
  40         (nios2_find_opcode_hash): Use state object.
  41         (bad_opcode): New.
  42         (nios2_print_insn_arg): Add op parameter.  Use it to access
  43         format.  Remove 'b' case.
  44         (nios2_disassemble): Remove special case for nop.  Remove
  45         hard-coded instruction size.
  46
  47 2014-10-21  Jan Beulich  <jbeulich@suse.com>
  48
  49         * ppc-opc.c (powerpc_opcodes): Enable msgclr and msgsnd on Power8.
  50
  51 2014-10-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
  52
  53         * sparc-opc.c (sparc-opcodes): Fix several misplaced hwcap
  54         entries.
  55         Annotate several instructions with the HWCAP2_VIS3B hwcap.
  56
  57 2014-10-15  Tristan Gingold  <gingold@adacore.com>
  58
  59         * configure: Regenerate.
  60
  61 2014-10-09  Jose E. Marchesi  &lt;jose.marchesi@oracle.com&gt;
  62
  63         * sparc-opc.c (sparc-opcodes): Remove instructions `chkpt',
  64         `commit', `random', `wr r,r,%cps', `wr r,i,%cps' and `rd %cps,r'.
  65         Annotate table with HWCAP2 bits.
  66         Add instructions xmontmul, xmontsqr, xmpmul.
  67         (sparc-opcodes): Add the `mwait',  `wr r,r,%mwait', `wr
  68         r,i,%mwait' and `rd %mwait,r' instructions.
  69         Add rd/wr instructions for accessing the %mcdper ancillary state
  70         register.
  71         (sparc-opcodes): Add sparc5/vis4.0 instructions:
  72         subxc, subxccc, fpadd8, fpadds8, fpaddus8, fpaddus16, fpcmple8,
  73         fpcmpgt8, fpcmpule16, fpcmpugt16, fpcmpule32, fpcmpugt32, fpmax8,
  74         fpmax16, fpmax32, fpmaxu8, fpmaxu16, fpmaxu32, fpmin8, fpmin16,
  75         fpmin32, fpminu8, fpminu16, fpminu32, fpsub8, fpsubs8, fpsubus8,
  76         fpsubus16, and faligndatai.
  77         * sparc-dis.c (v9a_asr_reg_names): Add the %mwait (%asr28)
  78         ancillary state register to the table.
  79         (print_insn_sparc): Handle the %mcdper ancillary state register.
  80         (print_insn_sparc): Handle new operand type '}'.
  81
  82 2014-09-22  H.J. Lu  <hongjiu.lu@intel.com>
  83
  84         * i386-dis.c (MOD_0F20): Removed.
  85         (MOD_0F21): Likewise.
  86         (MOD_0F22): Likewise.
  87         (MOD_0F23): Likewise.
  88         (dis386_twobyte): Replace MOD_0F20, MOD_0F21, MOD_0F22 and
  89         MOD_0F23 with "movZ".
  90         (mod_table): Remove MOD_0F20, MOD_0F21, MOD_0F22 and MOD_0F23.
  91         (OP_R): Check mod/rm byte and call OP_E_register.
  92
  93 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
  94
  95         * nds32-asm.c (nds32_opcodes, operand_fields, keyword_im5_i,
  96         keyword_im5_m, keyword_accumulator, keyword_aridx, keyword_aridx2,
  97         keyword_aridxi): Add audio ISA extension.
  98         (keyword_gpr, keyword_usr, keyword_sr, keyword_cp, keyword_cpr,
  99         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm, keyword_dpref_st,
 100         keyword_cctl_lv, keyword_standby_st, keyword_msync_st): Adjust scrope
 101         for nds32-dis.c using.
 102         (build_opcode_syntax): Remove dead code.
 103         (parse_re, parse_a30b20, parse_rt21, parse_rte_start, parse_rte_end,
 104         parse_rte69_start, parse_rte69_end, parse_im5_ip, parse_im5_mr,
 105         parse_im6_ip, parse_im6_iq, parse_im6_mr, parse_im6_ms): Add audio ISA
 106         operand parser.
 107         * nds32-asm.h: Declare.
 108         * nds32-dis.c: Use array nds32_opcodes to disassemble instead of
 109         decoding by switch.
 110
 111 2014-09-15  Andrew Bennett  <andrew.bennett@imgtec.com>
 112             Matthew Fortune  <matthew.fortune@imgtec.com>
 113
 114         * mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
 115         mips64r6.
 116         (parse_mips_dis_option): Allow MSA and virtualization support for
 117         mips64r6.
 118         (mips_print_arg_state): Add fields dest_regno and seen_dest.
 119         (mips_seen_register): New function.
 120         (print_insn_arg): Refactored code to use mips_seen_register
 121         function.  Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
 122         OP_NON_ZERO_REG.  Changed OP_REPEAT_DEST_REG case to print out
 123         the register rather than aborting.
 124         (print_insn_args): Add length argument.  Add code to correctly
 125         calculate the instruction address for pc relative instructions.
 126         (validate_insn_args): New static function.
 127         (print_insn_mips): Prevent jalx disassembling for r6.  Use
 128         validate_insn_args.
 129         (print_insn_micromips): Use validate_insn_args.
 130         all the arguments are valid.
 131         * mips-formats.h (PREV_CHECK): New define.
 132         * mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
 133         -t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
 134         (RD_pc): New define.
 135         (FS): New define.
 136         (I37): New define.
 137         (I69): New define.
 138         (mips_builtin_opcodes): Add MIPS R6 instructions.  Exclude recoded
 139         MIPS R6 instructions from MIPS R2 instructions.
 140
 141 2014-09-10  H.J. Lu  <hongjiu.lu@intel.com>
 142
 143         * i386-dis.c (dis386): Replace "P" with "%LP" for iret and sysret.
 144         (putop): Handle "%LP".
 145
 146 2014-09-03  Jiong Wang  <jiong.wang@arm.com>
 147
 148         * aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
 149         * aarch64-dis-2.c: Update auto-generated file.
 150
 151 2014-09-03  Jiong Wang  <jiong.wang@arm.com>
 152
 153         * aarch64-tbl.h (QL_R4NIL): New qualifiers.
 154         (aarch64_feature_lse): New feature added.
 155         (LSE): New Added.
 156         (aarch64_opcode_table): New LSE instructions added.  Improve
 157         descriptions for ldarb/ldarh/ldar.
 158         (aarch64_opcode_table): Describe PAIRREG.
 159         * aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
 160         * aarch64-opc.c (fields): Add entry for F_LSE_SZ.
 161         (aarch64_print_operand): Recognize PAIRREG.
 162         (operand_general_constraint_met_p): Check reg pair constraints for CASP
 163         instructions.
 164         * aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
 165         (do_special_decoding): Recognize F_LSE_SZ.
 166         * aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.
 167
 168 2014-08-26  Maciej W. Rozycki  <macro@codesourcery.com>
 169
 170         * micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
 171         (micromips_opcodes): Use "+J" in place of "B" for "hypcall",
 172         "sdbbp", "syscall" and "wait".
 173
 174 2014-08-21  Nathan Sidwell  <nathan@codesourcery.com>
 175             Maciej W. Rozycki  <macro@codesourcery.com>
 176
 177         * arm-dis.c (print_arm_address): Negate the GPR-relative offset
 178         returned if the U bit is set.
 179
 180 2014-08-21  Maciej W. Rozycki  <macro@codesourcery.com>
 181
 182         * micromips-opc.c (micromips_opcodes): Remove #ifdef-ed out
 183         48-bit "li" encoding.
 184
 185 2014-08-19  Andreas Arnez  <arnez@linux.vnet.ibm.com>
 186
 187         * s390-dis.c (s390_insn_length, s390_insn_matches_opcode)
 188         (s390_print_insn_with_opcode, opcode_mask_more_specific): New
 189         static functions, code was moved from...
 190         (print_insn_s390): ...here.
 191         (s390_extract_operand): Adjust comment.  Change type of first
 192         parameter from 'unsigned char *' to 'const bfd_byte *'.
 193         (union operand_value): New.
 194         (s390_extract_operand): Change return type to union operand_value.
 195         Also avoid integer overflow in sign-extension.
 196         (s390_print_insn_with_opcode): Adjust to changed return value from
 197         s390_extract_operand().  Change "%i" printf format to "%u" for
 198         unsigned values.
 199         (init_disasm): Simplify initialization of opc_index[].  This also
 200         fixes an access after the last element of s390_opcodes[].
 201         (print_insn_s390): Simplify the opcode search loop.
 202         Check architecture mask against all searched opcodes, not just the
 203         first matching one.
 204         (s390_print_insn_with_opcode): Drop function pointer dereferences
 205         without effect.
 206         (print_insn_s390): Likewise.
 207         (s390_insn_length): Simplify formula for return value.
 208         (s390_print_insn_with_opcode): Avoid special handling for the
 209         separator before the first operand.  Use new local variable
 210         'flags' in place of 'operand->flags'.
 211
 212 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 213
 214         * bfin-dis.c (struct private): Change int's to bfd_boolean's.
 215         (decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
 216         decode_dagMODik_0, decode_LDIMMhalf_0, decode_linkage_0):
 217         Change assignment of 1 to priv->comment to TRUE.
 218         (print_insn_bfin): Change legal to a bfd_boolean.  Change
 219         assignment of 0/1 with priv comment and parallel and legal
 220         to FALSE/TRUE.
 221
 222 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 223
 224         * bfin-dis.c (OUT): Define.
 225         (decode_CC2stat_0): Declare new op_names array.
 226         Replace multiple if statements with a single one.
 227
 228 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 229
 230         * bfin-dis.c (struct private): Add iw0.
 231         (_print_insn_bfin): Assign iw0 to priv.iw0.
 232         (print_insn_bfin): Drop ifetch and use priv.iw0.
 233
 234 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 235
 236         * bfin-dis.c (comment, parallel): Move from global scope ...
 237         (struct private): ... to this new struct.
 238         (decode_ProgCtrl_0, decode_CaCTRL_0, decode_PushPopReg_0,
 239         decode_PushPopMultiple_0, decode_ccMV_0, decode_CCflag_0,
 240         decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
 241         decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
 242         decode_dagMODik_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
 243         decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
 244         decode_pseudoOChar_0, decode_pseudodbg_assert_0, _print_insn_bfin,
 245         print_insn_bfin): Declare private struct.  Use priv's comment and
 246         parallel members.
 247
 248 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 249
 250         * bfin-dis.c (ifetch): Do not align pc to 2 bytes.
 251         (_print_insn_bfin): Add check for unaligned pc.
 252
 253 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 254
 255         * bfin-dis.c (ifetch): New function.
 256         (_print_insn_bfin, print_insn_bfin): Call new ifetch and return
 257         -1 when it errors.
 258
 259 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
 260
 261         * micromips-opc.c (COD): Rename throughout to...
 262         (CM): New define, update to use INSN_COPROC_MOVE.
 263         (LCD): Rename throughout to...
 264         (LC): New define, update to use INSN_LOAD_COPROC.
 265         * mips-opc.c: Likewise.
 266
 267 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
 268
 269         * micromips-opc.c (COD, LCD) New macros.
 270         (cfc1, ctc1): Remove FP_S attribute.
 271         (dmfc1, mfc1, mfhc1): Add LCD attribute.
 272         (dmtc1, mtc1, mthc1): Add COD attribute.
 273         * mips-opc.c (cfc1, cftc1, ctc, cttc1): Remove FP_S attribute.
 274
 275 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 276             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 277             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 278             Sergey Lega  <sergey.s.lega@intel.com>
 279             Anna Tikhonova  <anna.tikhonova@intel.com>
 280             Ilya Tocar  <ilya.tocar@intel.com>
 281             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 282             Ilya Verbin  <ilya.verbin@intel.com>
 283             Kirill Yukhin  <kirill.yukhin@intel.com>
 284             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 285
 286         * i386-dis-evex.h: Updated.
 287         * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
 288         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0F3A16,
 289         PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51,
 290         PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
 291         PREFIX_EVEX_0F3A67.
 292         (VEX_LEN enum): Add VEX_LEN_0F92_P_2, VEX_LEN_0F93_P_2,
 293         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_2_LEN_0.
 294         (VEX_W enum): Add EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 295         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, EVEX_W_0F57_P_0,
 296         EVEX_W_0F57_P_2, EVEX_W_0F78_P_2, EVEX_W_0F79_P_2, EVEX_W_0F7A_P_2,
 297         EVEX_W_0F7B_P_2, EVEX_W_0F3838_P_1, EVEX_W_0F3839_P_1,
 298         EVEX_W_0F3A16_P_2, EVEX_W_0F3A22_P_2, EVEX_W_0F3A50_P_2,
 299         EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2,
 300         EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2.
 301         (prefix_table): Add entries for new instructions.
 302         (vex_len_table): Ditto.
 303         (vex_w_table): Ditto.
 304         (OP_E_memory): Update xmmq_mode handling.
 305         * i386-gen.c (cpu_flag_init): Add CPU_AVX512DQ_FLAGS.
 306         (cpu_flags): Add CpuAVX512DQ.
 307         * i386-init.h: Regenerared.
 308         * i386-opc.h (CpuAVX512DQ): New.
 309         (i386_cpu_flags): Add cpuavx512dq.
 310         * i386-opc.tbl: Add AVX512DQ instructions.
 311         * i386-tbl.h: Regenerate.
 312
 313 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 314             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 315             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 316             Sergey Lega  <sergey.s.lega@intel.com>
 317             Anna Tikhonova  <anna.tikhonova@intel.com>
 318             Ilya Tocar  <ilya.tocar@intel.com>
 319             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 320             Ilya Verbin  <ilya.verbin@intel.com>
 321             Kirill Yukhin  <kirill.yukhin@intel.com>
 322             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 323
 324         * i386-dis-evex.h: Add new instructions (prefixes bellow).
 325         * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE.
 326         (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71.
 327         (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31,
 328         PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63,
 329         PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
 330         PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4,
 331         PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7,
 332         PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
 333         PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9,
 334         PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
 335         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4,
 336         PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA,
 337         PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
 338         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9,
 339         PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804,
 340         PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D,
 341         PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830,
 342         PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866,
 343         PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A,
 344         PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F,
 345         PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E,
 346         PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42.
 347         (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2,
 348         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 349         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2,
 350         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0,
 351         VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1,
 352         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1,
 353         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 354         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0,
 355         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0,
 356         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0,
 357         VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0.
 358         (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3,
 359         EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2,
 360         EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1,
 361         EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2,
 362         EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2,
 363         EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2,
 364         EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2.
 365         (prefix_table): Add entries for new instructions.
 366         (vex_table) : Ditto.
 367         (vex_len_table): Ditto.
 368         (vex_w_table): Ditto.
 369         (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode,
 370         mask_bd_mode handling.
 371         (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode
 372         handling.
 373         (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode
 374         handling.
 375         (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling.
 376         (OP_EX): Add dqw_swap_mode handling.
 377         (OP_VEX): Add mask_bd_mode handling.
 378         (OP_Mask): Add mask_bd_mode handling.
 379         * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS.
 380         (cpu_flags): Add CpuAVX512BW.
 381         * i386-init.h: Regenerated.
 382         * i386-opc.h (CpuAVX512BW): New.
 383         (i386_cpu_flags): Add cpuavx512bw.
 384         * i386-opc.tbl: Add AVX512BW instructions.
 385         * i386-tbl.h: Regenerate.
 386
 387 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 388             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 389             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 390             Sergey Lega  <sergey.s.lega@intel.com>
 391             Anna Tikhonova  <anna.tikhonova@intel.com>
 392             Ilya Tocar  <ilya.tocar@intel.com>
 393             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 394             Ilya Verbin  <ilya.verbin@intel.com>
 395             Kirill Yukhin  <kirill.yukhin@intel.com>
 396             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 397
 398         * i386-opc.tbl: Add AVX512VL and AVX512CD instructions.
 399         * i386-tbl.h: Regenerate.
 400
 401 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 402             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 403             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 404             Sergey Lega  <sergey.s.lega@intel.com>
 405             Anna Tikhonova  <anna.tikhonova@intel.com>
 406             Ilya Tocar  <ilya.tocar@intel.com>
 407             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 408             Ilya Verbin  <ilya.verbin@intel.com>
 409             Kirill Yukhin  <kirill.yukhin@intel.com>
 410             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 411
 412         * i386-dis.c (intel_operand_size): Support 128/256 length in
 413         vex_vsib_q_w_dq_mode.
 414         (OP_E_memory): Add ymmq_mode handling, handle new broadcast.
 415         * i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS.
 416         (cpu_flags): Add CpuAVX512VL.
 417         * i386-init.h: Regenerated.
 418         * i386-opc.h (CpuAVX512VL): New.
 419         (i386_cpu_flags): Add cpuavx512vl.
 420         (BROADCAST_1TO4, BROADCAST_1TO2): Define.
 421         * i386-opc.tbl: Add AVX512VL instructions.
 422         * i386-tbl.h: Regenerate.
 423
 424 2014-07-20  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>
 425
 426         * or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
 427         * or1k-opinst.c: Regenerate.
 428
 429 2014-07-08  Ilya Tocar  <ilya.tocar@intel.com>
 430
 431         * i386-dis-evex.h (EVEX_W_0F10_P_1_M_1): Fix vmovss.
 432         (EVEX_W_0F10_P_3_M_1): Fix vmovsd.
 433
 434 2014-07-04  Alan Modra  <amodra@gmail.com>
 435
 436         * configure.ac: Rename from configure.in.
 437         * Makefile.in: Regenerate.
 438         * config.in: Regenerate.
 439
 440 2014-07-04  Alan Modra  <amodra@gmail.com>
 441
 442         * configure.in: Include bfd/version.m4.
 443         (AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
 444         (BFD_VERSION): Delete.
 445         * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
 446         * configure: Regenerate.
 447         * Makefile.in: Regenerate.
 448
 449 2014-07-01  Barney Stratford   <barney_stratford@fastmail.fm>
 450             Senthil Kumar Selvaraj  <senthil_kumar.selvaraj@atmel.com>
 451             Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 452             Soundararajan  <Sounderarajan.D@atmel.com>
 453
 454         * avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
 455         (print_insn_avr): Do not select opcode if insn ISA is avrtiny and
 456         machine is not avrtiny.
 457
 458 2014-06-26  Philippe De Muyter <phdm@macqel.be>
 459
 460         * or1k-desc.h (spr_field_masks): Add U suffix to the end of long
 461         constants.
 462
 463 2014-06-12  Alan Modra  <amodra@gmail.com>
 464
 465         * or1k-asm.c, * or1k-desc.c, * or1k-desc.h, * or1k-dis.c,
 466         * or1k-ibld.c, * or1k-opc.c, * or1k-opc.h, * or1k-opinst.c: Regenerate.
 467
 468 2014-06-10  H.J. Lu  <hongjiu.lu@intel.com>
 469
 470         * i386-dis.c (fwait_prefix): New.
 471         (ckprefix): Set fwait_prefix.
 472         (print_insn): Properly print prefixes before fwait.
 473
 474 2014-06-07  Alan Modra  <amodra@gmail.com>
 475
 476         * ppc-opc.c (UISIGNOPT): Define and use with cmpli.
 477
 478 2014-06-05  Joel Brobecker  <brobecker@adacore.com>
 479
 480         * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
 481         bfd's development.sh.
 482         * Makefile.in, configure: Regenerate.
 483
 484 2014-06-03  Nick Clifton  <nickc@redhat.com>
 485
 486         * msp430-dis.c (msp430_doubleoperand): Use extension_word to
 487         decide when extended addressing is being used.
 488
 489 2014-06-02  Eric Botcazou  <ebotcazou@adacore.com>
 490
 491         * sparc-opc.c (cas): Disable for LEON.
 492         (casl): Likewise.
 493
 494 2014-05-20  Alan Modra  <amodra@gmail.com>
 495
 496         * m68k-dis.c: Don't include setjmp.h.
 497
 498 2014-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 499
 500         * i386-dis.c (ADDR16_PREFIX): Removed.
 501         (ADDR32_PREFIX): Likewise.
 502         (DATA16_PREFIX): Likewise.
 503         (DATA32_PREFIX): Likewise.
 504         (prefix_name): Updated.
 505         (print_insn): Simplify data and address size prefixes processing.
 506
 507 2014-05-08  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>
 508
 509         * or1k-desc.c: Regenerated.
 510         * or1k-desc.h: Likewise.
 511         * or1k-opc.c: Likewise.
 512         * or1k-opc.h: Likewise.
 513         * or1k-opinst.c: Likewise.
 514
 515 2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
 516
 517         * mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
 518         (I34): New define.
 519         (I36): New define.
 520         (I66): New define.
 521         (I68): New define.
 522         * mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
 523         mips64r5.
 524         (parse_mips_dis_option): Update MSA and virtualization support to
 525         allow mips64r3 and mips64r5.
 526
 527 2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
 528
 529         * mips-opc.c (G3): Remove I4.
 530
 531 2014-05-05  H.J. Lu  <hongjiu.lu@intel.com>
 532
 533         PR binutils/16893
 534         * i386-dis.c (twobyte_has_mandatory_prefix): New variable.
 535         (end_codep): Likewise.
 536         (mandatory_prefix): Likewise.
 537         (active_seg_prefix): Likewise.
 538         (ckprefix): Set active_seg_prefix to the active segment register
 539         prefix.
 540         (seg_prefix): Removed.
 541         (get_valid_dis386): Use the last of PREFIX_REPNZ and PREFIX_REPZ
 542         for prefix index.  Ignore the index if it is invalid and the
 543         mandatory prefix isn't required.
 544         (print_insn): Set mandatory_prefix if the PREFIX_XXX prefix is
 545         mandatory.  Don't set PREFIX_REPZ/PREFIX_REPNZ/PREFIX_LOCK bits
 546         in used_prefixes here.  Don't print unused prefixes.  Check
 547         active_seg_prefix for the active segment register prefix.
 548         Restore the DFLAG bit in sizeflag if the data size prefix is
 549         unused.  Check the unused mandatory PREFIX_XXX prefixes
 550         (append_seg): Only print the segment register which gets used.
 551         (OP_E_memory): Check active_seg_prefix for the segment register
 552         prefix.
 553         (OP_OFF): Likewise.
 554         (OP_OFF64): Likewise.
 555         (OP_DSreg): Set active_seg_prefix to PREFIX_DS if it is unset.
 556
 557 2014-05-02  H.J. Lu  <hongjiu.lu@intel.com>
 558
 559         PR binutils/16886
 560         * config.in: Regenerated.
 561         * configure: Likewise.
 562         * configure.in: Check if sigsetjmp is available.
 563         * h8500-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 564         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 565         (print_insn_h8500): Replace setjmp with OPCODES_SIGSETJMP.
 566         * i386-dis.c (dis_private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 567         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 568         (print_insn): Replace setjmp with OPCODES_SIGSETJMP.
 569         * ns32k-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 570         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 571         (print_insn_ns32k): Replace setjmp with OPCODES_SIGSETJMP.
 572         * sysdep.h (OPCODES_SIGJMP_BUF): New macro.
 573         (OPCODES_SIGSETJMP): Likewise.
 574         (OPCODES_SIGLONGJMP): Likewise.
 575         * vax-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 576         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 577         (print_insn_vax): Replace setjmp with OPCODES_SIGSETJMP.
 578         * xtensa-dis.c (dis_private): Replace jmp_buf with
 579         OPCODES_SIGJMP_BUF.
 580         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 581         (print_insn_xtensa): Replace setjmp with OPCODES_SIGSETJMP.
 582         * z8k-dis.c(instr_data_s): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 583         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 584         (print_insn_z8k): Replace setjmp with OPCODES_SIGSETJMP.
 585
 586 2014-05-01  H.J. Lu  <hongjiu.lu@intel.com>
 587
 588         PR binutils/16891
 589         * i386-dis.c (print_insn): Handle prefixes before fwait.
 590
 591 2014-04-26  Alan Modra  <amodra@gmail.com>
 592
 593         * po/POTFILES.in: Regenerate.
 594
 595 2014-04-23  Andrew Bennett  <andrew.bennett@imgtec.com>
 596
 597         * mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
 598         to allow the MIPS XPA ASE.
 599         (parse_mips_dis_option): Process the -Mxpa option.
 600         * mips-opc.c (XPA): New define.
 601         (mips_builtin_opcodes): Add MIPS XPA instructions and move the
 602         locations of the ctc0 and cfc0 instructions.
 603
 604 2014-04-22  Christian Svensson  <blue@cmd.nu>
 605
 606         * Makefile.am: Remove openrisc and or32 support.  Add support for or1k.
 607         * configure.in: Likewise.
 608         * disassemble.c: Likewise.
 609         * or1k-asm.c: New file.
 610         * or1k-desc.c: New file.
 611         * or1k-desc.h: New file.
 612         * or1k-dis.c: New file.
 613         * or1k-ibld.c: New file.
 614         * or1k-opc.c: New file.
 615         * or1k-opc.h: New file.
 616         * or1k-opinst.c: New file.
 617         * Makefile.in: Regenerate.
 618         * configure: Regenerate.
 619         * openrisc-asm.c: Delete.
 620         * openrisc-desc.c: Delete.
 621         * openrisc-desc.h: Delete.
 622         * openrisc-dis.c: Delete.
 623         * openrisc-ibld.c: Delete.
 624         * openrisc-opc.c: Delete.
 625         * openrisc-opc.h: Delete.
 626         * or32-dis.c: Delete.
 627         * or32-opc.c: Delete.
 628
 629 2014-04-04  Ilya Tocar  <ilya.tocar@intel.com>
 630
 631         * i386-dis.c (rm_table): Add encls, enclu.
 632         * i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
 633         (cpu_flags): Add CpuSE1.
 634         * i386-opc.h (enum): Add CpuSE1.
 635         (i386_cpu_flags): Add cpuse1.
 636         * i386-opc.tbl: Add encls, enclu.
 637         * i386-init.h: Regenerated.
 638         * i386-tbl.h: Likewise.
 639
 640 2014-04-02  Anthony Green  <green@moxielogic.com>
 641
 642         * moxie-opc.c (moxie_form1_opc_info): Add sign-extension
 643         instructions, sex.b and sex.s.
 644
 645 2014-03-26  Jiong Wang  <jiong.wang@arm.com>
 646
 647         * aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
 648         instructions.
 649
 650 2014-03-20  Ilya Tocar  <ilya.tocar@intel.com>
 651
 652         * i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
 653         vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
 654         vscatterqps.
 655         * i386-tbl.h: Regenerate.
 656
 657 2014-03-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 658
 659         * sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
 660         %hstick_enable added.
 661
 662 2014-03-19  Nick Clifton  <nickc@redhat.com>
 663
 664         * rx-decode.opc (bwl): Allow for bogus instructions with a size
 665         field of 3.
 666         (sbwl, ubwl, SCALE): Likewise.
 667         * rx-decode.c: Regenerate.
 668
 669 2014-03-12  Alan Modra  <amodra@gmail.com>
 670
 671         * Makefile.in: Regenerate.
 672
 673 2014-03-05  Alan Modra  <amodra@gmail.com>
 674
 675         Update copyright years.
 676
 677 2014-03-04  Heiher  <r@hev.cc>
 678
 679         * mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
 680
 681 2014-03-04  Richard Sandiford  <rdsandiford@googlemail.com>
 682
 683         * mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
 684         so that they come after the Loongson extensions.
 685
 686 2014-03-03  Alan Modra  <amodra@gmail.com>
 687
 688         * i386-gen.c (process_copyright): Emit copyright notice on one line.
 689
 690 2014-02-28  Alan Modra  <amodra@gmail.com>
 691
 692         * msp430-decode.c: Regenerate.
 693
 694 2014-02-27  Jiong Wang  <jiong.wang@arm.com>
 695
 696         * aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
 697         FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.
 698
 699 2014-02-27  Yufeng Zhang  <yufeng.zhang@arm.com>
 700
 701         * aarch64-opc.c (print_register_offset_address): Call
 702         get_int_reg_name to prepare the register name.
 703
 704 2014-02-25  Ilya Tocar  <ilya.tocar@intel.com>
 705
 706         * i386-opc.tbl: Remove wrong variant of vcvtps2ph
 707         * i386-tbl.h: Regenerate.
 708
 709 2014-02-20  Ilya Tocar  <ilya.tocar@intel.com>
 710
 711         * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
 712         (cpu_flags): Add CpuPREFETCHWT1.
 713         * i386-init.h: Regenerate.
 714         * i386-opc.h (CpuPREFETCHWT1): New.
 715         (i386_cpu_flags): Add cpuprefetchwt1.
 716         * i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1.
 717         * i386-tbl.h: Regenerate.
 718
 719 2014-02-20  Ilya Tocar  <ilya.tocar@intel.com>
 720
 721         * i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD,
 722         to CpuAVX512F.
 723         * i386-tbl.h: Regenerate.
 724
 725 2014-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 726
 727         * i386-gen.c (output_cpu_flags): Don't output trailing space.
 728         (output_opcode_modifier): Likewise.
 729         (output_operand_type): Likewise.
 730         * i386-init.h: Regenerated.
 731         * i386-tbl.h: Likewise.
 732
 733 2014-02-12  Ilya Tocar  <ilya.tocar@intel.com>
 734
 735         * i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
 736         MOD_0FC7_REG_5.
 737         (PREFIX enum): Add PREFIX_0FAE_REG_7.
 738         (reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
 739         (prefix_table): Add clflusopt.
 740         (mod_table): Add xrstors, xsavec, xsaves.
 741         * i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
 742         CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
 743         (cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
 744         * i386-init.h: Regenerate.
 745         * i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
 746         xsaves64, xsavec, xsavec64.
 747         * i386-tbl.h: Regenerate.
 748
 749 2014-02-10  Alan Modra  <amodra@gmail.com>
 750
 751         * po/POTFILES.in: Regenerate.
 752         * po/opcodes.pot: Regenerate.
 753
 754 2014-01-30  Michael Zolotukhin  <michael.v.zolotukhin@gmail.com>
 755             Jan Beulich  <jbeulich@suse.com>
 756
 757         PR binutils/16490
 758         * i386-dis.c (OP_E_memory): Fix shift computation for
 759         vex_vsib_q_w_dq_mode.
 760
 761 2014-01-09  Bradley Nelson  <bradnelson@google.com>
 762             Roland McGrath  <mcgrathr@google.com>
 763
 764         * i386-dis.c (print_insn): Do not touch all_prefixes[-1] when
 765         last_rex_prefix is -1.
 766
 767 2014-01-08  H.J. Lu  <hongjiu.lu@intel.com>
 768
 769         * i386-gen.c (process_copyright): Update copyright year to 2014.
 770
 771 2014-01-03  Maciej W. Rozycki  <macro@codesourcery.com>
 772
 773         * nds32-asm.c (parse_operand): Fix out-of-range integer constant.
 774
 775 For older changes see ChangeLog-2013
 776 \f
 777 Copyright (C) 2014 Free Software Foundation, Inc.
 778
 779 Copying and distribution of this file, with or without modification,
 780 are permitted in any medium without royalty provided the copyright
 781 notice and this notice are preserved.
 782
 783 Local Variables:
 784 mode: change-log
 785 left-margin: 8
 786 fill-column: 74
 787 version-control: never
 788 End: