opcodes/ChangeLog

   1 2015-06-22  Nick Clifton  <nickc@redhat.com>
   2
   3         * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
   4         requested region lies beyond it.
   5         * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
   6         looking for 32-bit insns.
   7         * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
   8         data.
   9         * sh-dis.c (print_insn_sh): Likewise.
  10         * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
  11         blocks of instructions.
  12         * vax-dis.c (print_insn_vax): Check that the requested address
  13         does not clash with the stop_vma.
  14
  15 2015-06-19  Peter Bergner  <bergner@vnet.ibm.com>
  16
  17         * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
  18         * ppc-opc.c (FXM4): Add non-zero optional value.
  19         (TBR): Likewise.
  20         (SXL): Likewise.
  21         (insert_fxm): Handle new default operand value.
  22         (extract_fxm): Likewise.
  23         (insert_tbr): Likewise.
  24         (extract_tbr): Likewise.
  25
  26 2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
  27
  28         * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
  29
  30 2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  31
  32         * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
  33
  34 2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>
  35
  36         * ppc-opc.c: Add comment accidentally removed by old commit.
  37         (MTMSRD_L): Delete.
  38
  39 2015-06-04  Nick Clifton  <nickc@redhat.com>
  40
  41         PR 18474
  42         * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
  43
  44 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
  45
  46         * arm-dis.c (arm_opcodes): Add "setpan".
  47         (thumb_opcodes): Add "setpan".
  48
  49 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
  50
  51         * arm-dis.c (select_arm_features): Rework to avoid used of redefined
  52         macros.
  53
  54 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
  55
  56         * aarch64-tbl.h (aarch64_feature_rdma): New.
  57         (RDMA): New.
  58         (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
  59         * aarch64-asm-2.c: Regenerate.
  60         * aarch64-dis-2.c: Regenerate.
  61         * aarch64-opc-2.c: Regenerate.
  62
  63 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
  64
  65         * aarch64-tbl.h (aarch64_feature_lor): New.
  66         (LOR): New.
  67         (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
  68         "stllrb", "stllrh".
  69         * aarch64-asm-2.c: Regenerate.
  70         * aarch64-dis-2.c: Regenerate.
  71         * aarch64-opc-2.c: Regenerate.
  72
  73 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
  74
  75         * aarch64-opc.c (F_ARCHEXT): New.
  76         (aarch64_sys_regs): Add "pan".
  77         (aarch64_sys_reg_supported_p): New.
  78         (aarch64_pstatefields): Add "pan".
  79         (aarch64_pstatefield_supported_p): New.
  80
  81 2015-06-01  Jan Beulich  <jbeulich@suse.com>
  82
  83         * i386-tbl.h: Regenerate.
  84
  85 2015-06-01  Jan Beulich  <jbeulich@suse.com>
  86
  87         * i386-dis.c (print_insn): Swap rounding mode specifier and
  88         general purpose register in Intel mode.
  89
  90 2015-06-01  Jan Beulich  <jbeulich@suse.com>
  91
  92         * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
  93         * i386-tbl.h: Regenerate.
  94
  95 2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
  96
  97         * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
  98         * i386-init.h: Regenerated.
  99
 100 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 101
 102         PR binutis/18386
 103         * i386-dis.c: Add comments for '@'.
 104         (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
 105         (enum x86_64_isa): New.
 106         (isa64): Likewise.
 107         (print_i386_disassembler_options): Add amd64 and intel64.
 108         (print_insn): Handle amd64 and intel64.
 109         (putop): Handle '@'.
 110         (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
 111         * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
 112         * i386-opc.h (AMD64): New.
 113         (CpuIntel64): Likewise.
 114         (i386_cpu_flags): Add cpuamd64 and cpuintel64.
 115         * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
 116         Mark direct call/jmp without Disp16|Disp32 as Intel64.
 117         * i386-init.h: Regenerated.
 118         * i386-tbl.h: Likewise.
 119
 120 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
 121
 122         * ppc-opc.c (IH) New define.
 123         (powerpc_opcodes) <wait>: Do not enable for POWER7.
 124         <tlbie>: Add RS operand for POWER7.
 125         <slbia>: Add IH operand for POWER6.
 126
 127 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 128
 129         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
 130         direct branch.
 131         (jmp): Likewise.
 132         * i386-tbl.h: Regenerated.
 133
 134 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 135
 136         * configure.ac: Support bfd_iamcu_arch.
 137         * disassemble.c (disassembler): Support bfd_iamcu_arch.
 138         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
 139         CPU_IAMCU_COMPAT_FLAGS.
 140         (cpu_flags): Add CpuIAMCU.
 141         * i386-opc.h (CpuIAMCU): New.
 142         (i386_cpu_flags): Add cpuiamcu.
 143         * configure: Regenerated.
 144         * i386-init.h: Likewise.
 145         * i386-tbl.h: Likewise.
 146
 147 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
 148
 149         PR binutis/18386
 150         * i386-dis.c (X86_64_E8): New.
 151         (X86_64_E9): Likewise.
 152         Update comments on 'T', 'U', 'V'.  Add comments for '^'.
 153         (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
 154         (x86_64_table): Add X86_64_E8 and X86_64_E9.
 155         (mod_table): Replace {T|} with ^ on Jcall/Jmp.
 156         (putop): Handle '^'.
 157         (OP_J): Ignore the operand size prefix in 64-bit.  Don't check
 158         REX_W.
 159
 160 2015-04-30  DJ Delorie  <dj@redhat.com>
 161
 162         * disassemble.c (disassembler): Choose suitable disassembler based
 163         on E_ABI.
 164         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
 165         it to decode mul/div insns.
 166         * rl78-decode.c: Regenerate.
 167         * rl78-dis.c (print_insn_rl78): Rename to...
 168         (print_insn_rl78_common): ...this, take ISA parameter.
 169         (print_insn_rl78): New.
 170         (print_insn_rl78_g10): New.
 171         (print_insn_rl78_g13): New.
 172         (print_insn_rl78_g14): New.
 173         (rl78_get_disassembler): New.
 174
 175 2015-04-29  Nick Clifton  <nickc@redhat.com>
 176
 177         * po/fr.po: Updated French translation.
 178
 179 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
 180
 181         * ppc-opc.c (DCBT_EO): New define.
 182         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
 183         <lharx>: Likewise.
 184         <stbcx.>: Likewise.
 185         <sthcx.>: Likewise.
 186         <waitrsv>: Do not enable for POWER7 and later.
 187         <waitimpl>: Likewise.
 188         <dcbt>: Default to the two operand form of the instruction for all
 189         "old" cpus.  For "new" cpus, use the operand ordering that matches
 190         whether the cpu is server or embedded.
 191         <dcbtst>: Likewise.
 192
 193 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 194
 195         * s390-opc.c: New instruction type VV0UU2.
 196         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
 197         and WFC.
 198
 199 2015-04-23  Jan Beulich  <jbeulich@suse.com>
 200
 201         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
 202         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
 203         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
 204         (vfpclasspd, vfpclassps): Add %XZ.
 205
 206 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 207
 208         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
 209         (PREFIX_UD_REPZ): Likewise.
 210         (PREFIX_UD_REPNZ): Likewise.
 211         (PREFIX_UD_DATA): Likewise.
 212         (PREFIX_UD_ADDR): Likewise.
 213         (PREFIX_UD_LOCK): Likewise.
 214
 215 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 216
 217         * i386-dis.c (prefix_requirement): Removed.
 218         (print_insn): Don't set prefix_requirement.  Check
 219         dp->prefix_requirement instead of prefix_requirement.
 220
 221 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 222
 223         PR binutils/17898
 224         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
 225         (PREFIX_MOD_0_0FC7_REG_6): This.
 226         (PREFIX_MOD_3_0FC7_REG_6): New.
 227         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
 228         (prefix_table): Replace PREFIX_0FC7_REG_6 with
 229         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
 230         PREFIX_MOD_3_0FC7_REG_7.
 231         (mod_table): Replace PREFIX_0FC7_REG_6 with
 232         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
 233         PREFIX_MOD_3_0FC7_REG_7.
 234
 235 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 236
 237         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
 238         (PREFIX_MANDATORY_REPNZ): Likewise.
 239         (PREFIX_MANDATORY_DATA): Likewise.
 240         (PREFIX_MANDATORY_ADDR): Likewise.
 241         (PREFIX_MANDATORY_LOCK): Likewise.
 242         (PREFIX_MANDATORY): Likewise.
 243         (PREFIX_UD_SHIFT): Set to 8
 244         (PREFIX_UD_REPZ): Updated.
 245         (PREFIX_UD_REPNZ): Likewise.
 246         (PREFIX_UD_DATA): Likewise.
 247         (PREFIX_UD_ADDR): Likewise.
 248         (PREFIX_UD_LOCK): Likewise.
 249         (PREFIX_IGNORED_SHIFT): New.
 250         (PREFIX_IGNORED_REPZ): Likewise.
 251         (PREFIX_IGNORED_REPNZ): Likewise.
 252         (PREFIX_IGNORED_DATA): Likewise.
 253         (PREFIX_IGNORED_ADDR): Likewise.
 254         (PREFIX_IGNORED_LOCK): Likewise.
 255         (PREFIX_OPCODE): Likewise.
 256         (PREFIX_IGNORED): Likewise.
 257         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 258         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 259         (three_byte_table): Likewise.
 260         (mod_table): Likewise.
 261         (mandatory_prefix): Renamed to ...
 262         (prefix_requirement): This.
 263         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 264         Update PREFIX_90 entry.
 265         (get_valid_dis386): Check prefix_requirement to see if a prefix
 266         should be ignored.
 267         (print_insn): Replace mandatory_prefix with prefix_requirement.
 268
 269 2015-04-15  Renlin Li  <renlin.li@arm.com>
 270
 271         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
 272         use it for ssat and ssat16.
 273         (print_insn_thumb32): Add handle case for 'D' control code.
 274
 275 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
 276             H.J. Lu  <hongjiu.lu@intel.com>
 277
 278         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
 279         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
 280         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
 281         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
 282         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
 283         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
 284         Fill prefix_requirement field.
 285         (struct dis386): Add prefix_requirement field.
 286         (dis386): Fill prefix_requirement field.
 287         (dis386_twobyte): Ditto.
 288         (twobyte_has_mandatory_prefix_: Remove.
 289         (reg_table): Fill prefix_requirement field.
 290         (prefix_table): Ditto.
 291         (x86_64_table): Ditto.
 292         (three_byte_table): Ditto.
 293         (xop_table): Ditto.
 294         (vex_table): Ditto.
 295         (vex_len_table): Ditto.
 296         (vex_w_table): Ditto.
 297         (mod_table): Ditto.
 298         (bad_opcode): Ditto.
 299         (print_insn): Use prefix_requirement.
 300         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
 301         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
 302         (float_reg): Ditto.
 303
 304 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
 305
 306         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
 307
 308 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 309
 310         * Makefile.in: Regenerated.
 311
 312 2015-03-25  Anton Blanchard  <anton@samba.org>
 313
 314         * ppc-dis.c (disassemble_init_powerpc): Only initialise
 315         powerpc_opcd_indices and vle_opcd_indices once.
 316
 317 2015-03-25  Anton Blanchard  <anton@samba.org>
 318
 319         * ppc-opc.c (powerpc_opcodes): Add slbfee.
 320
 321 2015-03-24  Terry Guo  <terry.guo@arm.com>
 322
 323         * arm-dis.c (opcode32): Updated to use new arm feature struct.
 324         (opcode16): Likewise.
 325         (coprocessor_opcodes): Replace bit with feature struct.
 326         (neon_opcodes): Likewise.
 327         (arm_opcodes): Likewise.
 328         (thumb_opcodes): Likewise.
 329         (thumb32_opcodes): Likewise.
 330         (print_insn_coprocessor): Likewise.
 331         (print_insn_arm): Likewise.
 332         (select_arm_features): Follow new feature struct.
 333
 334 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 335
 336         * i386-dis.c (rm_table): Add clzero.
 337         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
 338         Add CPU_CLZERO_FLAGS.
 339         (cpu_flags): Add CpuCLZERO.
 340         * i386-opc.h: Add CpuCLZERO.
 341         * i386-opc.tbl: Add clzero.
 342         * i386-init.h: Re-generated.
 343         * i386-tbl.h: Re-generated.
 344
 345 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 346
 347         * mips-opc.c (decode_mips_operand): Fix constraint issues
 348         with u and y operands.
 349
 350 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 351
 352         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
 353
 354 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 355
 356         * s390-opc.c: Add new IBM z13 instructions.
 357         * s390-opc.txt: Likewise.
 358
 359 2015-03-10  Renlin Li  <renlin.li@arm.com>
 360
 361         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
 362         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
 363         related alias.
 364         * aarch64-asm-2.c: Regenerate.
 365         * aarch64-dis-2.c: Likewise.
 366         * aarch64-opc-2.c: Likewise.
 367
 368 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
 369
 370         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
 371
 372 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
 373
 374         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
 375         arch_sh_up.
 376         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
 377         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
 378
 379 2015-02-23  Vinay  <Vinay.G@kpit.com>
 380
 381         * rl78-decode.opc (MOV): Added space between two operands for
 382         'mov' instruction in index addressing mode.
 383         * rl78-decode.c: Regenerate.
 384
 385 2015-02-19  Pedro Alves  <palves@redhat.com>
 386
 387         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
 388
 389 2015-02-10  Pedro Alves  <palves@redhat.com>
 390             Tom Tromey  <tromey@redhat.com>
 391
 392         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
 393         microblaze_and, microblaze_xor.
 394         * microblaze-opc.h (opcodes): Adjust.
 395
 396 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
 397
 398         * Makefile.am: Add FT32 files.
 399         * configure.ac: Handle FT32.
 400         * disassemble.c (disassembler): Call print_insn_ft32.
 401         * ft32-dis.c: New file.
 402         * ft32-opc.c: New file.
 403         * Makefile.in: Regenerate.
 404         * configure: Regenerate.
 405         * po/POTFILES.in: Regenerate.
 406
 407 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 408
 409         * nds32-asm.c (keyword_sr): Add new system registers.
 410
 411 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 412
 413         * s390-dis.c (s390_extract_operand): Support vector register
 414         operands.
 415         (s390_print_insn_with_opcode): Support new operands types and add
 416         new handling of optional operands.
 417         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
 418         and include opcode/s390.h instead.
 419         (struct op_struct): New field `flags'.
 420         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
 421         (dumpTable): Dump flags.
 422         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
 423         string.
 424         * s390-opc.c: Add new operands types, instruction formats, and
 425         instruction masks.
 426         (s390_opformats): Add new formats for .insn.
 427         * s390-opc.txt: Add new instructions.
 428
 429 2015-01-01  Alan Modra  <amodra@gmail.com>
 430
 431         Update year range in copyright notice of all files.
 432
 433 For older changes see ChangeLog-2014
 434 \f
 435 Copyright (C) 2015 Free Software Foundation, Inc.
 436
 437 Copying and distribution of this file, with or without modification,
 438 are permitted in any medium without royalty provided the copyright
 439 notice and this notice are preserved.
 440
 441 Local Variables:
 442 mode: change-log
 443 left-margin: 8
 444 fill-column: 74
 445 version-control: never
 446 End: