opcodes/ChangeLog

   1 2016-12-23  Maciej W. Rozycki  <macro@imgtec.com>
   2
   3         * mips-dis.c (print_mips16_insn_arg): Simplify processing of
   4         extended operands.
   5         * mips16-opc.c (decode_mips16_operand): Switch the extended
   6         form of the `<' operand type to LSB position 22.
   7
   8 2016-12-23  Maciej W. Rozycki  <macro@imgtec.com>
   9
  10         * mips16-opc.c (decode_mips16_operand): Replace `0' and `4'
  11         operand codes with `.' and `F' respectively.
  12         (mips16_opcodes): Likewise.
  13
  14 2016-12-23  Maciej W. Rozycki  <macro@imgtec.com>
  15
  16         * mips-dis.c (print_insn_mips16): Disallow EXTEND prefix
  17         matching for INSN2_SHORT_ONLY opcode table entries.
  18         * mips16-opc.c (SH): New macro.
  19         (mips16_opcodes): Set SH in `pinfo2' for non-extensible
  20         instruction entries: "nop", "addu", "and", "break", "cmp",
  21         "daddu", "ddiv", "ddivu", "div", "divu", "dmult", "dmultu",
  22         "drem", "dremu", "dsllv", "dsll", "dsrav", "dsra", "dsrlv",
  23         "dsrl", "dsubu", "exit", "entry", "jalr", "jal", "jr", "j",
  24         "jalrc", "jrc", "mfhi", "mflo", "move", "mult", "multu", "neg",
  25         "not", "or", "rem", "remu", "sllv", "sll", "slt", "sltu",
  26         "srav", "sra", "srlv", "srl", "subu", "xor", "sdbbp", "seb",
  27         "seh", "sew", "zeb", "zeh", "zew" and "extend".
  28
  29 2016-12-23  Maciej W. Rozycki  <macro@imgtec.com>
  30
  31         * mips16-opc.c (decode_mips16_operand) <'6'>: Remove extended
  32         encoding support.
  33
  34 2016-12-23  Maciej W. Rozycki  <macro@imgtec.com>
  35
  36         * mips16-opc.c (mips16_opcodes): Set NODS in `pinfo' for
  37         "extend".
  38
  39 2016-12-23  Maciej W. Rozycki  <macro@imgtec.com>
  40
  41         * mips-dis.c (set_default_mips_dis_options): Use
  42         HAVE_BFD_MIPS_ELF_GET_ABIFLAGS rather than BFD64 to guard the
  43         call to `bfd_mips_elf_get_abiflags'.
  44         * configure.ac: Check for `bfd_mips_elf_get_abiflags' in BFD.
  45         * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add `libbfd.la'.
  46         * aclocal.m4: Regenerate.
  47         * configure: Regenerate.
  48         * config.in: Regenerate.
  49         * Makefile.in: Regenerate.
  50
  51 2016-12-23  Tristan Gingold  <gingold@adacore.com>
  52
  53         * configure: Regenerate.
  54
  55 2016-12-23  Tristan Gingold  <gingold@adacore.com>
  56
  57         * po/opcodes.pot: Regenerate.
  58
  59 2016-12-21  Andrew Waterman  <andrew@sifive.com>
  60
  61         * riscv-opc.c (riscv_opcodes): Reorder jal and call entries.
  62
  63 2016-12-20  Maciej W. Rozycki  <macro@imgtec.com>
  64
  65         * mips-dis.c (mips_arch_choices): Use ISA_MIPS64 rather than
  66         ISA_MIPS3 as the `isa' selection in the `bfd_mach_mips16' entry.
  67         (print_insn_mips16): Check opcode entries for validity against
  68         the ISA level and ASE set selected.
  69
  70 2016-12-20  Maciej W. Rozycki  <macro@imgtec.com>
  71
  72         * mips-dis.c (print_mips16_insn_arg): Always handle `extend' and
  73         `insn' together, with `extend' as the high-order 16 bits.
  74         (match_kind): New enum.
  75         (print_insn_mips16): Rework for 32-bit instruction matching.
  76         Do not dump EXTEND prefixes here.
  77         * mips16-opc.c (mips16_opcodes): Move "extend" entry to the end.
  78         Recode `match' and `mask' fields as 32-bit in absolute "jal" and
  79         "jalx" entries.
  80
  81 2016-12-20  Maciej W. Rozycki  <macro@imgtec.com>
  82
  83         * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
  84         than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu"
  85         INSN_MACRO entries.
  86
  87 2016-12-20  Maciej W. Rozycki  <macro@imgtec.com>
  88
  89         * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
  90         than I1 for the SP-relative "sd"/$ra entry (SDRASP minor
  91         opcode).
  92
  93 2016-12-20  Andrew Waterman  <andrew@sifive.com>
  94
  95         * riscv-opc.c (riscv_opcodes): Rename the "*.sc" instructions to
  96         "*.aqrl".
  97
  98 2016-12-20  Andrew Waterman  <andrew@sifive.com>
  99
 100         * riscv-opc.c (riscv_opcodes): Mark the rd* and csr* aliases as
 101         INSN_ALIAS.
 102
 103 2016-12-20  Andrew Waterman  <andrew@sifive.com>
 104
 105         * riscv-opc.c (riscv_opcodes): Change jr and jalr to "o(s)"
 106         format.
 107
 108 2016-12-20  Andrew Waterman  <andrew@sifive.com>
 109
 110         * riscv-dis.c (riscv_disassemble_insn): Default to the ELF's
 111         XLEN when none is provided.
 112
 113 2016-12-20  Andrew Waterman  <andrew@sifive.com>
 114
 115         * riscv-opc.c: Formatting fixes.
 116
 117 2016-12-20  Alan Modra  <amodra@gmail.com>
 118
 119         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files.
 120         * Makefile.in: Regenerate.
 121         * po/POTFILES.in: Regenerate.
 122
 123 2016-12-19  Maciej W. Rozycki  <macro@imgtec.com>
 124
 125         * mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]:
 126         Only examine ELF file structures here.
 127
 128 2016-12-19  Maciej W. Rozycki  <macro@imgtec.com>
 129
 130         * mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call
 131         `bfd_mips_elf_get_abiflags' here.
 132
 133 2016-12-16  Nick Clifton  <nickc@redhat.com>
 134
 135         * arm-dis.c (print_insn_thumb32): Fix compile time warning
 136         computing value_in_comment.
 137
 138 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
 139
 140         * mips-dis.c (mips_convert_abiflags_ases): New function.
 141         (set_default_mips_dis_options): Also infer ASE flags from ELF
 142         file structures.
 143
 144 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
 145
 146         * mips-dis.c (set_default_mips_dis_options): Reorder ELF file
 147         header flag interpretation code.
 148
 149 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
 150
 151         * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
 152         `pinfo2' with SP-relative "sd" entries.
 153
 154 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
 155
 156         * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e
 157         compact jumps.
 158
 159 2016-12-13 Renlin Li <renlin.li@arm.com>
 160
 161         * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
 162         qualifier.
 163         (operand_general_constraint_met_p): Remove case for CP_REG.
 164         (aarch64_print_operand): Print CRn, CRm operand using imm field.
 165         * aarch64-tbl.h (QL_SYS): Use CR qualifier.
 166         (QL_SYSL): Likewise.
 167         (aarch64_opcode_table): Change CRn, CRm operand class and type.
 168         * aarch64-opc-2.c : Regenerate.
 169         * aarch64-asm-2.c : Likewise.
 170         * aarch64-dis-2.c : Likewise.
 171
 172 2016-12-12  Yao Qi  <yao.qi@linaro.org>
 173
 174         * rx-dis.c: Include <setjmp.h>
 175         (struct private): New.
 176         (rx_get_byte): Check return value of read_memory_func, and
 177         call memory_error_func and OPCODES_SIGLONGJMP on error.
 178         (print_insn_rx): Call OPCODES_SIGSETJMP.
 179
 180 2016-12-12  Yao Qi  <yao.qi@linaro.org>
 181
 182         * rl78-dis.c: Include <setjmp.h>.
 183         (struct private): New.
 184         (rl78_get_byte): Check return value of read_memory_func, and
 185         call memory_error_func and OPCODES_SIGLONGJMP on error.
 186         (print_insn_rl78_common): Call OPCODES_SIGJMP.
 187
 188 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
 189
 190         * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
 191
 192 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
 193
 194         * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
 195         than UINT.
 196
 197 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
 198
 199         * mips-dis.c (print_insn_mips16): Use a tab rather than a space
 200         to separate `extend' and its uninterpreted argument output.
 201         Separate hexadecimal halves of undecoded extended instructions
 202         output.
 203
 204 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
 205
 206         * mips-dis.c (print_mips16_insn_arg): Remove extraneous
 207         indentation space across.
 208
 209 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
 210
 211         * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
 212         adjustment for PC-relative operations following MIPS16e compact
 213         jumps or undefined RR/J(AL)R(C) encodings.
 214
 215 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
 216
 217         * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
 218         variable to `reglane_index'.
 219
 220 2016-12-08  Luis Machado  <lgustavo@codesourcery.com>
 221
 222         * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
 223
 224 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
 225
 226         * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
 227
 228 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
 229
 230         * mips16-opc.c (mips16_opcodes): Update comment naming structure
 231         members.
 232
 233 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
 234
 235         * mips-dis.c (print_mips_disassembler_options): Reformat output.
 236
 237 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 238
 239         * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
 240         (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
 241
 242 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 243
 244         * arm-dis.c (coprocessor_opcodes): Add vjcvt.
 245
 246 2016-12-01  Nick Clifton  <nickc@redhat.com>
 247
 248         PR binutils/20893
 249         * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
 250         opcode designator.
 251
 252 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
 253
 254         * arc-opc.c (insert_ra_chk): New function.
 255         (insert_rb_chk): Likewise.
 256         (insert_rad): Update text error message.
 257         (insert_rcd): Likewise.
 258         (insert_rhv2): Likewise.
 259         (insert_r0): Likewise.
 260         (insert_r1): Likewise.
 261         (insert_r2): Likewise.
 262         (insert_r3): Likewise.
 263         (insert_sp): Likewise.
 264         (insert_gp): Likewise.
 265         (insert_pcl): Likewise.
 266         (insert_blink): Likewise.
 267         (insert_ilink1): Likewise.
 268         (insert_ilink2): Likewise.
 269         (insert_ras): Likewise.
 270         (insert_rbs): Likewise.
 271         (insert_rcs): Likewise.
 272         (insert_simm3s): Likewise.
 273         (insert_rrange): Likewise.
 274         (insert_fpel): Likewise.
 275         (insert_blinkel): Likewise.
 276         (insert_pcel): Likewise.
 277         (insert_nps_3bit_dst): Likewise.
 278         (insert_nps_3bit_dst_short): Likewise.
 279         (insert_nps_3bit_src2_short): Likewise.
 280         (insert_nps_bitop_size_2b): Likewise.
 281         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
 282         (RA_CHK): Define.
 283         (RB): Adjust.
 284         (RB_CHK): Define.
 285         (RC): Adjust.
 286         * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
 287         * arc-tbl.h (div, divu): All instructions are DIVREM class.
 288         Change first insn argument to check for LP_COUNT usage.
 289         (rem): Likewise.
 290         (ld, ldd): All instructions are LOAD class.  Change first insn
 291         argument to check for LP_COUNT usage.
 292         (st, std): All instructions are STORE class.
 293         (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
 294         Change first insn argument to check for LP_COUNT usage.
 295         (mov): All instructions are MOVE class.  Change first insn
 296         argument to check for LP_COUNT usage.
 297
 298 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
 299
 300         * arc-dis.c (is_compatible_p): Remove function.
 301         (skip_this_opcode): Don't add any decoding class to decode list.
 302         Remove warning.
 303         (find_format_from_table): Go through all opcodes, and warn if we
 304         use a guessed mnemonic.
 305
 306 2016-11-28  Ramiro Polla  <ramiro@hex-rays.com>
 307             Amit Pawar  <amit.pawar@amd.com>
 308
 309         PR binutils/20637
 310         * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
 311         instructions.
 312
 313 2016-11-22  Ambrogino Modigliani  <ambrogino.modigliani@gmail.com>
 314
 315         * configure: Regenerate.
 316
 317 2016-11-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 318
 319         * sparc-opc.c (HWS_V8): Definition moved from
 320         gas/config/tc-sparc.c.
 321         (HWS_V9): Likewise.
 322         (HWS_VA): Likewise.
 323         (HWS_VB): Likewise.
 324         (HWS_VC): Likewise.
 325         (HWS_VD): Likewise.
 326         (HWS_VE): Likewise.
 327         (HWS_VV): Likewise.
 328         (HWS_VM): Likewise.
 329         (HWS2_VM): Likewise.
 330         (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
 331         existing entries.
 332
 333 2016-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
 334
 335         * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
 336         instructions.
 337
 338 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 339
 340         * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
 341         (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
 342         (aarch64_opcode_table): Add fcmla and fcadd.
 343         (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
 344         * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
 345         * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
 346         * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
 347         * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
 348         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
 349         * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
 350         (operand_general_constraint_met_p): Rotate and index range check.
 351         (aarch64_print_operand): Handle rotate operand.
 352         * aarch64-asm-2.c: Regenerate.
 353         * aarch64-dis-2.c: Likewise.
 354         * aarch64-opc-2.c: Likewise.
 355
 356 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 357
 358         * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
 359         * aarch64-asm-2.c: Regenerate.
 360         * aarch64-dis-2.c: Regenerate.
 361         * aarch64-opc-2.c: Regenerate.
 362
 363 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 364
 365         * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
 366         (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
 367         * aarch64-asm-2.c: Regenerate.
 368         * aarch64-dis-2.c: Regenerate.
 369         * aarch64-opc-2.c: Regenerate.
 370
 371 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 372
 373         * aarch64-tbl.h (QL_X1NIL): New.
 374         (arch64_opcode_table): Add ldraa, ldrab.
 375         (AARCH64_OPERANDS): Add "ADDR_SIMM10".
 376         * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
 377         * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
 378         * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
 379         * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
 380         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
 381         * aarch64-opc.c (fields): Add data for FLD_S_simm10.
 382         (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
 383         (aarch64_print_operand): Likewise.
 384         * aarch64-asm-2.c: Regenerate.
 385         * aarch64-dis-2.c: Regenerate.
 386         * aarch64-opc-2.c: Regenerate.
 387
 388 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 389
 390         * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
 391         brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
 392         * aarch64-asm-2.c: Regenerate.
 393         * aarch64-dis-2.c: Regenerate.
 394         * aarch64-opc-2.c: Regenerate.
 395
 396 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 397
 398         * aarch64-tbl.h (arch64_opcode_table): Add pacga.
 399         (AARCH64_OPERANDS): Add Rm_SP.
 400         * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
 401         * aarch64-asm-2.c: Regenerate.
 402         * aarch64-dis-2.c: Regenerate.
 403         * aarch64-opc-2.c: Regenerate.
 404
 405 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 406
 407         * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
 408         autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
 409         autdzb, xpaci, xpacd.
 410         * aarch64-asm-2.c: Regenerate.
 411         * aarch64-dis-2.c: Regenerate.
 412         * aarch64-opc-2.c: Regenerate.
 413
 414 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 415
 416         * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
 417         apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
 418         apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
 419         (aarch64_sys_reg_supported_p): Add feature test for new registers.
 420
 421 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 422
 423         * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
 424         (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
 425         autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
 426         autibsp.
 427         * aarch64-asm-2.c: Regenerate.
 428         * aarch64-dis-2.c: Regenerate.
 429
 430 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 431
 432         * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
 433
 434 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 435
 436         PR binutils/20799
 437         * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
 438         * i386-dis.c (EdqwS): Removed.
 439         (dqw_swap_mode): Likewise.
 440         (intel_operand_size): Don't check dqw_swap_mode.
 441         (OP_E_register): Likewise.
 442         (OP_E_memory): Likewise.
 443         (OP_G): Likewise.
 444         (OP_EX): Likewise.
 445         * i386-opc.tbl: Remove "S" from EVEX vpextrw.
 446         * i386-tbl.h: Regerated.
 447
 448 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 449
 450         * i386-opc.tbl: Merge AVX512F vmovq.
 451         * i386-tbl.h: Regerated.
 452
 453 2016-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 454
 455         PR binutils/20701
 456         * i386-dis.c (THREE_BYTE_0F7A): Removed.
 457         (dis386_twobyte): Don't use THREE_BYTE_0F7A.
 458         (three_byte_table): Remove THREE_BYTE_0F7A.
 459
 460 2016-11-07  H.J. Lu  <hongjiu.lu@intel.com>
 461
 462         PR binutils/20775
 463         * i386-dis.c (FGRPd9_2): Replace 0 with 1.
 464         (FGRPd9_4): Replace 1 with 2.
 465         (FGRPd9_5): Replace 2 with 3.
 466         (FGRPd9_6): Replace 3 with 4.
 467         (FGRPd9_7): Replace 4 with 5.
 468         (FGRPda_5): Replace 5 with 6.
 469         (FGRPdb_4): Replace 6 with 7.
 470         (FGRPde_3): Replace 7 with 8.
 471         (FGRPdf_4): Replace 8 with 9.
 472         (fgrps): Add an entry for Bad_Opcode.
 473
 474 2016-11-04  Andrew Burgess  <andrew.burgess@embecosm.com>
 475
 476         * arc-opc.c (arc_flag_operands): Add F_DI14.
 477         (arc_flag_classes): Add C_DI14.
 478         * arc-nps400-tbl.h: Add new exc instructions.
 479
 480 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 481
 482         * arc-dis.c (arc_insn_length): Return length 8 for instructions with
 483         major opcode 0xa.
 484         * arc-nps-400-tbl.h: Add dcmac instruction.
 485         * arc-opc.c (arc_operands): Added operands for dcmac instruction.
 486         (insert_nps_rbdouble_64): Added.
 487         (extract_nps_rbdouble_64): Added.
 488         (insert_nps_proto_size): Added.
 489         (extract_nps_proto_size): Added.
 490
 491 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 492
 493         * arc-dis.c (struct arc_operand_iterator): Remove all fields
 494         relating to long instruction processing, add new limm field.
 495         (OPCODE): Rename to...
 496         (OPCODE_32BIT_INSN): ...this.
 497         (OPCODE_AC): Delete.
 498         (skip_this_opcode): Handle different instruction lengths, update
 499         macro name.
 500         (special_flag_p): Update parameter type.
 501         (find_format_from_table): Update for more instruction lengths.
 502         (find_format_long_instructions): Delete.
 503         (find_format): Update for more instruction lengths.
 504         (arc_insn_length): Likewise.
 505         (extract_operand_value): Update for more instruction lengths.
 506         (operand_iterator_next): Remove code relating to long
 507         instructions.
 508         (arc_opcode_to_insn_type): New function.
 509         (print_insn_arc):Update for more instructions lengths.
 510         * arc-ext.c (extInstruction_t): Change argument type.
 511         * arc-ext.h (extInstruction_t): Change argument type.
 512         * arc-fxi.h: Change type unsigned to unsigned long long
 513         extensively throughout.
 514         * arc-nps400-tbl.h: Add long instructions taken from
 515         arc_long_opcodes table in arc-opc.c.
 516         * arc-opc.c: Update parameter types on insert/extract handlers.
 517         (arc_long_opcodes): Delete.
 518         (arc_num_long_opcodes): Delete.
 519         (arc_opcode_len): Update for more instruction lengths.
 520
 521 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 522
 523         * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
 524
 525 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 526
 527         * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
 528         with arc_opcode_len.
 529         (find_format_long_instructions): Likewise.
 530         * arc-opc.c (arc_opcode_len): New function.
 531
 532 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 533
 534         * arc-nps400-tbl.h: Fix some instruction masks.
 535
 536 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 537
 538         * i386-dis.c (REG_82): Removed.
 539         (X86_64_82_REG_0): Likewise.
 540         (X86_64_82_REG_1): Likewise.
 541         (X86_64_82_REG_2): Likewise.
 542         (X86_64_82_REG_3): Likewise.
 543         (X86_64_82_REG_4): Likewise.
 544         (X86_64_82_REG_5): Likewise.
 545         (X86_64_82_REG_6): Likewise.
 546         (X86_64_82_REG_7): Likewise.
 547         (X86_64_82): New.
 548         (dis386): Use X86_64_82 instead of REG_82.
 549         (reg_table): Remove REG_82.
 550         (x86_64_table): Add X86_64_82.  Remove X86_64_82_REG_0,
 551         X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
 552         X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
 553         X86_64_82_REG_7.
 554
 555 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 556
 557         PR binutils/20754
 558         * i386-dis.c (REG_82): New.
 559         (X86_64_82_REG_0): Likewise.
 560         (X86_64_82_REG_1): Likewise.
 561         (X86_64_82_REG_2): Likewise.
 562         (X86_64_82_REG_3): Likewise.
 563         (X86_64_82_REG_4): Likewise.
 564         (X86_64_82_REG_5): Likewise.
 565         (X86_64_82_REG_6): Likewise.
 566         (X86_64_82_REG_7): Likewise.
 567         (dis386): Use REG_82.
 568         (reg_table): Add REG_82.
 569         (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
 570         X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
 571         X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
 572
 573 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 574
 575         * i386-dis.c (REG_82): Renamed to ...
 576         (REG_83): This.
 577         (dis386): Updated.
 578         (reg_table): Likewise.
 579
 580 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 581
 582         * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
 583         * i386-dis-evex.h (evex_table): Updated.
 584         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
 585         CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 586         (cpu_flags): Add CpuAVX512_4VNNIW.
 587         * i386-opc.h (enum): (AVX512_4VNNIW): New.
 588         (i386_cpu_flags): Add cpuavx512_4vnniw.
 589         * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
 590         * i386-init.h: Regenerate.
 591         * i386-tbl.h: Ditto.
 592
 593 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 594
 595         * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
 596         PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
 597         * i386-dis-evex.h (evex_table): Updated.
 598         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
 599         CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 600         (cpu_flags): Add CpuAVX512_4FMAPS.
 601         (opcode_modifiers): Add ImplicitQuadGroup modifier.
 602         * i386-opc.h (AVX512_4FMAP): New.
 603         (i386_cpu_flags): Add cpuavx512_4fmaps.
 604         (ImplicitQuadGroup): New.
 605         (i386_opcode_modifier): Add implicitquadgroup.
 606         * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
 607         * i386-init.h: Regenerate.
 608         * i386-tbl.h: Ditto.
 609
 610 2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
 611             Andrew Waterman <andrew@sifive.com>
 612
 613         Add support for RISC-V architecture.
 614         * configure.ac: Add entry for bfd_riscv_arch.
 615         * configure: Regenerate.
 616         * disassemble.c (disassembler): Add support for riscv.
 617         (disassembler_usage): Likewise.
 618         * riscv-dis.c: New file.
 619         * riscv-opc.c: New file.
 620
 621 2016-10-21  H.J. Lu  <hongjiu.lu@intel.com>
 622
 623         * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
 624         (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
 625         (rm_table): Update the RM_0FAE_REG_7 entry.
 626         * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
 627         (cpu_flags): Remove CpuPCOMMIT.
 628         * i386-opc.h (CpuPCOMMIT): Removed.
 629         (i386_cpu_flags): Remove cpupcommit.
 630         * i386-opc.tbl: Remove pcommit.
 631         * i386-init.h: Regenerated.
 632         * i386-tbl.h: Likewise.
 633
 634 2016-10-20  H.J. Lu  <hongjiu.lu@intel.com>
 635
 636         PR binutis/20705
 637         * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
 638         the highest bit in VEX.vvvv for the 3-byte VEX prefix in
 639         32-bit mode.  Don't check vex.register_specifier in 32-bit
 640         mode.
 641         (OP_VEX): Check for invalid mask registers.
 642
 643 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 644
 645         PR binutis/20699
 646         * i386-dis.c (OP_E_memory): Check addr32flag in stead of
 647         sizeflag.
 648
 649 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 650
 651         PR binutis/20704
 652         * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
 653
 654 2016-10-18  Maciej W. Rozycki  <macro@imgtec.com>
 655
 656         * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
 657         local variable to `index_regno'.
 658
 659 2016-10-17  Cupertino Miranda  <cmiranda@synopsys.com>
 660
 661         * arc-tbl.h: Removed any "inv.+" instructions from the table.
 662
 663 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
 664
 665         * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
 666         usage on ISA basis.
 667
 668 2016-10-11  Jiong Wang  <jiong.wang@arm.com>
 669
 670         PR target/20666
 671         * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
 672
 673 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
 674
 675         PR target/20667
 676         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
 677         available.
 678
 679 2016-10-07  Alan Modra  <amodra@gmail.com>
 680
 681         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
 682
 683 2016-10-06  Alan Modra  <amodra@gmail.com>
 684
 685         * aarch64-opc.c: Spell fall through comments consistently.
 686         * i386-dis.c: Likewise.
 687         * aarch64-dis.c: Add missing fall through comments.
 688         * aarch64-opc.c: Likewise.
 689         * arc-dis.c: Likewise.
 690         * arm-dis.c: Likewise.
 691         * i386-dis.c: Likewise.
 692         * m68k-dis.c: Likewise.
 693         * mep-asm.c: Likewise.
 694         * ns32k-dis.c: Likewise.
 695         * sh-dis.c: Likewise.
 696         * tic4x-dis.c: Likewise.
 697         * tic6x-dis.c: Likewise.
 698         * vax-dis.c: Likewise.
 699
 700 2016-10-06  Alan Modra  <amodra@gmail.com>
 701
 702         * arc-ext.c (create_map): Add missing break.
 703         * msp430-decode.opc (encode_as): Likewise.
 704         * msp430-decode.c: Regenerate.
 705
 706 2016-10-06  Alan Modra  <amodra@gmail.com>
 707
 708         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
 709         * crx-dis.c (print_insn_crx): Likewise.
 710
 711 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 712
 713         PR binutils/20657
 714         * i386-dis.c (putop): Don't assign alt twice.
 715
 716 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
 717
 718         PR target/20553
 719         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
 720
 721 2016-09-29  Alan Modra  <amodra@gmail.com>
 722
 723         * ppc-opc.c (L): Make compulsory.
 724         (LOPT): New, optional form of L.
 725         (HTM_R): Define as LOPT.
 726         (L0, L1): Delete.
 727         (L32OPT): New, optional for 32-bit L.
 728         (L2OPT): New, 2-bit L for dcbf.
 729         (SVC_LEC): Update.
 730         (L2): Define.
 731         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
 732         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
 733         <dcbf>: Use L2OPT.
 734         <tlbiel, tlbie>: Use LOPT.
 735         <wclr, wclrall>: Use L2.
 736
 737 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
 738
 739         * Makefile.in: Regenerate.
 740         * configure: Likewise.
 741
 742 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 743
 744         * arc-ext-tbl.h (EXTINSN2OPF): Define.
 745         (EXTINSN2OP): Use EXTINSN2OPF.
 746         (bspeekm, bspop, modapp): New extension instructions.
 747         * arc-opc.c (F_DNZ_ND): Define.
 748         (F_DNZ_D): Likewise.
 749         (F_SIZEB1): Changed.
 750         (C_DNZ_D): Define.
 751         (C_HARD): Changed.
 752         * arc-tbl.h (dbnz): New instruction.
 753         (prealloc): Allow it for ARC EM.
 754         (xbfu): Likewise.
 755
 756 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 757
 758         * aarch64-opc.c (print_immediate_offset_address): Print spaces
 759         after commas in addresses.
 760         (aarch64_print_operand): Likewise.
 761
 762 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 763
 764         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
 765         rather than "should be" or "expected to be" in error messages.
 766
 767 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 768
 769         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
 770         (print_mnemonic_name): ...here.
 771         (print_comment): New function.
 772         (print_aarch64_insn): Call it.
 773         * aarch64-opc.c (aarch64_conds): Add SVE names.
 774         (aarch64_print_operand): Print alternative condition names in
 775         a comment.
 776
 777 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 778
 779         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 780         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 781         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 782         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 783         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 784         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 785         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 786         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 787         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 788         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 789         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 790         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 791         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 792         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 793         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 794         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 795         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 796         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 797         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 798         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 799         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 800         (aarch64_feature_sve): New variable.
 801         (SVE): New macro.
 802         (_SVE_INSN): Likewise.
 803         (aarch64_opcode_table): Add SVE instructions.
 804         * aarch64-opc.h (extract_fields): Declare.
 805         * aarch64-opc-2.c: Regenerate.
 806         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 807         * aarch64-asm-2.c: Regenerate.
 808         * aarch64-dis.c (extract_fields): Make global.
 809         (do_misc_decoding): Handle the new SVE aarch64_ops.
 810         * aarch64-dis-2.c: Regenerate.
 811
 812 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 813
 814         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 815         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 816         aarch64_field_kinds.
 817         * aarch64-opc.c (fields): Add corresponding entries.
 818         * aarch64-asm.c (aarch64_get_variant): New function.
 819         (aarch64_encode_variant_using_iclass): Likewise.
 820         (aarch64_opcode_encode): Call it.
 821         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 822         (aarch64_opcode_decode): Call it.
 823
 824 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 825
 826         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 827         and FP register operands.
 828         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 829         (FLD_SVE_Vn): New aarch64_field_kinds.
 830         * aarch64-opc.c (fields): Add corresponding entries.
 831         (aarch64_print_operand): Handle the new SVE core and FP register
 832         operands.
 833         * aarch64-opc-2.c: Regenerate.
 834         * aarch64-asm-2.c: Likewise.
 835         * aarch64-dis-2.c: Likewise.
 836
 837 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 838
 839         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 840         immediate operands.
 841         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 842         * aarch64-opc.c (fields): Add corresponding entry.
 843         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 844         operands.
 845         (aarch64_print_operand): Likewise.
 846         * aarch64-opc-2.c: Regenerate.
 847         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 848         (ins_sve_float_zero_one): New inserters.
 849         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 850         (aarch64_ins_sve_float_half_two): Likewise.
 851         (aarch64_ins_sve_float_zero_one): Likewise.
 852         * aarch64-asm-2.c: Regenerate.
 853         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 854         (ext_sve_float_zero_one): New extractors.
 855         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 856         (aarch64_ext_sve_float_half_two): Likewise.
 857         (aarch64_ext_sve_float_zero_one): Likewise.
 858         * aarch64-dis-2.c: Regenerate.
 859
 860 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 861
 862         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 863         integer immediate operands.
 864         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 865         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 866         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 867         * aarch64-opc.c (fields): Add corresponding entries.
 868         (operand_general_constraint_met_p): Handle the new SVE integer
 869         immediate operands.
 870         (aarch64_print_operand): Likewise.
 871         (aarch64_sve_dupm_mov_immediate_p): New function.
 872         * aarch64-opc-2.c: Regenerate.
 873         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 874         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 875         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 876         (aarch64_ins_limm): ...here.
 877         (aarch64_ins_inv_limm): New function.
 878         (aarch64_ins_sve_aimm): Likewise.
 879         (aarch64_ins_sve_asimm): Likewise.
 880         (aarch64_ins_sve_limm_mov): Likewise.
 881         (aarch64_ins_sve_shlimm): Likewise.
 882         (aarch64_ins_sve_shrimm): Likewise.
 883         * aarch64-asm-2.c: Regenerate.
 884         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 885         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 886         * aarch64-dis.c (decode_limm): New function, split out from...
 887         (aarch64_ext_limm): ...here.
 888         (aarch64_ext_inv_limm): New function.
 889         (decode_sve_aimm): Likewise.
 890         (aarch64_ext_sve_aimm): Likewise.
 891         (aarch64_ext_sve_asimm): Likewise.
 892         (aarch64_ext_sve_limm_mov): Likewise.
 893         (aarch64_top_bit): Likewise.
 894         (aarch64_ext_sve_shlimm): Likewise.
 895         (aarch64_ext_sve_shrimm): Likewise.
 896         * aarch64-dis-2.c: Regenerate.
 897
 898 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 899
 900         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 901         operands.
 902         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 903         the AARCH64_MOD_MUL_VL entry.
 904         (value_aligned_p): Cope with non-power-of-two alignments.
 905         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 906         (print_immediate_offset_address): Likewise.
 907         (aarch64_print_operand): Likewise.
 908         * aarch64-opc-2.c: Regenerate.
 909         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 910         (ins_sve_addr_ri_s9xvl): New inserters.
 911         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 912         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 913         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 914         * aarch64-asm-2.c: Regenerate.
 915         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 916         (ext_sve_addr_ri_s9xvl): New extractors.
 917         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 918         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 919         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 920         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 921         * aarch64-dis-2.c: Regenerate.
 922
 923 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 924
 925         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 926         address operands.
 927         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 928         (FLD_SVE_xs_22): New aarch64_field_kinds.
 929         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 930         (get_operand_specific_data): New function.
 931         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 932         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 933         (operand_general_constraint_met_p): Handle the new SVE address
 934         operands.
 935         (sve_reg): New array.
 936         (get_addr_sve_reg_name): New function.
 937         (aarch64_print_operand): Handle the new SVE address operands.
 938         * aarch64-opc-2.c: Regenerate.
 939         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 940         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 941         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 942         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 943         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 944         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 945         (aarch64_ins_sve_addr_zi_u5): Likewise.
 946         (aarch64_ins_sve_addr_zz): Likewise.
 947         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 948         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 949         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 950         * aarch64-asm-2.c: Regenerate.
 951         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 952         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 953         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 954         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 955         (aarch64_ext_sve_addr_ri_u6): Likewise.
 956         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 957         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 958         (aarch64_ext_sve_addr_zi_u5): Likewise.
 959         (aarch64_ext_sve_addr_zz): Likewise.
 960         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 961         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 962         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 963         * aarch64-dis-2.c: Regenerate.
 964
 965 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 966
 967         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 968         AARCH64_OPND_SVE_PATTERN_SCALED.
 969         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 970         * aarch64-opc.c (fields): Add a corresponding entry.
 971         (set_multiplier_out_of_range_error): New function.
 972         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 973         (operand_general_constraint_met_p): Handle
 974         AARCH64_OPND_SVE_PATTERN_SCALED.
 975         (print_register_offset_address): Use PRIi64 to print the
 976         shift amount.
 977         (aarch64_print_operand): Likewise.  Handle
 978         AARCH64_OPND_SVE_PATTERN_SCALED.
 979         * aarch64-opc-2.c: Regenerate.
 980         * aarch64-asm.h (ins_sve_scale): New inserter.
 981         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 982         * aarch64-asm-2.c: Regenerate.
 983         * aarch64-dis.h (ext_sve_scale): New inserter.
 984         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 985         * aarch64-dis-2.c: Regenerate.
 986
 987 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 988
 989         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 990         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 991         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 992         (FLD_SVE_prfop): Likewise.
 993         * aarch64-opc.c: Include libiberty.h.
 994         (aarch64_sve_pattern_array): New variable.
 995         (aarch64_sve_prfop_array): Likewise.
 996         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 997         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 998         AARCH64_OPND_SVE_PRFOP.
 999         * aarch64-asm-2.c: Regenerate.
1000         * aarch64-dis-2.c: Likewise.
1001         * aarch64-opc-2.c: Likewise.
1002
1003 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1004
1005         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
1006         AARCH64_OPND_QLF_P_[ZM].
1007         (aarch64_print_operand): Print /z and /m where appropriate.
1008
1009 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1010
1011         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
1012         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
1013         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
1014         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
1015         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
1016         * aarch64-opc.c (fields): Add corresponding entries here.
1017         (operand_general_constraint_met_p): Check that SVE register lists
1018         have the correct length.  Check the ranges of SVE index registers.
1019         Check for cases where p8-p15 are used in 3-bit predicate fields.
1020         (aarch64_print_operand): Handle the new SVE operands.
1021         * aarch64-opc-2.c: Regenerate.
1022         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
1023         * aarch64-asm.c (aarch64_ins_sve_index): New function.
1024         (aarch64_ins_sve_reglist): Likewise.
1025         * aarch64-asm-2.c: Regenerate.
1026         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
1027         * aarch64-dis.c (aarch64_ext_sve_index): New function.
1028         (aarch64_ext_sve_reglist): Likewise.
1029         * aarch64-dis-2.c: Regenerate.
1030
1031 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1032
1033         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
1034         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
1035         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
1036         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
1037         tied operands.
1038
1039 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1040
1041         * aarch64-opc.c (get_offset_int_reg_name): New function.
1042         (print_immediate_offset_address): Likewise.
1043         (print_register_offset_address): Take the base and offset
1044         registers as parameters.
1045         (aarch64_print_operand): Update caller accordingly.  Use
1046         print_immediate_offset_address.
1047
1048 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1049
1050         * aarch64-opc.c (BANK): New macro.
1051         (R32, R64): Take a register number as argument
1052         (int_reg): Use BANK.
1053
1054 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1055
1056         * aarch64-opc.c (print_register_list): Add a prefix parameter.
1057         (aarch64_print_operand): Update accordingly.
1058
1059 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1060
1061         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
1062         for FPIMM.
1063         * aarch64-asm.h (ins_fpimm): New inserter.
1064         * aarch64-asm.c (aarch64_ins_fpimm): New function.
1065         * aarch64-asm-2.c: Regenerate.
1066         * aarch64-dis.h (ext_fpimm): New extractor.
1067         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
1068         (aarch64_ext_fpimm): New function.
1069         * aarch64-dis-2.c: Regenerate.
1070
1071 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1072
1073         * aarch64-asm.c: Include libiberty.h.
1074         (insert_fields): New function.
1075         (aarch64_ins_imm): Use it.
1076         * aarch64-dis.c (extract_fields): New function.
1077         (aarch64_ext_imm): Use it.
1078
1079 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1080
1081         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
1082         with an esize parameter.
1083         (operand_general_constraint_met_p): Update accordingly.
1084         Fix misindented code.
1085         * aarch64-asm.c (aarch64_ins_limm): Update call to
1086         aarch64_logical_immediate_p.
1087
1088 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1089
1090         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
1091
1092 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
1093
1094         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
1095
1096 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
1097
1098         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
1099
1100 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
1101
1102         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
1103         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
1104         xor3>: Delete mnemonics.
1105         <cp_abort>: Rename mnemonic from ...
1106         <cpabort>: ...to this.
1107         <setb>: Change to a X form instruction.
1108         <sync>: Change to 1 operand form.
1109         <copy>: Delete mnemonic.
1110         <copy_first>: Rename mnemonic from ...
1111         <copy>: ...to this.
1112         <paste, paste.>: Delete mnemonics.
1113         <paste_last>: Rename mnemonic from ...
1114         <paste.>: ...to this.
1115
1116 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
1117
1118         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
1119
1120 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1121
1122         * s390-mkopc.c (main): Support alternate arch strings.
1123
1124 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
1125
1126         * s390-opc.txt: Fix kmctr instruction type.
1127
1128 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
1129
1130         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
1131         * i386-init.h: Regenerated.
1132
1133 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
1134
1135         * opcodes/arc-dis.c (print_insn_arc): Changed.
1136
1137 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
1138
1139         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
1140         camellia_fl.
1141
1142 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1143
1144         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
1145         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
1146         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
1147
1148 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
1149
1150         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
1151         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
1152         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
1153         PREFIX_MOD_3_0FAE_REG_4.
1154         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
1155         PREFIX_MOD_3_0FAE_REG_4.
1156         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
1157         (cpu_flags): Add CpuPTWRITE.
1158         * i386-opc.h (CpuPTWRITE): New.
1159         (i386_cpu_flags): Add cpuptwrite.
1160         * i386-opc.tbl: Add ptwrite instruction.
1161         * i386-init.h: Regenerated.
1162         * i386-tbl.h: Likewise.
1163
1164 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
1165
1166         * arc-dis.h: Wrap around in extern "C".
1167
1168 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
1169
1170         * aarch64-tbl.h (V8_2_INSN): New macro.
1171         (aarch64_opcode_table): Use it.
1172
1173 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
1174
1175         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
1176         CORE_INSN, __FP_INSN and SIMD_INSN.
1177
1178 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
1179
1180         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
1181         (aarch64_opcode_table): Update uses accordingly.
1182
1183 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
1184         Kwok Cheung Yeung  <kcy@codesourcery.com>
1185
1186         opcodes/
1187         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
1188         'e_cmplwi' to 'e_cmpli' instead.
1189         (OPVUPRT, OPVUPRT_MASK): Define.
1190         (powerpc_opcodes): Add E200Z4 insns.
1191         (vle_opcodes): Add context save/restore insns.
1192
1193 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
1194
1195         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
1196         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
1197         "j".
1198
1199 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
1200
1201         * arc-nps400-tbl.h: Change block comments to GNU format.
1202         * arc-dis.c: Add new globals addrtypenames,
1203         addrtypenames_max, and addtypeunknown.
1204         (get_addrtype): New function.
1205         (print_insn_arc): Print colons and address types when
1206         required.
1207         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1208         define insert and extract functions for all address types.
1209         (arc_operands): Add operands for colon and all address
1210         types.
1211         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1212         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1213         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1214         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1215         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1216         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1217
1218 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
1219
1220         * configure: Regenerated.
1221
1222 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
1223
1224         * arc-dis.c (skipclass): New structure.
1225         (decodelist): New variable.
1226         (is_compatible_p): New function.
1227         (new_element): Likewise.
1228         (skip_class_p): Likewise.
1229         (find_format_from_table): Use skip_class_p function.
1230         (find_format): Decode first the extension instructions.
1231         (print_insn_arc): Select either ARCEM or ARCHS based on elf
1232         e_flags.
1233         (parse_option): New function.
1234         (parse_disassembler_options): Likewise.
1235         (print_arc_disassembler_options): Likewise.
1236         (print_insn_arc): Use parse_disassembler_options function.  Proper
1237         select ARCv2 cpu variant.
1238         * disassemble.c (disassembler_usage): Add ARC disassembler
1239         options.
1240
1241 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
1242
1243         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1244         annotation from the "nal" entry and reorder it beyond "bltzal".
1245
1246 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
1247
1248         * sparc-opc.c (ldtxa): New macro.
1249         (sparc_opcodes): Use the macro defined above to add entries for
1250         the LDTXA instructions.
1251         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1252         instruction.
1253
1254 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
1255
1256         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1257         and "jmpc".
1258
1259 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1260
1261         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1262         (movzb): Adjust to cover all permitted suffixes.
1263         (movzw): New.
1264         * i386-tbl.h: Re-generate.
1265
1266 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1267
1268         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1269         (lgdt): Remove Tbyte from non-64-bit variant.
1270         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1271         xsaves64, xsavec64): Remove Disp16.
1272         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1273         Remove Disp32S from non-64-bit variants. Remove Disp16 from
1274         64-bit variants.
1275         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1276         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1277         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1278         64-bit variants.
1279         * i386-tbl.h: Re-generate.
1280
1281 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1282
1283         * i386-opc.tbl (xlat): Remove RepPrefixOk.
1284         * i386-tbl.h: Re-generate.
1285
1286 2016-06-30  Yao Qi  <yao.qi@linaro.org>
1287
1288         * arm-dis.c (print_insn): Fix typo in comment.
1289
1290 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
1291
1292         * aarch64-opc.c (operand_general_constraint_met_p): Check the
1293         range of ldst_elemlist operands.
1294         (print_register_list): Use PRIi64 to print the index.
1295         (aarch64_print_operand): Likewise.
1296
1297 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1298
1299         * mcore-opc.h: Remove sentinal.
1300         * mcore-dis.c (print_insn_mcore): Adjust.
1301
1302 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
1303
1304         * arc-opc.c: Correct description of availability of NPS400
1305         features.
1306
1307 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
1308
1309         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1310         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1311         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1312         xor3>: New mnemonics.
1313         <setb>: Change to a VX form instruction.
1314         (insert_sh6): Add support for rldixor.
1315         (extract_sh6): Likewise.
1316
1317 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1318
1319         * arc-ext.h: Wrap in extern C.
1320
1321 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
1322
1323         * arc-dis.c (arc_insn_length): Add comment on instruction length.
1324         Use same method for determining instruction length on ARC700 and
1325         NPS-400.
1326         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1327         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1328         with the NPS400 subclass.
1329         * arc-opc.c: Likewise.
1330
1331 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1332
1333         * sparc-opc.c (rdasr): New macro.
1334         (wrasr): Likewise.
1335         (rdpr): Likewise.
1336         (wrpr): Likewise.
1337         (rdhpr): Likewise.
1338         (wrhpr): Likewise.
1339         (sparc_opcodes): Use the macros above to fix and expand the
1340         definition of read/write instructions from/to
1341         asr/privileged/hyperprivileged instructions.
1342         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1343         %hva_mask_nz.  Prefer softint_set and softint_clear over
1344         set_softint and clear_softint.
1345         (print_insn_sparc): Support %ver in Rd.
1346
1347 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1348
1349         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1350         architecture according to the hardware capabilities they require.
1351
1352 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1353
1354         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1355         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1356         bfd_mach_sparc_v9{c,d,e,v,m}.
1357         * sparc-opc.c (MASK_V9C): Define.
1358         (MASK_V9D): Likewise.
1359         (MASK_V9E): Likewise.
1360         (MASK_V9V): Likewise.
1361         (MASK_V9M): Likewise.
1362         (v6): Add MASK_V9{C,D,E,V,M}.
1363         (v6notlet): Likewise.
1364         (v7): Likewise.
1365         (v8): Likewise.
1366         (v9): Likewise.
1367         (v9andleon): Likewise.
1368         (v9a): Likewise.
1369         (v9b): Likewise.
1370         (v9c): Define.
1371         (v9d): Likewise.
1372         (v9e): Likewise.
1373         (v9v): Likewise.
1374         (v9m): Likewise.
1375         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1376
1377 2016-06-15  Nick Clifton  <nickc@redhat.com>
1378
1379         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1380         constants to match expected behaviour.
1381         (nds32_parse_opcode): Likewise.  Also for whitespace.
1382
1383 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
1384
1385         * arc-opc.c (extract_rhv1): Extract value from insn.
1386
1387 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1388
1389         * arc-nps400-tbl.h: Add ldbit instruction.
1390         * arc-opc.c: Add flag classes required for ldbit.
1391
1392 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1393
1394         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1395         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1396         support the above instructions.
1397
1398 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1399
1400         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1401         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1402         csma, cbba, zncv, and hofs.
1403         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1404         support the above instructions.
1405
1406 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1407
1408         * arc-nps400-tbl.h: Add andab and orab instructions.
1409
1410 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1411
1412         * arc-nps400-tbl.h: Add addl-like instructions.
1413
1414 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1415
1416         * arc-nps400-tbl.h: Add mxb and imxb instructions.
1417
1418 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1419
1420         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1421         instructions.
1422
1423 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1424
1425         * s390-dis.c (option_use_insn_len_bits_p): New file scope
1426         variable.
1427         (init_disasm): Handle new command line option "insnlength".
1428         (print_s390_disassembler_options): Mention new option in help
1429         output.
1430         (print_insn_s390): Use the encoded insn length when dumping
1431         unknown instructions.
1432
1433 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
1434
1435         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1436          to the address and set as symbol address for LDS/ STS immediate operands.
1437
1438 2016-06-07  Alan Modra  <amodra@gmail.com>
1439
1440         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
1441         cpu for "vle" to e500.
1442         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1443         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1444         (PPCNONE): Delete, substitute throughout.
1445         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
1446         except for major opcode 4 and 31.
1447         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1448
1449 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
1450
1451         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1452         ARM_EXT_RAS in relevant entries.
1453
1454 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
1455
1456         PR binutils/20196
1457         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1458         opcodes for E6500.
1459
1460 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
1461
1462         PR binutis/18386
1463         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1464         (indir_v_mode): New.
1465         Add comments for '&'.
1466         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1467         (putop): Handle '&'.
1468         (intel_operand_size): Handle indir_v_mode.
1469         (OP_E_register): Likewise.
1470         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
1471         64-bit indirect call/jmp for AMD64.
1472         * i386-tbl.h: Regenerated
1473
1474 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1475
1476         * arc-dis.c (struct arc_operand_iterator): New structure.
1477         (find_format_from_table): All the old content from find_format,
1478         with some minor adjustments, and parameter renaming.
1479         (find_format_long_instructions): New function.
1480         (find_format): Rewritten.
1481         (arc_insn_length): Add LSB parameter.
1482         (extract_operand_value): New function.
1483         (operand_iterator_next): New function.
1484         (print_insn_arc): Use new functions to find opcode, and iterator
1485         over operands.
1486         * arc-opc.c (insert_nps_3bit_dst_short): New function.
1487         (extract_nps_3bit_dst_short): New function.
1488         (insert_nps_3bit_src2_short): New function.
1489         (extract_nps_3bit_src2_short): New function.
1490         (insert_nps_bitop1_size): New function.
1491         (extract_nps_bitop1_size): New function.
1492         (insert_nps_bitop2_size): New function.
1493         (extract_nps_bitop2_size): New function.
1494         (insert_nps_bitop_mod4_msb): New function.
1495         (extract_nps_bitop_mod4_msb): New function.
1496         (insert_nps_bitop_mod4_lsb): New function.
1497         (extract_nps_bitop_mod4_lsb): New function.
1498         (insert_nps_bitop_dst_pos3_pos4): New function.
1499         (extract_nps_bitop_dst_pos3_pos4): New function.
1500         (insert_nps_bitop_ins_ext): New function.
1501         (extract_nps_bitop_ins_ext): New function.
1502         (arc_operands): Add new operands.
1503         (arc_long_opcodes): New global array.
1504         (arc_num_long_opcodes): New global.
1505         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1506
1507 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1508
1509         * nds32-asm.h: Add extern "C".
1510         * sh-opc.h: Likewise.
1511
1512 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
1513
1514         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1515         0,b,limm to the rflt instruction.
1516
1517 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1518
1519         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1520         constant.
1521
1522 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
1523
1524         PR gas/20145
1525         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1526         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1527         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1528         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1529         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1530         * i386-init.h: Regenerated.
1531
1532 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1533
1534         PR gas/20145
1535         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
1536         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
1537         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1538         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1539         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
1540         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1541         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1542         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
1543         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1544         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1545         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
1546         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
1547         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
1548         CpuRegMask for AVX512.
1549         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1550         and CpuRegMask.
1551         (set_bitfield_from_cpu_flag_init): New function.
1552         (set_bitfield): Remove const on f.  Call
1553         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1554         * i386-opc.h (CpuRegMMX): New.
1555         (CpuRegXMM): Likewise.
1556         (CpuRegYMM): Likewise.
1557         (CpuRegZMM): Likewise.
1558         (CpuRegMask): Likewise.
1559         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1560         and cpuregmask.
1561         * i386-init.h: Regenerated.
1562         * i386-tbl.h: Likewise.
1563
1564 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1565
1566         PR gas/20154
1567         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1568         (opcode_modifiers): Add AMD64 and Intel64.
1569         (main): Properly verify CpuMax.
1570         * i386-opc.h (CpuAMD64): Removed.
1571         (CpuIntel64): Likewise.
1572         (CpuMax): Set to CpuNo64.
1573         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1574         (AMD64): New.
1575         (Intel64): Likewise.
1576         (i386_opcode_modifier): Add amd64 and intel64.
1577         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1578         on call and jmp.
1579         * i386-init.h: Regenerated.
1580         * i386-tbl.h: Likewise.
1581
1582 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1583
1584         PR gas/20154
1585         * i386-gen.c (main): Fail if CpuMax is incorrect.
1586         * i386-opc.h (CpuMax): Set to CpuIntel64.
1587         * i386-tbl.h: Regenerated.
1588
1589 2016-05-27  Nick Clifton  <nickc@redhat.com>
1590
1591         PR target/20150
1592         * msp430-dis.c (msp430dis_read_two_bytes): New function.
1593         (msp430dis_opcode_unsigned): New function.
1594         (msp430dis_opcode_signed): New function.
1595         (msp430_singleoperand): Use the new opcode reading functions.
1596         Only disassenmble bytes if they were successfully read.
1597         (msp430_doubleoperand): Likewise.
1598         (msp430_branchinstr): Likewise.
1599         (msp430x_callx_instr): Likewise.
1600         (print_insn_msp430): Check that it is safe to read bytes before
1601         attempting disassembly.  Use the new opcode reading functions.
1602
1603 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
1604
1605         * ppc-opc.c (CY): New define.  Document it.
1606         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1607
1608 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1609
1610         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1611         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1612         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
1613         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1614         CPU_ANY_AVX_FLAGS.
1615         * i386-init.h: Regenerated.
1616
1617 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1618
1619         PR gas/20141
1620         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1621         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1622         * i386-init.h: Regenerated.
1623
1624 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1625
1626         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1627         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
1628         * i386-init.h: Regenerated.
1629
1630 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1631
1632         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1633         information.
1634         (print_insn_arc): Set insn_type information.
1635         * arc-opc.c (C_CC): Add F_CLASS_COND.
1636         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1637         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1638         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1639         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1640         (brne, brne_s, jeq_s, jne_s): Likewise.
1641
1642 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1643
1644         * arc-tbl.h (neg): New instruction variant.
1645
1646 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
1647
1648         * arc-dis.c (find_format, find_format, get_auxreg)
1649         (print_insn_arc): Changed.
1650         * arc-ext.h (INSERT_XOP): Likewise.
1651
1652 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1653
1654         * tic54x-dis.c (sprint_mmr): Adjust.
1655         * tic54x-opc.c: Likewise.
1656
1657 2016-05-19  Alan Modra  <amodra@gmail.com>
1658
1659         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1660
1661 2016-05-19  Alan Modra  <amodra@gmail.com>
1662
1663         * ppc-opc.c: Formatting.
1664         (NSISIGNOPT): Define.
1665         (powerpc_opcodes <subis>): Use NSISIGNOPT.
1666
1667 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
1668
1669         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1670         replacing references to `micromips_ase' throughout.
1671         (_print_insn_mips): Don't use file-level microMIPS annotation to
1672         determine the disassembly mode with the symbol table.
1673
1674 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1675
1676         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1677
1678 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1679
1680         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1681         mips64r6.
1682         * mips-opc.c (D34): New macro.
1683         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1684
1685 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1686
1687         * i386-dis.c (prefix_table): Add RDPID instruction.
1688         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1689         (cpu_flags): Add RDPID bitfield.
1690         * i386-opc.h (enum): Add RDPID element.
1691         (i386_cpu_flags): Add RDPID field.
1692         * i386-opc.tbl: Add RDPID instruction.
1693         * i386-init.h: Regenerate.
1694         * i386-tbl.h: Regenerate.
1695
1696 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1697
1698         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1699         branch type of a symbol.
1700         (print_insn): Likewise.
1701
1702 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1703
1704         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1705         Mainline Security Extensions instructions.
1706         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1707         Extensions instructions.
1708         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1709         instructions.
1710         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1711         special registers.
1712
1713 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1714
1715         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1716
1717 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1718
1719         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1720         (arcExtMap_genOpcode): Likewise.
1721         * arc-opc.c (arg_32bit_rc): Define new variable.
1722         (arg_32bit_u6): Likewise.
1723         (arg_32bit_limm): Likewise.
1724
1725 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1726
1727         * aarch64-gen.c (VERIFIER): Define.
1728         * aarch64-opc.c (VERIFIER): Define.
1729         (verify_ldpsw): Use static linkage.
1730         * aarch64-opc.h (verify_ldpsw): Remove.
1731         * aarch64-tbl.h: Use VERIFIER for verifiers.
1732
1733 2016-04-28  Nick Clifton  <nickc@redhat.com>
1734
1735         PR target/19722
1736         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1737         * aarch64-opc.c (verify_ldpsw): New function.
1738         * aarch64-opc.h (verify_ldpsw): New prototype.
1739         * aarch64-tbl.h: Add initialiser for verifier field.
1740         (LDPSW): Set verifier to verify_ldpsw.
1741
1742 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1743
1744         PR binutils/19983
1745         PR binutils/19984
1746         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1747         smaller than address size.
1748
1749 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1750
1751         * alpha-dis.c: Regenerate.
1752         * crx-dis.c: Likewise.
1753         * disassemble.c: Likewise.
1754         * epiphany-opc.c: Likewise.
1755         * fr30-opc.c: Likewise.
1756         * frv-opc.c: Likewise.
1757         * ip2k-opc.c: Likewise.
1758         * iq2000-opc.c: Likewise.
1759         * lm32-opc.c: Likewise.
1760         * lm32-opinst.c: Likewise.
1761         * m32c-opc.c: Likewise.
1762         * m32r-opc.c: Likewise.
1763         * m32r-opinst.c: Likewise.
1764         * mep-opc.c: Likewise.
1765         * mt-opc.c: Likewise.
1766         * or1k-opc.c: Likewise.
1767         * or1k-opinst.c: Likewise.
1768         * tic80-opc.c: Likewise.
1769         * xc16x-opc.c: Likewise.
1770         * xstormy16-opc.c: Likewise.
1771
1772 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1773
1774         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1775         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1776         calcsd, and calcxd instructions.
1777         * arc-opc.c (insert_nps_bitop_size): Delete.
1778         (extract_nps_bitop_size): Delete.
1779         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1780         (extract_nps_qcmp_m3): Define.
1781         (extract_nps_qcmp_m2): Define.
1782         (extract_nps_qcmp_m1): Define.
1783         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1784         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1785         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1786         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1787         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1788         NPS_QCMP_M3.
1789
1790 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1791
1792         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1793
1794 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1795
1796         * Makefile.in: Regenerated with automake 1.11.6.
1797         * aclocal.m4: Likewise.
1798
1799 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1800
1801         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1802         instructions.
1803         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1804         (extract_nps_cmem_uimm16): New function.
1805         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1806
1807 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1808
1809         * arc-dis.c (arc_insn_length): New function.
1810         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1811         (find_format): Change insnLen parameter to unsigned.
1812
1813 2016-04-13  Nick Clifton  <nickc@redhat.com>
1814
1815         PR target/19937
1816         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1817         the LD.B and LD.BU instructions.
1818
1819 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1820
1821         * arc-dis.c (find_format): Check for extension flags.
1822         (print_flags): New function.
1823         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1824         .extAuxRegister.
1825         * arc-ext.c (arcExtMap_coreRegName): Use
1826         LAST_EXTENSION_CORE_REGISTER.
1827         (arcExtMap_coreReadWrite): Likewise.
1828         (dump_ARC_extmap): Update printing.
1829         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1830         (arc_aux_regs): Add cpu field.
1831         * arc-regs.h: Add cpu field, lower case name aux registers.
1832
1833 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1834
1835         * arc-tbl.h: Add rtsc, sleep with no arguments.
1836
1837 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1838
1839         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1840         Initialize.
1841         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1842         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1843         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1844         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1845         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1846         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1847         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1848         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1849         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1850         (arc_opcode arc_opcodes): Null terminate the array.
1851         (arc_num_opcodes): Remove.
1852         * arc-ext.h (INSERT_XOP): Define.
1853         (extInstruction_t): Likewise.
1854         (arcExtMap_instName): Delete.
1855         (arcExtMap_insn): New function.
1856         (arcExtMap_genOpcode): Likewise.
1857         * arc-ext.c (ExtInstruction): Remove.
1858         (create_map): Zero initialize instruction fields.
1859         (arcExtMap_instName): Remove.
1860         (arcExtMap_insn): New function.
1861         (dump_ARC_extmap): More info while debuging.
1862         (arcExtMap_genOpcode): New function.
1863         * arc-dis.c (find_format): New function.
1864         (print_insn_arc): Use find_format.
1865         (arc_get_disassembler): Enable dump_ARC_extmap only when
1866         debugging.
1867
1868 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1869
1870         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1871         instruction bits out.
1872
1873 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1874
1875         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1876         * arc-opc.c (arc_flag_operands): Add new flags.
1877         (arc_flag_classes): Add new classes.
1878
1879 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1880
1881         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1882
1883 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1884
1885         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1886         encode1, rflt, crc16, and crc32 instructions.
1887         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1888         (arc_flag_classes): Add C_NPS_R.
1889         (insert_nps_bitop_size_2b): New function.
1890         (extract_nps_bitop_size_2b): Likewise.
1891         (insert_nps_bitop_uimm8): Likewise.
1892         (extract_nps_bitop_uimm8): Likewise.
1893         (arc_operands): Add new operand entries.
1894
1895 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1896
1897         * arc-regs.h: Add a new subclass field.  Add double assist
1898         accumulator register values.
1899         * arc-tbl.h: Use DPA subclass to mark the double assist
1900         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1901         * arc-opc.c (RSP): Define instead of SP.
1902         (arc_aux_regs): Add the subclass field.
1903
1904 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1905
1906         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1907
1908 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1909
1910         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1911         NPS_R_SRC1.
1912
1913 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1914
1915         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1916         issues.  No functional changes.
1917
1918 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1919
1920         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1921         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1922         (RTT): Remove duplicate.
1923         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1924         (PCT_CONFIG*): Remove.
1925         (D1L, D1H, D2H, D2L): Define.
1926
1927 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1928
1929         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1930
1931 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1932
1933         * arc-tbl.h (invld07): Remove.
1934         * arc-ext-tbl.h: New file.
1935         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1936         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1937
1938 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1939
1940         Fix -Wstack-usage warnings.
1941         * aarch64-dis.c (print_operands): Substitute size.
1942         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1943
1944 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1945
1946         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1947         to get a proper diagnostic when an invalid ASR register is used.
1948
1949 2016-03-22  Nick Clifton  <nickc@redhat.com>
1950
1951         * configure: Regenerate.
1952
1953 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1954
1955         * arc-nps400-tbl.h: New file.
1956         * arc-opc.c: Add top level comment.
1957         (insert_nps_3bit_dst): New function.
1958         (extract_nps_3bit_dst): New function.
1959         (insert_nps_3bit_src2): New function.
1960         (extract_nps_3bit_src2): New function.
1961         (insert_nps_bitop_size): New function.
1962         (extract_nps_bitop_size): New function.
1963         (arc_flag_operands): Add nps400 entries.
1964         (arc_flag_classes): Add nps400 entries.
1965         (arc_operands): Add nps400 entries.
1966         (arc_opcodes): Add nps400 include.
1967
1968 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1969
1970         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1971         the new class enum values.
1972
1973 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1974
1975         * arc-dis.c (print_insn_arc): Handle nps400.
1976
1977 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1978
1979         * arc-opc.c (BASE): Delete.
1980
1981 2016-03-18  Nick Clifton  <nickc@redhat.com>
1982
1983         PR target/19721
1984         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1985         of MOV insn that aliases an ORR insn.
1986
1987 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1988
1989         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1990
1991 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1992
1993         * mcore-opc.h: Add const qualifiers.
1994         * microblaze-opc.h (struct op_code_struct): Likewise.
1995         * sh-opc.h: Likewise.
1996         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1997         (tic4x_print_op): Likewise.
1998
1999 2016-03-02  Alan Modra  <amodra@gmail.com>
2000
2001         * or1k-desc.h: Regenerate.
2002         * fr30-ibld.c: Regenerate.
2003         * rl78-decode.c: Regenerate.
2004
2005 2016-03-01  Nick Clifton  <nickc@redhat.com>
2006
2007         PR target/19747
2008         * rl78-dis.c (print_insn_rl78_common): Fix typo.
2009
2010 2016-02-24  Renlin Li  <renlin.li@arm.com>
2011
2012         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
2013         (print_insn_coprocessor): Support fp16 instructions.
2014
2015 2016-02-24  Renlin Li  <renlin.li@arm.com>
2016
2017         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
2018         vminnm, vrint(mpna).
2019
2020 2016-02-24  Renlin Li  <renlin.li@arm.com>
2021
2022         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
2023         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
2024
2025 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
2026
2027         * i386-dis.c (print_insn): Parenthesize expression to prevent
2028         truncated addresses.
2029         (OP_J): Likewise.
2030
2031 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
2032             Janek van Oirschot  <jvanoirs@synopsys.com>
2033
2034         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
2035         variable.
2036
2037 2016-02-04  Nick Clifton  <nickc@redhat.com>
2038
2039         PR target/19561
2040         * msp430-dis.c (print_insn_msp430): Add a special case for
2041         decoding an RRC instruction with the ZC bit set in the extension
2042         word.
2043
2044 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
2045
2046         * cgen-ibld.in (insert_normal): Rework calculation of shift.
2047         * epiphany-ibld.c: Regenerate.
2048         * fr30-ibld.c: Regenerate.
2049         * frv-ibld.c: Regenerate.
2050         * ip2k-ibld.c: Regenerate.
2051         * iq2000-ibld.c: Regenerate.
2052         * lm32-ibld.c: Regenerate.
2053         * m32c-ibld.c: Regenerate.
2054         * m32r-ibld.c: Regenerate.
2055         * mep-ibld.c: Regenerate.
2056         * mt-ibld.c: Regenerate.
2057         * or1k-ibld.c: Regenerate.
2058         * xc16x-ibld.c: Regenerate.
2059         * xstormy16-ibld.c: Regenerate.
2060
2061 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
2062
2063         * epiphany-dis.c: Regenerated from latest cpu files.
2064
2065 2016-02-01  Michael McConville  <mmcco@mykolab.com>
2066
2067         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
2068         test bit.
2069
2070 2016-01-25  Renlin Li  <renlin.li@arm.com>
2071
2072         * arm-dis.c (mapping_symbol_for_insn): New function.
2073         (find_ifthen_state): Call mapping_symbol_for_insn().
2074
2075 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
2076
2077         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
2078         of MSR UAO immediate operand.
2079
2080 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
2081
2082         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
2083         instruction support.
2084
2085 2016-01-17  Alan Modra  <amodra@gmail.com>
2086
2087         * configure: Regenerate.
2088
2089 2016-01-14  Nick Clifton  <nickc@redhat.com>
2090
2091         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
2092         instructions that can support stack pointer operations.
2093         * rl78-decode.c: Regenerate.
2094         * rl78-dis.c: Fix display of stack pointer in MOVW based
2095         instructions.
2096
2097 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
2098
2099         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
2100         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
2101         erxtatus_el1 and erxaddr_el1.
2102
2103 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
2104
2105         * arm-dis.c (arm_opcodes): Add "esb".
2106         (thumb_opcodes): Likewise.
2107
2108 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
2109
2110         * ppc-opc.c <xscmpnedp>: Delete.
2111         <xvcmpnedp>: Likewise.
2112         <xvcmpnedp.>: Likewise.
2113         <xvcmpnesp>: Likewise.
2114         <xvcmpnesp.>: Likewise.
2115
2116 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
2117
2118         PR gas/13050
2119         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
2120         addition to ISA_A.
2121
2122 2016-01-01  Alan Modra  <amodra@gmail.com>
2123
2124         Update year range in copyright notice of all files.
2125
2126 For older changes see ChangeLog-2015
2127 \f
2128 Copyright (C) 2016 Free Software Foundation, Inc.
2129
2130 Copying and distribution of this file, with or without modification,
2131 are permitted in any medium without royalty provided the copyright
2132 notice and this notice are preserved.
2133
2134 Local Variables:
2135 mode: change-log
2136 left-margin: 8
2137 fill-column: 74
2138 version-control: never
2139 End: