1 2020-07-21 Jan Beulich <jbeulich@suse.com>
3 * i386-dis.c (OP_E_memory): Revert previous change.
5 2020-07-15 H.J. Lu <hongjiu.lu@intel.com>
8 * i386-dis.c (OP_E_memory): Don't display eiz with no scale
9 without base nor index registers.
11 2020-07-15 Jan Beulich <jbeulich@suse.com>
13 * i386-dis.c (putop): Move 'V' and 'W' handling.
15 2020-07-15 Jan Beulich <jbeulich@suse.com>
17 * i386-dis.c (dis386): Adjust 'V' description. Use P-based
18 construct for push/pop of register.
19 (putop): Honor cond when handling 'P'. Drop handling of plain
22 2020-07-15 Jan Beulich <jbeulich@suse.com>
24 * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
25 description. Drop '&' description. Use P for push of immediate,
26 pushf/popf, enter, and leave. Use %LP for lret/retf.
27 (dis386_twobyte): Use P for push/pop of fs/gs.
28 (reg_table): Use P for push/pop. Use @ for near call/jmp.
29 (x86_64_table): Use P for far call/jmp.
30 (putop): Drop handling of 'U' and '&'. Move and adjust handling
31 of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
33 (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
34 and dqw_mode (unconditional).
36 2020-07-14 H.J. Lu <hongjiu.lu@intel.com>
39 * i386-dis.c (OP_E_memory): Without base nor index registers,
40 32-bit displacement to 64 bits.
42 2020-07-14 Claudiu Zissulescu <claziss@gmail.com>
44 * arc-dis.c (print_insn_arc): Detect and emit a warning when a
45 faulty double register pair is detected.
47 2020-07-14 Jan Beulich <jbeulich@suse.com>
49 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
51 2020-07-14 Jan Beulich <jbeulich@suse.com>
53 * i386-dis.c (OP_R, Rm): Delete.
54 (MOD_0F24, MOD_0F26): Rename to ...
55 (X86_64_0F24, X86_64_0F26): ... respectively.
56 (dis386): Update 'L' and 'Z' comments.
57 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
59 (mod_table): Move opcode 0F24 and 0F26 entries ...
60 (x86_64_table): ... here.
61 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
64 2020-07-14 Jan Beulich <jbeulich@suse.com>
66 * i386-dis.c (Rd, Rdq, MaskR): Delete.
67 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
68 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
69 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
70 MOD_EVEX_0F387C): New enumerators.
71 (reg_table): Use Edq for rdssp.
72 (prefix_table): Use Edq for incssp.
73 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
74 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
75 ktest*, and kshift*. Use Edq / MaskE for kmov*.
76 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
77 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
78 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
79 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
80 0F3828_P_1 and 0F3838_P_1.
81 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
82 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
84 2020-07-14 Jan Beulich <jbeulich@suse.com>
86 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
87 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
88 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
89 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
90 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
91 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
92 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
93 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
94 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
95 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
96 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
97 (reg_table, prefix_table, three_byte_table, vex_table,
98 vex_len_table, mod_table, rm_table): Replace / remove respective
100 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
101 of PREFIX_DATA in used_prefixes.
103 2020-07-14 Jan Beulich <jbeulich@suse.com>
105 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
106 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
107 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
108 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
109 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
110 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
111 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
112 VEX_W_0F3A33_L_0): Delete.
113 (dis386): Adjust "BW" description.
114 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
115 0F3A31, 0F3A32, and 0F3A33.
116 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
118 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
121 2020-07-14 Jan Beulich <jbeulich@suse.com>
123 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
124 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
125 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
126 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
127 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
128 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
129 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
130 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
131 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
132 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
133 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
134 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
135 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
136 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
137 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
138 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
139 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
140 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
141 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
142 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
143 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
144 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
145 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
146 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
147 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
148 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
149 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
150 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
151 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
152 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
153 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
154 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
155 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
156 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
157 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
158 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
159 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
160 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
161 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
162 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
163 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
164 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
165 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
166 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
167 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
168 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
169 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
170 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
171 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
172 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
173 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
174 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
175 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
176 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
177 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
178 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
179 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
180 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
181 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
182 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
183 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
184 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
185 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
186 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
187 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
188 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
189 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
190 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
191 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
192 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
193 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
194 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
195 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
196 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
197 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
198 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
199 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
200 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
201 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
202 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
203 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
204 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
205 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
206 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
207 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
208 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
209 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
210 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
211 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
212 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
213 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
214 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
215 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
216 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
217 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
218 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
219 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
220 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
221 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
222 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
223 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
224 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
225 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
226 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
227 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
228 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
229 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
230 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
231 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
232 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
233 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
234 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
235 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
236 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
237 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
238 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
239 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
240 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
241 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
242 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
243 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
244 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
245 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
246 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
247 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
248 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
249 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
250 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
251 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
252 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
253 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
254 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
255 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
256 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
257 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
258 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
259 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
260 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
261 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
262 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
263 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
264 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
265 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
266 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
267 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
268 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
269 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
270 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
271 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
272 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
273 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
274 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
275 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
276 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
277 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
278 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
279 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
280 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
281 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
282 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
283 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
284 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
285 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
286 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
287 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
288 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
289 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
290 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
291 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
292 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
293 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
294 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
295 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
296 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
297 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
298 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
299 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
300 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
301 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
302 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
303 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
304 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
305 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
306 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
307 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
308 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
309 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
310 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
311 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
312 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
313 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
314 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
315 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
316 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
317 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
318 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
319 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
320 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
321 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
322 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
323 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
324 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
325 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
326 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
327 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
328 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
329 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
330 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
331 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
332 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
333 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
334 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
335 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
336 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
337 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
338 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
339 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
340 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
341 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
342 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
343 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
344 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
345 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
346 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
347 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
348 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
349 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
350 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
351 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
352 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
353 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
354 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
355 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
356 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
357 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
358 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
359 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
360 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
361 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
362 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
363 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
364 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
365 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
366 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
367 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
368 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
369 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
370 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
371 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
372 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
373 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
374 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
375 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
376 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
377 EVEX_W_0F3A72_P_2): Rename to ...
378 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
379 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
380 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
381 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
382 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
383 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
384 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
385 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
386 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
387 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
388 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
389 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
390 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
391 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
392 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
393 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
394 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
395 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
396 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
397 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
398 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
399 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
400 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
401 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
402 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
403 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
404 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
405 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
406 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
407 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
408 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
409 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
410 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
411 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
412 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
413 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
414 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
415 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
416 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
417 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
418 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
419 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
420 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
421 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
422 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
423 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
424 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
425 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
426 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
427 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
428 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
429 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
430 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
431 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
432 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
433 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
434 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
435 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
436 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
437 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
438 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
439 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
440 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
441 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
442 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
443 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
444 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
445 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
446 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
447 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
448 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
449 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
451 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
452 vex_w_table, mod_table): Replace / remove respective entries.
453 (print_insn): Move up dp->prefix_requirement handling. Handle
455 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
456 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
457 Replace / remove respective entries.
459 2020-07-14 Jan Beulich <jbeulich@suse.com>
461 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
462 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
463 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
464 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
465 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
467 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
468 0F2C, 0F2D, 0F2E, and 0F2F.
469 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
472 2020-07-14 Jan Beulich <jbeulich@suse.com>
474 * i386-dis.c (OP_VexR, VexScalarR): New.
475 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
476 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
477 need_vex_reg): Delete.
478 (prefix_table): Replace VexScalar by VexScalarR and
479 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
480 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
481 (vex_len_table): Replace EXqVexScalarS by EXqS.
482 (get_valid_dis386): Don't set need_vex_reg.
483 (print_insn): Don't initialize need_vex_reg.
484 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
485 q_scalar_swap_mode cases.
486 (OP_EX): Don't check for d_scalar_swap_mode and
488 (OP_VEX): Done check need_vex_reg.
489 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
490 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
491 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
493 2020-07-14 Jan Beulich <jbeulich@suse.com>
495 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
496 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
497 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
498 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
499 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
500 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
501 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
502 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
503 (vex_table): Replace Vex128 by Vex.
504 (vex_len_table): Likewise. Adjust referenced enum names.
505 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
506 referenced enum names.
507 (OP_VEX): Drop vex128_mode and vex256_mode cases.
508 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
510 2020-07-14 Jan Beulich <jbeulich@suse.com>
512 * i386-dis.c (dis386): "LW" description now applies to "DQ".
513 (putop): Handle "DQ". Don't handle "LW" anymore.
514 (prefix_table, mod_table): Replace %LW by %DQ.
515 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
517 2020-07-14 Jan Beulich <jbeulich@suse.com>
519 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
520 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
521 d_scalar_swap_mode case handling. Move shift adjsutment into
522 the case its applicable to.
524 2020-07-14 Jan Beulich <jbeulich@suse.com>
526 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
527 (EXbScalar, EXwScalar): Fold to ...
528 (EXbwUnit): ... this.
529 (b_scalar_mode, w_scalar_mode): Fold to ...
530 (bw_unit_mode): ... this.
531 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
532 w_scalar_mode handling by bw_unit_mode one.
533 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
535 * i386-dis-evex-prefix.h: ... here.
537 2020-07-14 Jan Beulich <jbeulich@suse.com>
539 * i386-dis.c (PCMPESTR_Fixup): Delete.
540 (dis386): Adjust "LQ" description.
541 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
542 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
543 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
544 vpcmpestrm, and vpcmpestri.
545 (putop): Honor "cond" when handling LQ.
546 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
547 vcvtsi2ss and vcvtusi2ss.
548 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
549 vcvtsi2sd and vcvtusi2sd.
551 2020-07-14 Jan Beulich <jbeulich@suse.com>
553 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
554 (simd_cmp_op): Add const.
555 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
556 (CMP_Fixup): Handle VEX case.
557 (prefix_table): Replace VCMP by CMP.
558 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
560 2020-07-14 Jan Beulich <jbeulich@suse.com>
562 * i386-dis.c (MOVBE_Fixup): Delete.
564 (prefix_table): Use Mv for movbe entries.
566 2020-07-14 Jan Beulich <jbeulich@suse.com>
568 * i386-dis.c (CRC32_Fixup): Delete.
569 (prefix_table): Use Eb/Ev for crc32 entries.
571 2020-07-14 Jan Beulich <jbeulich@suse.com>
573 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
574 Conditionalize invocations of "USED_REX (0)".
576 2020-07-14 Jan Beulich <jbeulich@suse.com>
578 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
579 CH, DH, BH, AX, DX): Delete.
580 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
581 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
582 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
584 2020-07-10 Lili Cui <lili.cui@intel.com>
586 * i386-dis.c (TMM): New.
589 (MVexSIBMEM): Likewise.
590 (tmm_mode): Likewise.
591 (vex_sibmem_mode): Likewise.
592 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
593 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
594 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
595 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
596 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
597 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
598 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
599 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
600 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
601 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
602 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
603 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
604 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
605 (PREFIX_VEX_0F3849_X86_64): Likewise.
606 (PREFIX_VEX_0F384B_X86_64): Likewise.
607 (PREFIX_VEX_0F385C_X86_64): Likewise.
608 (PREFIX_VEX_0F385E_X86_64): Likewise.
609 (X86_64_VEX_0F3849): Likewise.
610 (X86_64_VEX_0F384B): Likewise.
611 (X86_64_VEX_0F385C): Likewise.
612 (X86_64_VEX_0F385E): Likewise.
613 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
614 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
615 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
616 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
617 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
618 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
619 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
620 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
621 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
622 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
623 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
624 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
625 (VEX_W_0F3849_X86_64_P_0): Likewise.
626 (VEX_W_0F3849_X86_64_P_2): Likewise.
627 (VEX_W_0F3849_X86_64_P_3): Likewise.
628 (VEX_W_0F384B_X86_64_P_1): Likewise.
629 (VEX_W_0F384B_X86_64_P_2): Likewise.
630 (VEX_W_0F384B_X86_64_P_3): Likewise.
631 (VEX_W_0F385C_X86_64_P_1): Likewise.
632 (VEX_W_0F385E_X86_64_P_0): Likewise.
633 (VEX_W_0F385E_X86_64_P_1): Likewise.
634 (VEX_W_0F385E_X86_64_P_2): Likewise.
635 (VEX_W_0F385E_X86_64_P_3): Likewise.
636 (names_tmm): Likewise.
637 (att_names_tmm): Likewise.
638 (intel_operand_size): Handle void_mode.
639 (OP_XMM): Handle tmm_mode.
642 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
643 CpuAMX_BF16 and CpuAMX_TILE.
644 (operand_type_shorthands): Add RegTMM.
645 (operand_type_init): Likewise.
646 (operand_types): Add Tmmword.
647 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
648 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
649 * i386-opc.h (CpuAMX_INT8): New.
650 (CpuAMX_BF16): Likewise.
651 (CpuAMX_TILE): Likewise.
654 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
655 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
656 (i386_operand_type): Add tmmword.
657 * i386-opc.tbl: Add AMX instructions.
658 * i386-reg.tbl: Add AMX registers.
659 * i386-init.h: Regenerated.
660 * i386-tbl.h: Likewise.
662 2020-07-08 Jan Beulich <jbeulich@suse.com>
664 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
665 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
667 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
668 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
670 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
671 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
672 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
673 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
674 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
675 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
676 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
677 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
678 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
679 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
680 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
681 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
682 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
683 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
684 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
685 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
686 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
687 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
688 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
689 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
690 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
691 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
692 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
693 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
694 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
695 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
696 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
697 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
698 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
699 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
700 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
701 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
702 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
703 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
704 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
705 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
706 (reg_table): Re-order XOP entries. Adjust their operands.
707 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
708 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
709 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
710 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
711 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
712 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
713 entries by references ...
714 (vex_len_table): ... to resepctive new entries here. For several
715 new and existing entries reference ...
716 (vex_w_table): ... new entries here.
717 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
719 2020-07-08 Jan Beulich <jbeulich@suse.com>
721 * i386-dis.c (XMVexScalarI4): Define.
722 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
723 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
724 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
725 (vex_len_table): Move scalar FMA4 entries ...
726 (prefix_table): ... here.
727 (OP_REG_VexI4): Handle scalar_mode.
728 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
729 * i386-tbl.h: Re-generate.
731 2020-07-08 Jan Beulich <jbeulich@suse.com>
733 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
735 (OP_VexW, VexW): New.
736 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
737 for shifts and rotates by register.
739 2020-07-08 Jan Beulich <jbeulich@suse.com>
741 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
742 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
743 OP_EX_VexReg): Delete.
744 (OP_VexI4, VexI4): New.
745 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
746 (prefix_table): ... here.
747 (print_insn): Drop setting of vex_w_done.
749 2020-07-08 Jan Beulich <jbeulich@suse.com>
751 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
752 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
753 (xop_table): Replace operands of 4-operand insns.
754 (OP_REG_VexI4): Move VEX.W based operand swaping here.
756 2020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
758 * arc-opc.c (insert_rbd): New function.
761 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
764 2020-07-07 Jan Beulich <jbeulich@suse.com>
766 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
767 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
768 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
769 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
771 (putop): Handle "BW".
772 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
773 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
775 * i386-dis-evex-prefix.h: ... here.
777 2020-07-06 Jan Beulich <jbeulich@suse.com>
779 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
780 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
781 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
782 VEX_W_0FXOP_09_83): New enumerators.
783 (xop_table): Reference the above.
784 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
785 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
786 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
787 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
789 2020-07-06 Jan Beulich <jbeulich@suse.com>
791 * i386-dis.c (EVEX_W_0F3838_P_1,
792 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
793 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
794 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
795 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
796 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
797 (putop): Centralize management of last[]. Delete SAVE_LAST.
798 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
799 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
800 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
801 * i386-dis-evex-prefix.h: here.
803 2020-07-06 Jan Beulich <jbeulich@suse.com>
805 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
806 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
807 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
808 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
810 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
811 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
812 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
813 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
814 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
815 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
816 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
817 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
819 * i386-dis-evex-len.h: Adjust comments.
820 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
821 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
822 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
823 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
824 MOD_EVEX_0F385B_P_2_W_1 table entries.
825 * i386-dis-evex-w.h: Reference mod_table[] for
826 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
829 2020-07-06 Jan Beulich <jbeulich@suse.com>
831 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
832 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
834 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
835 Likewise. Mark 256-bit entries invalid.
837 2020-07-06 Jan Beulich <jbeulich@suse.com>
839 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
840 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
841 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
842 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
843 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
844 PREFIX_EVEX_0F382B): Delete.
845 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
846 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
847 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
848 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
849 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
851 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
852 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
853 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
854 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
856 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
857 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
858 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
859 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
860 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
861 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
862 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
863 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
864 PREFIX_EVEX_0F382B): Remove table entries.
865 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
866 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
867 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
869 2020-07-06 Jan Beulich <jbeulich@suse.com>
871 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
872 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
874 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
875 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
876 EVEX_LEN_0F3A01_P_2_W_1 table entries.
877 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
880 2020-07-06 Jan Beulich <jbeulich@suse.com>
882 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
883 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
884 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
885 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
886 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
887 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
888 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
889 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
890 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
893 2020-07-06 Jan Beulich <jbeulich@suse.com>
895 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
896 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
897 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
899 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
901 * i386-dis-evex.h (evex_table): Reference VEX table entry for
903 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
905 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
907 2020-07-06 Jan Beulich <jbeulich@suse.com>
909 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
910 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
911 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
912 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
913 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
914 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
915 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
916 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
917 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
918 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
919 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
920 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
921 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
922 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
923 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
924 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
925 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
926 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
927 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
928 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
929 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
930 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
931 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
932 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
933 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
934 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
935 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
936 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
937 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
938 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
939 (prefix_table): Add EXxEVexR to FMA table entries.
940 (OP_Rounding): Move abort() invocation.
941 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
942 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
943 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
944 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
945 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
946 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
947 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
948 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
949 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
950 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
952 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
953 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
954 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
955 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
956 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
957 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
958 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
959 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
960 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
961 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
962 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
963 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
964 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
965 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
966 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
967 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
968 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
969 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
970 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
971 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
972 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
973 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
974 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
975 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
976 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
977 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
978 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
979 Delete table entries.
980 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
981 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
982 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
985 2020-07-06 Jan Beulich <jbeulich@suse.com>
987 * i386-dis.c (EXqScalarS): Delete.
988 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
989 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
991 2020-07-06 Jan Beulich <jbeulich@suse.com>
993 * i386-dis.c (safe-ctype.h): Include.
994 (EXdScalar, EXqScalar): Delete.
995 (d_scalar_mode, q_scalar_mode): Delete.
996 (prefix_table, vex_len_table): Use EXxmm_md in place of
997 EXdScalar and EXxmm_mq in place of EXqScalar.
998 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
999 d_scalar_mode and q_scalar_mode.
1000 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1001 (vmovsd): Use EXxmm_mq.
1003 2020-07-06 Yuri Chornoivan <yurchor@ukr.net>
1006 * arc-dis.c: Fix spelling mistake.
1007 * po/opcodes.pot: Regenerate.
1009 2020-07-06 Nick Clifton <nickc@redhat.com>
1011 * po/pt_BR.po: Updated Brazilian Portugugese translation.
1012 * po/uk.po: Updated Ukranian translation.
1014 2020-07-04 Nick Clifton <nickc@redhat.com>
1016 * configure: Regenerate.
1017 * po/opcodes.pot: Regenerate.
1019 2020-07-04 Nick Clifton <nickc@redhat.com>
1021 Binutils 2.35 branch created.
1023 2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
1025 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1026 * i386-opc.h (VexSwapSources): New.
1027 (i386_opcode_modifier): Add vexswapsources.
1028 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1029 with two source operands swapped.
1030 * i386-tbl.h: Regenerated.
1032 2020-06-30 Nelson Chu <nelson.chu@sifive.com>
1034 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
1035 unprivileged CSR can also be initialized.
1037 2020-06-29 Alan Modra <amodra@gmail.com>
1039 * arm-dis.c: Use C style comments.
1040 * cr16-opc.c: Likewise.
1041 * ft32-dis.c: Likewise.
1042 * moxie-opc.c: Likewise.
1043 * tic54x-dis.c: Likewise.
1044 * s12z-opc.c: Remove useless comment.
1045 * xgate-dis.c: Likewise.
1047 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1049 * i386-opc.tbl: Add a blank line.
1051 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1053 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1054 (VecSIB128): Renamed to ...
1056 (VecSIB256): Renamed to ...
1058 (VecSIB512): Renamed to ...
1060 (VecSIB): Renamed to ...
1062 (i386_opcode_modifier): Replace vecsib with sib.
1063 * i386-opc.tbl (VecSIB128): New.
1064 (VecSIB256): Likewise.
1065 (VecSIB512): Likewise.
1066 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
1067 and VecSIB512, respectively.
1069 2020-06-26 Jan Beulich <jbeulich@suse.com>
1071 * i386-dis.c: Adjust description of I macro.
1072 (x86_64_table): Drop use of I.
1073 (float_mem): Replace use of I.
1074 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1076 2020-06-26 Jan Beulich <jbeulich@suse.com>
1078 * i386-dis.c: (print_insn): Avoid straight assignment to
1079 priv.orig_sizeflag when processing -M sub-options.
1081 2020-06-25 Jan Beulich <jbeulich@suse.com>
1083 * i386-dis.c: Adjust description of J macro.
1084 (dis386, x86_64_table, mod_table): Replace J.
1085 (putop): Remove handling of J.
1087 2020-06-25 Jan Beulich <jbeulich@suse.com>
1089 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1091 2020-06-25 Jan Beulich <jbeulich@suse.com>
1093 * i386-dis.c: Adjust description of "LQ" macro.
1094 (dis386_twobyte): Use LQ for sysret.
1095 (putop): Adjust handling of LQ.
1097 2020-06-22 Nelson Chu <nelson.chu@sifive.com>
1099 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1100 * riscv-dis.c: Include elfxx-riscv.h.
1102 2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1104 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1106 2020-06-17 Lili Cui <lili.cui@intel.com>
1108 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1110 2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1113 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1114 * i386-opc.tbl: Likewise.
1115 * i386-tbl.h: Regenerated.
1117 2020-06-12 Nelson Chu <nelson.chu@sifive.com>
1119 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1121 2020-06-11 Alex Coplan <alex.coplan@arm.com>
1123 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1124 (SR_CORE): Likewise.
1125 (SR_FEAT): Likewise.
1127 (SR_V8_1): Likewise.
1128 (SR_V8_2): Likewise.
1129 (SR_V8_3): Likewise.
1130 (SR_V8_4): Likewise.
1133 (SR_SSBS): Likewise.
1135 (SR_ID_PFR2): Likewise.
1136 (SR_PROFILE): Likewise.
1137 (SR_MEMTAG): Likewise.
1138 (SR_SCXTNUM): Likewise.
1139 (aarch64_sys_regs): Refactor to store feature information in the table.
1140 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1141 that now describe their own features.
1142 (aarch64_pstatefield_supported_p): Likewise.
1144 2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1146 * i386-dis.c (prefix_table): Fix a typo in comments.
1148 2020-06-09 Jan Beulich <jbeulich@suse.com>
1150 * i386-dis.c (rex_ignored): Delete.
1151 (ckprefix): Drop rex_ignored initialization.
1152 (get_valid_dis386): Drop setting of rex_ignored.
1153 (print_insn): Drop checking of rex_ignored. Don't record data
1154 size prefix as used with VEX-and-alike encodings.
1156 2020-06-09 Jan Beulich <jbeulich@suse.com>
1158 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1159 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1160 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1161 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1162 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1163 VEX_0F12, and VEX_0F16.
1164 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1165 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1166 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1167 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1168 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1169 MOD_VEX_0F16_PREFIX_2 entries.
1171 2020-06-09 Jan Beulich <jbeulich@suse.com>
1173 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1174 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1175 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1176 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1177 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1178 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1179 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1180 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1181 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1182 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1183 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1184 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1185 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1186 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1187 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1188 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1189 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1190 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1191 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1192 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1193 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1194 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1195 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1196 EVEX_W_0FC6_P_2): Delete.
1197 (print_insn): Add EVEX.W vs embedded prefix consistency check
1198 to prefix validation.
1199 * i386-dis-evex.h (evex_table): Don't further descend for
1200 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1201 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1203 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1204 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1205 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1206 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1207 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1208 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1209 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1210 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1211 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1212 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1213 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1214 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1215 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1216 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1217 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1218 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1219 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1220 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1221 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1222 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1223 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1224 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1225 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1226 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1227 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1228 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1229 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1231 2020-06-09 Jan Beulich <jbeulich@suse.com>
1233 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1234 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1235 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1237 (print_insn): Drop pointless check against bad_opcode. Split
1238 prefix validation into legacy and VEX-and-alike parts.
1239 (putop): Re-work 'X' macro handling.
1241 2020-06-09 Jan Beulich <jbeulich@suse.com>
1243 * i386-dis.c (MOD_0F51): Rename to ...
1244 (MOD_0F50): ... this.
1246 2020-06-08 Alex Coplan <alex.coplan@arm.com>
1248 * arm-dis.c (arm_opcodes): Add dfb.
1249 (thumb32_opcodes): Add dfb.
1251 2020-06-08 Jan Beulich <jbeulich@suse.com>
1253 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1255 2020-06-06 Alan Modra <amodra@gmail.com>
1257 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1259 2020-06-05 Alan Modra <amodra@gmail.com>
1261 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1262 size is large enough.
1264 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1266 * disassemble.c (disassemble_init_for_target): Set endian_code for
1268 * bpf-desc.c: Regenerate.
1269 * bpf-opc.c: Likewise.
1270 * bpf-dis.c: Likewise.
1272 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1274 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1275 (cgen_put_insn_value): Likewise.
1276 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1277 * cgen-dis.in (print_insn): Likewise.
1278 * cgen-ibld.in (insert_1): Likewise.
1279 (insert_1): Likewise.
1280 (insert_insn_normal): Likewise.
1281 (extract_1): Likewise.
1282 * bpf-dis.c: Regenerate.
1283 * bpf-ibld.c: Likewise.
1284 * bpf-ibld.c: Likewise.
1285 * cgen-dis.in: Likewise.
1286 * cgen-ibld.in: Likewise.
1287 * cgen-opc.c: Likewise.
1288 * epiphany-dis.c: Likewise.
1289 * epiphany-ibld.c: Likewise.
1290 * fr30-dis.c: Likewise.
1291 * fr30-ibld.c: Likewise.
1292 * frv-dis.c: Likewise.
1293 * frv-ibld.c: Likewise.
1294 * ip2k-dis.c: Likewise.
1295 * ip2k-ibld.c: Likewise.
1296 * iq2000-dis.c: Likewise.
1297 * iq2000-ibld.c: Likewise.
1298 * lm32-dis.c: Likewise.
1299 * lm32-ibld.c: Likewise.
1300 * m32c-dis.c: Likewise.
1301 * m32c-ibld.c: Likewise.
1302 * m32r-dis.c: Likewise.
1303 * m32r-ibld.c: Likewise.
1304 * mep-dis.c: Likewise.
1305 * mep-ibld.c: Likewise.
1306 * mt-dis.c: Likewise.
1307 * mt-ibld.c: Likewise.
1308 * or1k-dis.c: Likewise.
1309 * or1k-ibld.c: Likewise.
1310 * xc16x-dis.c: Likewise.
1311 * xc16x-ibld.c: Likewise.
1312 * xstormy16-dis.c: Likewise.
1313 * xstormy16-ibld.c: Likewise.
1315 2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1317 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1318 (print_insn_): Handle instruction endian.
1319 * bpf-dis.c: Regenerate.
1320 * bpf-desc.c: Regenerate.
1321 * epiphany-dis.c: Likewise.
1322 * epiphany-desc.c: Likewise.
1323 * fr30-dis.c: Likewise.
1324 * fr30-desc.c: Likewise.
1325 * frv-dis.c: Likewise.
1326 * frv-desc.c: Likewise.
1327 * ip2k-dis.c: Likewise.
1328 * ip2k-desc.c: Likewise.
1329 * iq2000-dis.c: Likewise.
1330 * iq2000-desc.c: Likewise.
1331 * lm32-dis.c: Likewise.
1332 * lm32-desc.c: Likewise.
1333 * m32c-dis.c: Likewise.
1334 * m32c-desc.c: Likewise.
1335 * m32r-dis.c: Likewise.
1336 * m32r-desc.c: Likewise.
1337 * mep-dis.c: Likewise.
1338 * mep-desc.c: Likewise.
1339 * mt-dis.c: Likewise.
1340 * mt-desc.c: Likewise.
1341 * or1k-dis.c: Likewise.
1342 * or1k-desc.c: Likewise.
1343 * xc16x-dis.c: Likewise.
1344 * xc16x-desc.c: Likewise.
1345 * xstormy16-dis.c: Likewise.
1346 * xstormy16-desc.c: Likewise.
1348 2020-06-03 Nick Clifton <nickc@redhat.com>
1350 * po/sr.po: Updated Serbian translation.
1352 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
1354 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1355 (riscv_get_priv_spec_class): Likewise.
1357 2020-06-01 Alan Modra <amodra@gmail.com>
1359 * bpf-desc.c: Regenerate.
1361 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1362 David Faust <david.faust@oracle.com>
1364 * bpf-desc.c: Regenerate.
1365 * bpf-opc.h: Likewise.
1366 * bpf-opc.c: Likewise.
1367 * bpf-dis.c: Likewise.
1369 2020-05-28 Alan Modra <amodra@gmail.com>
1371 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1374 2020-05-28 Alan Modra <amodra@gmail.com>
1376 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1378 (print_insn_ns32k): Revert last change.
1380 2020-05-28 Nick Clifton <nickc@redhat.com>
1382 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1385 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
1387 Fix extraction of signed constants in nios2 disassembler (again).
1389 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
1390 extractions of signed fields.
1392 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1394 * s390-opc.txt: Relocate vector load/store instructions with
1395 additional alignment parameter and change architecture level
1396 constraint from z14 to z13.
1398 2020-05-21 Alan Modra <amodra@gmail.com>
1400 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
1401 * sparc-dis.c: Likewise.
1402 * tic4x-dis.c: Likewise.
1403 * xtensa-dis.c: Likewise.
1404 * bpf-desc.c: Regenerate.
1405 * epiphany-desc.c: Regenerate.
1406 * fr30-desc.c: Regenerate.
1407 * frv-desc.c: Regenerate.
1408 * ip2k-desc.c: Regenerate.
1409 * iq2000-desc.c: Regenerate.
1410 * lm32-desc.c: Regenerate.
1411 * m32c-desc.c: Regenerate.
1412 * m32r-desc.c: Regenerate.
1413 * mep-asm.c: Regenerate.
1414 * mep-desc.c: Regenerate.
1415 * mt-desc.c: Regenerate.
1416 * or1k-desc.c: Regenerate.
1417 * xc16x-desc.c: Regenerate.
1418 * xstormy16-desc.c: Regenerate.
1420 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
1422 * riscv-opc.c (riscv_ext_version_table): The table used to store
1423 all information about the supported spec and the corresponding ISA
1424 versions. Currently, only Zicsr is supported to verify the
1425 correctness of Z sub extension settings. Others will be supported
1426 in the future patches.
1427 (struct isa_spec_t, isa_specs): List for all supported ISA spec
1428 classes and the corresponding strings.
1429 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
1430 spec class by giving a ISA spec string.
1431 * riscv-opc.c (struct priv_spec_t): New structure.
1432 (struct priv_spec_t priv_specs): List for all supported privilege spec
1433 classes and the corresponding strings.
1434 (riscv_get_priv_spec_class): New function. Get the corresponding
1435 privilege spec class by giving a spec string.
1436 (riscv_get_priv_spec_name): New function. Get the corresponding
1437 privilege spec string by giving a CSR version class.
1438 * riscv-dis.c: Updated since DECLARE_CSR is changed.
1439 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
1440 according to the chosen version. Build a hash table riscv_csr_hash to
1441 store the valid CSR for the chosen pirv verison. Dump the direct
1442 CSR address rather than it's name if it is invalid.
1443 (parse_riscv_dis_option_without_args): New function. Parse the options
1445 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
1446 parse the options without arguments first, and then handle the options
1447 with arguments. Add the new option -Mpriv-spec, which has argument.
1448 * riscv-dis.c (print_riscv_disassembler_options): Add description
1449 about the new OBJDUMP option.
1451 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
1453 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
1454 WC values on POWER10 sync, dcbf and wait instructions.
1455 (insert_pl, extract_pl): New functions.
1456 (L2OPT, LS, WC): Use insert_ls and extract_ls.
1457 (LS3): New , 3-bit L for sync.
1458 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
1459 (SC2, PL): New, 2-bit SC and PL for sync and wait.
1460 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
1461 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
1462 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
1463 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
1464 <wait>: Enable PL operand on POWER10.
1465 <dcbf>: Enable L3OPT operand on POWER10.
1466 <sync>: Enable SC2 operand on POWER10.
1468 2020-05-19 Stafford Horne <shorne@gmail.com>
1471 * or1k-asm.c: Regenerate.
1472 * or1k-desc.c: Regenerate.
1473 * or1k-desc.h: Regenerate.
1474 * or1k-dis.c: Regenerate.
1475 * or1k-ibld.c: Regenerate.
1476 * or1k-opc.c: Regenerate.
1477 * or1k-opc.h: Regenerate.
1478 * or1k-opinst.c: Regenerate.
1480 2020-05-11 Alan Modra <amodra@gmail.com>
1482 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
1485 2020-05-11 Alan Modra <amodra@gmail.com>
1487 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
1488 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
1490 2020-05-11 Alan Modra <amodra@gmail.com>
1492 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
1494 2020-05-11 Alan Modra <amodra@gmail.com>
1496 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
1497 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
1499 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1501 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
1504 2020-05-11 Alan Modra <amodra@gmail.com>
1506 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
1507 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
1508 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
1509 (prefix_opcodes): Add xxeval.
1511 2020-05-11 Alan Modra <amodra@gmail.com>
1513 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
1514 xxgenpcvwm, xxgenpcvdm.
1516 2020-05-11 Alan Modra <amodra@gmail.com>
1518 * ppc-opc.c (MP, VXVAM_MASK): Define.
1519 (VXVAPS_MASK): Use VXVA_MASK.
1520 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
1521 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
1522 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
1523 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
1525 2020-05-11 Alan Modra <amodra@gmail.com>
1526 Peter Bergner <bergner@linux.ibm.com>
1528 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
1530 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
1531 YMSK2, XA6a, XA6ap, XB6a entries.
1532 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
1533 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
1535 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
1536 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
1537 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
1538 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
1539 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
1540 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
1541 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
1542 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
1543 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
1544 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
1545 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
1546 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
1547 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
1548 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
1550 2020-05-11 Alan Modra <amodra@gmail.com>
1552 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
1553 (insert_xts, extract_xts): New functions.
1554 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
1555 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
1556 (VXRC_MASK, VXSH_MASK): Define.
1557 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
1558 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
1559 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
1560 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
1561 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
1562 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
1563 xxblendvh, xxblendvw, xxblendvd, xxpermx.
1565 2020-05-11 Alan Modra <amodra@gmail.com>
1567 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
1568 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
1569 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
1570 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
1571 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
1573 2020-05-11 Alan Modra <amodra@gmail.com>
1575 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
1576 (XTP, DQXP, DQXP_MASK): Define.
1577 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
1578 (prefix_opcodes): Add plxvp and pstxvp.
1580 2020-05-11 Alan Modra <amodra@gmail.com>
1582 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
1583 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
1584 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
1586 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1588 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
1590 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1592 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
1594 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
1596 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1598 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
1600 2020-05-11 Alan Modra <amodra@gmail.com>
1602 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
1604 2020-05-11 Alan Modra <amodra@gmail.com>
1606 * ppc-dis.c (ppc_opts): Add "power10" entry.
1607 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
1608 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
1610 2020-05-11 Nick Clifton <nickc@redhat.com>
1612 * po/fr.po: Updated French translation.
1614 2020-04-30 Alex Coplan <alex.coplan@arm.com>
1616 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
1617 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
1618 (operand_general_constraint_met_p): validate
1619 AARCH64_OPND_UNDEFINED.
1620 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
1622 * aarch64-asm-2.c: Regenerated.
1623 * aarch64-dis-2.c: Regenerated.
1624 * aarch64-opc-2.c: Regenerated.
1626 2020-04-29 Nick Clifton <nickc@redhat.com>
1629 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
1632 2020-04-29 Nick Clifton <nickc@redhat.com>
1634 * po/sv.po: Updated Swedish translation.
1636 2020-04-29 Nick Clifton <nickc@redhat.com>
1639 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
1640 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
1641 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
1644 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
1647 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
1648 cmpi only on m68020up and cpu32.
1650 2020-04-20 Sudakshina Das <sudi.das@arm.com>
1652 * aarch64-asm.c (aarch64_ins_none): New.
1653 * aarch64-asm.h (ins_none): New declaration.
1654 * aarch64-dis.c (aarch64_ext_none): New.
1655 * aarch64-dis.h (ext_none): New declaration.
1656 * aarch64-opc.c (aarch64_print_operand): Update case for
1657 AARCH64_OPND_BARRIER_PSB.
1658 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
1659 (AARCH64_OPERANDS): Update inserter/extracter for
1660 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
1661 * aarch64-asm-2.c: Regenerated.
1662 * aarch64-dis-2.c: Regenerated.
1663 * aarch64-opc-2.c: Regenerated.
1665 2020-04-20 Sudakshina Das <sudi.das@arm.com>
1667 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
1668 (aarch64_feature_ras, RAS): Likewise.
1669 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
1670 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
1671 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
1672 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
1673 * aarch64-asm-2.c: Regenerated.
1674 * aarch64-dis-2.c: Regenerated.
1675 * aarch64-opc-2.c: Regenerated.
1677 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
1679 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
1680 (print_insn_neon): Support disassembly of conditional
1683 2020-02-16 David Faust <david.faust@oracle.com>
1685 * bpf-desc.c: Regenerate.
1686 * bpf-desc.h: Likewise.
1687 * bpf-opc.c: Regenerate.
1688 * bpf-opc.h: Likewise.
1690 2020-04-07 Lili Cui <lili.cui@intel.com>
1692 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
1693 (prefix_table): New instructions (see prefixes above).
1694 (rm_table): Likewise
1695 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
1696 CPU_ANY_TSXLDTRK_FLAGS.
1697 (cpu_flags): Add CpuTSXLDTRK.
1698 * i386-opc.h (enum): Add CpuTSXLDTRK.
1699 (i386_cpu_flags): Add cputsxldtrk.
1700 * i386-opc.tbl: Add XSUSPLDTRK insns.
1701 * i386-init.h: Regenerate.
1702 * i386-tbl.h: Likewise.
1704 2020-04-02 Lili Cui <lili.cui@intel.com>
1706 * i386-dis.c (prefix_table): New instructions serialize.
1707 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
1708 CPU_ANY_SERIALIZE_FLAGS.
1709 (cpu_flags): Add CpuSERIALIZE.
1710 * i386-opc.h (enum): Add CpuSERIALIZE.
1711 (i386_cpu_flags): Add cpuserialize.
1712 * i386-opc.tbl: Add SERIALIZE insns.
1713 * i386-init.h: Regenerate.
1714 * i386-tbl.h: Likewise.
1716 2020-03-26 Alan Modra <amodra@gmail.com>
1718 * disassemble.h (opcodes_assert): Declare.
1719 (OPCODES_ASSERT): Define.
1720 * disassemble.c: Don't include assert.h. Include opintl.h.
1721 (opcodes_assert): New function.
1722 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
1723 (bfd_h8_disassemble): Reduce size of data array. Correctly
1724 calculate maxlen. Omit insn decoding when insn length exceeds
1725 maxlen. Exit from nibble loop when looking for E, before
1726 accessing next data byte. Move processing of E outside loop.
1727 Replace tests of maxlen in loop with assertions.
1729 2020-03-26 Alan Modra <amodra@gmail.com>
1731 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
1733 2020-03-25 Alan Modra <amodra@gmail.com>
1735 * z80-dis.c (suffix): Init mybuf.
1737 2020-03-22 Alan Modra <amodra@gmail.com>
1739 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
1740 successflly read from section.
1742 2020-03-22 Alan Modra <amodra@gmail.com>
1744 * arc-dis.c (find_format): Use ISO C string concatenation rather
1745 than line continuation within a string. Don't access needs_limm
1746 before testing opcode != NULL.
1748 2020-03-22 Alan Modra <amodra@gmail.com>
1750 * ns32k-dis.c (print_insn_arg): Update comment.
1751 (print_insn_ns32k): Reduce size of index_offset array, and
1752 initialize, passing -1 to print_insn_arg for args that are not
1753 an index. Don't exit arg loop early. Abort on bad arg number.
1755 2020-03-22 Alan Modra <amodra@gmail.com>
1757 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
1758 * s12z-opc.c: Formatting.
1759 (operands_f): Return an int.
1760 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
1761 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
1762 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
1763 (exg_sex_discrim): Likewise.
1764 (create_immediate_operand, create_bitfield_operand),
1765 (create_register_operand_with_size, create_register_all_operand),
1766 (create_register_all16_operand, create_simple_memory_operand),
1767 (create_memory_operand, create_memory_auto_operand): Don't
1768 segfault on malloc failure.
1769 (z_ext24_decode): Return an int status, negative on fail, zero
1771 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
1772 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
1773 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
1774 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
1775 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
1776 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
1777 (loop_primitive_decode, shift_decode, psh_pul_decode),
1778 (bit_field_decode): Similarly.
1779 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
1780 to return value, update callers.
1781 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
1782 Don't segfault on NULL operand.
1783 (decode_operation): Return OP_INVALID on first fail.
1784 (decode_s12z): Check all reads, returning -1 on fail.
1786 2020-03-20 Alan Modra <amodra@gmail.com>
1788 * metag-dis.c (print_insn_metag): Don't ignore status from
1791 2020-03-20 Alan Modra <amodra@gmail.com>
1793 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
1794 Initialize parts of buffer not written when handling a possible
1795 2-byte insn at end of section. Don't attempt decoding of such
1796 an insn by the 4-byte machinery.
1798 2020-03-20 Alan Modra <amodra@gmail.com>
1800 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
1801 partially filled buffer. Prevent lookup of 4-byte insns when
1802 only VLE 2-byte insns are possible due to section size. Print
1803 ".word" rather than ".long" for 2-byte leftovers.
1805 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
1808 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
1810 2020-03-13 Jan Beulich <jbeulich@suse.com>
1812 * i386-dis.c (X86_64_0D): Rename to ...
1813 (X86_64_0E): ... this.
1815 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
1817 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
1818 * Makefile.in: Regenerated.
1820 2020-03-09 Jan Beulich <jbeulich@suse.com>
1822 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
1824 * i386-tbl.h: Re-generate.
1826 2020-03-09 Jan Beulich <jbeulich@suse.com>
1828 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
1829 vprot*, vpsha*, and vpshl*.
1830 * i386-tbl.h: Re-generate.
1832 2020-03-09 Jan Beulich <jbeulich@suse.com>
1834 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
1835 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
1836 * i386-tbl.h: Re-generate.
1838 2020-03-09 Jan Beulich <jbeulich@suse.com>
1840 * i386-gen.c (set_bitfield): Ignore zero-length field names.
1841 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
1842 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
1843 * i386-tbl.h: Re-generate.
1845 2020-03-09 Jan Beulich <jbeulich@suse.com>
1847 * i386-gen.c (struct template_arg, struct template_instance,
1848 struct template_param, struct template, templates,
1849 parse_template, expand_templates): New.
1850 (process_i386_opcodes): Various local variables moved to
1851 expand_templates. Call parse_template and expand_templates.
1852 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
1853 * i386-tbl.h: Re-generate.
1855 2020-03-06 Jan Beulich <jbeulich@suse.com>
1857 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
1858 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
1859 register and memory source templates. Replace VexW= by VexW*
1861 * i386-tbl.h: Re-generate.
1863 2020-03-06 Jan Beulich <jbeulich@suse.com>
1865 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
1866 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
1867 * i386-tbl.h: Re-generate.
1869 2020-03-06 Jan Beulich <jbeulich@suse.com>
1871 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
1872 * i386-tbl.h: Re-generate.
1874 2020-03-06 Jan Beulich <jbeulich@suse.com>
1876 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
1877 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
1878 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
1879 VexW0 on SSE2AVX variants.
1880 (vmovq): Drop NoRex64 from XMM/XMM variants.
1881 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
1882 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
1883 applicable use VexW0.
1884 * i386-tbl.h: Re-generate.
1886 2020-03-06 Jan Beulich <jbeulich@suse.com>
1888 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
1889 * i386-opc.h (Rex64): Delete.
1890 (struct i386_opcode_modifier): Remove rex64 field.
1891 * i386-opc.tbl (crc32): Drop Rex64.
1892 Replace Rex64 with Size64 everywhere else.
1893 * i386-tbl.h: Re-generate.
1895 2020-03-06 Jan Beulich <jbeulich@suse.com>
1897 * i386-dis.c (OP_E_memory): Exclude recording of used address
1898 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1899 addressed memory operands for MPX insns.
1901 2020-03-06 Jan Beulich <jbeulich@suse.com>
1903 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1904 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1905 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1906 (ptwrite): Split into non-64-bit and 64-bit forms.
1907 * i386-tbl.h: Re-generate.
1909 2020-03-06 Jan Beulich <jbeulich@suse.com>
1911 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1913 * i386-tbl.h: Re-generate.
1915 2020-03-04 Jan Beulich <jbeulich@suse.com>
1917 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
1918 (prefix_table): Move vmmcall here. Add vmgexit.
1919 (rm_table): Replace vmmcall entry by prefix_table[] escape.
1920 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
1921 (cpu_flags): Add CpuSEV_ES entry.
1922 * i386-opc.h (CpuSEV_ES): New.
1923 (union i386_cpu_flags): Add cpusev_es field.
1924 * i386-opc.tbl (vmgexit): New.
1925 * i386-init.h, i386-tbl.h: Re-generate.
1927 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1929 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
1931 * i386-opc.h (IGNORESIZE): New.
1932 (DEFAULTSIZE): Likewise.
1933 (IgnoreSize): Removed.
1934 (DefaultSize): Likewise.
1935 (MnemonicSize): New.
1936 (i386_opcode_modifier): Replace ignoresize/defaultsize with
1938 * i386-opc.tbl (IgnoreSize): New.
1939 (DefaultSize): Likewise.
1940 * i386-tbl.h: Regenerated.
1942 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1945 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
1948 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1951 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
1952 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
1953 * i386-tbl.h: Regenerated.
1955 2020-02-26 Alan Modra <amodra@gmail.com>
1957 * aarch64-asm.c: Indent labels correctly.
1958 * aarch64-dis.c: Likewise.
1959 * aarch64-gen.c: Likewise.
1960 * aarch64-opc.c: Likewise.
1961 * alpha-dis.c: Likewise.
1962 * i386-dis.c: Likewise.
1963 * nds32-asm.c: Likewise.
1964 * nfp-dis.c: Likewise.
1965 * visium-dis.c: Likewise.
1967 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
1969 * arc-regs.h (int_vector_base): Make it available for all ARC
1972 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
1974 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
1977 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
1979 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
1980 c.mv/c.li if rs1 is zero.
1982 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
1984 * i386-gen.c (cpu_flag_init): Replace CpuABM with
1985 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
1987 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
1988 * i386-opc.h (CpuABM): Removed.
1990 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
1991 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
1992 popcnt. Remove CpuABM from lzcnt.
1993 * i386-init.h: Regenerated.
1994 * i386-tbl.h: Likewise.
1996 2020-02-17 Jan Beulich <jbeulich@suse.com>
1998 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
1999 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2000 VexW1 instead of open-coding them.
2001 * i386-tbl.h: Re-generate.
2003 2020-02-17 Jan Beulich <jbeulich@suse.com>
2005 * i386-opc.tbl (AddrPrefixOpReg): Define.
2006 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2007 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2008 templates. Drop NoRex64.
2009 * i386-tbl.h: Re-generate.
2011 2020-02-17 Jan Beulich <jbeulich@suse.com>
2014 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2015 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2016 into Intel syntax instance (with Unpsecified) and AT&T one
2018 (vcvtneps2bf16): Likewise, along with folding the two so far
2020 * i386-tbl.h: Re-generate.
2022 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2024 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2025 CPU_ANY_SSE4A_FLAGS.
2027 2020-02-17 Alan Modra <amodra@gmail.com>
2029 * i386-gen.c (cpu_flag_init): Correct last change.
2031 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2033 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
2036 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
2038 * i386-opc.tbl (movsx): Remove Intel syntax comments.
2041 2020-02-14 Jan Beulich <jbeulich@suse.com>
2044 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2045 destination for Cpu64-only variant.
2046 (movzx): Fold patterns.
2047 * i386-tbl.h: Re-generate.
2049 2020-02-13 Jan Beulich <jbeulich@suse.com>
2051 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2052 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2053 CPU_ANY_SSE4_FLAGS entry.
2054 * i386-init.h: Re-generate.
2056 2020-02-12 Jan Beulich <jbeulich@suse.com>
2058 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2059 with Unspecified, making the present one AT&T syntax only.
2060 * i386-tbl.h: Re-generate.
2062 2020-02-12 Jan Beulich <jbeulich@suse.com>
2064 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2065 * i386-tbl.h: Re-generate.
2067 2020-02-12 Jan Beulich <jbeulich@suse.com>
2070 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2071 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2072 Amd64 and Intel64 templates.
2073 (call, jmp): Likewise for far indirect variants. Dro
2075 * i386-tbl.h: Re-generate.
2077 2020-02-11 Jan Beulich <jbeulich@suse.com>
2079 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2080 * i386-opc.h (ShortForm): Delete.
2081 (struct i386_opcode_modifier): Remove shortform field.
2082 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2083 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2084 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2085 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2087 * i386-tbl.h: Re-generate.
2089 2020-02-11 Jan Beulich <jbeulich@suse.com>
2091 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2092 fucompi): Drop ShortForm from operand-less templates.
2093 * i386-tbl.h: Re-generate.
2095 2020-02-11 Alan Modra <amodra@gmail.com>
2097 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2098 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2099 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2100 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2101 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2103 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2105 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2106 (cde_opcodes): Add VCX* instructions.
2108 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2109 Matthew Malcomson <matthew.malcomson@arm.com>
2111 * arm-dis.c (struct cdeopcode32): New.
2112 (CDE_OPCODE): New macro.
2113 (cde_opcodes): New disassembly table.
2114 (regnames): New option to table.
2115 (cde_coprocs): New global variable.
2116 (print_insn_cde): New
2117 (print_insn_thumb32): Use print_insn_cde.
2118 (parse_arm_disassembler_options): Parse coprocN args.
2120 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2123 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2125 * i386-opc.h (AMD64): Removed.
2126 (Intel64): Likewose.
2128 (INTEL64): Likewise.
2129 (INTEL64ONLY): Likewise.
2130 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2131 * i386-opc.tbl (Amd64): New.
2132 (Intel64): Likewise.
2133 (Intel64Only): Likewise.
2134 Replace AMD64 with Amd64. Update sysenter/sysenter with
2135 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2136 * i386-tbl.h: Regenerated.
2138 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2141 * z80-dis.c: Add support for GBZ80 opcodes.
2143 2020-02-04 Alan Modra <amodra@gmail.com>
2145 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2147 2020-02-03 Alan Modra <amodra@gmail.com>
2149 * m32c-ibld.c: Regenerate.
2151 2020-02-01 Alan Modra <amodra@gmail.com>
2153 * frv-ibld.c: Regenerate.
2155 2020-01-31 Jan Beulich <jbeulich@suse.com>
2157 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2158 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2159 (OP_E_memory): Replace xmm_mdq_mode case label by
2160 vex_scalar_w_dq_mode one.
2161 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2163 2020-01-31 Jan Beulich <jbeulich@suse.com>
2165 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2166 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2167 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2168 (intel_operand_size): Drop vex_w_dq_mode case label.
2170 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2172 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2173 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2175 2020-01-30 Alan Modra <amodra@gmail.com>
2177 * m32c-ibld.c: Regenerate.
2179 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2181 * bpf-opc.c: Regenerate.
2183 2020-01-30 Jan Beulich <jbeulich@suse.com>
2185 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2186 (dis386): Use them to replace C2/C3 table entries.
2187 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2188 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2189 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2190 * i386-tbl.h: Re-generate.
2192 2020-01-30 Jan Beulich <jbeulich@suse.com>
2194 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2196 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2198 * i386-tbl.h: Re-generate.
2200 2020-01-30 Alan Modra <amodra@gmail.com>
2202 * tic4x-dis.c (tic4x_dp): Make unsigned.
2204 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2205 Jan Beulich <jbeulich@suse.com>
2208 * i386-dis.c (MOVSXD_Fixup): New function.
2209 (movsxd_mode): New enum.
2210 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2211 (intel_operand_size): Handle movsxd_mode.
2212 (OP_E_register): Likewise.
2214 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2215 register on movsxd. Add movsxd with 16-bit destination register
2216 for AMD64 and Intel64 ISAs.
2217 * i386-tbl.h: Regenerated.
2219 2020-01-27 Tamar Christina <tamar.christina@arm.com>
2222 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2223 * aarch64-asm-2.c: Regenerate
2224 * aarch64-dis-2.c: Likewise.
2225 * aarch64-opc-2.c: Likewise.
2227 2020-01-21 Jan Beulich <jbeulich@suse.com>
2229 * i386-opc.tbl (sysret): Drop DefaultSize.
2230 * i386-tbl.h: Re-generate.
2232 2020-01-21 Jan Beulich <jbeulich@suse.com>
2234 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2236 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2237 * i386-tbl.h: Re-generate.
2239 2020-01-20 Nick Clifton <nickc@redhat.com>
2241 * po/de.po: Updated German translation.
2242 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2243 * po/uk.po: Updated Ukranian translation.
2245 2020-01-20 Alan Modra <amodra@gmail.com>
2247 * hppa-dis.c (fput_const): Remove useless cast.
2249 2020-01-20 Alan Modra <amodra@gmail.com>
2251 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2253 2020-01-18 Nick Clifton <nickc@redhat.com>
2255 * configure: Regenerate.
2256 * po/opcodes.pot: Regenerate.
2258 2020-01-18 Nick Clifton <nickc@redhat.com>
2260 Binutils 2.34 branch created.
2262 2020-01-17 Christian Biesinger <cbiesinger@google.com>
2264 * opintl.h: Fix spelling error (seperate).
2266 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2268 * i386-opc.tbl: Add {vex} pseudo prefix.
2269 * i386-tbl.h: Regenerated.
2271 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2274 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2275 (neon_opcodes): Likewise.
2276 (select_arm_features): Make sure we enable MVE bits when selecting
2277 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2280 2020-01-16 Jan Beulich <jbeulich@suse.com>
2282 * i386-opc.tbl: Drop stale comment from XOP section.
2284 2020-01-16 Jan Beulich <jbeulich@suse.com>
2286 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2287 (extractps): Add VexWIG to SSE2AVX forms.
2288 * i386-tbl.h: Re-generate.
2290 2020-01-16 Jan Beulich <jbeulich@suse.com>
2292 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2293 Size64 from and use VexW1 on SSE2AVX forms.
2294 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2295 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2296 * i386-tbl.h: Re-generate.
2298 2020-01-15 Alan Modra <amodra@gmail.com>
2300 * tic4x-dis.c (tic4x_version): Make unsigned long.
2301 (optab, optab_special, registernames): New file scope vars.
2302 (tic4x_print_register): Set up registernames rather than
2303 malloc'd registertable.
2304 (tic4x_disassemble): Delete optable and optable_special. Use
2305 optab and optab_special instead. Throw away old optab,
2306 optab_special and registernames when info->mach changes.
2308 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2311 * z80-dis.c (suffix): Use .db instruction to generate double
2314 2020-01-14 Alan Modra <amodra@gmail.com>
2316 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2317 values to unsigned before shifting.
2319 2020-01-13 Thomas Troeger <tstroege@gmx.de>
2321 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2323 (print_insn_thumb16, print_insn_thumb32): Likewise.
2324 (print_insn): Initialize the insn info.
2325 * i386-dis.c (print_insn): Initialize the insn info fields, and
2328 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2330 * arc-opc.c (C_NE): Make it required.
2332 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2334 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2335 reserved register name.
2337 2020-01-13 Alan Modra <amodra@gmail.com>
2339 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2340 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2342 2020-01-13 Alan Modra <amodra@gmail.com>
2344 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2345 result of wasm_read_leb128 in a uint64_t and check that bits
2346 are not lost when copying to other locals. Use uint32_t for
2347 most locals. Use PRId64 when printing int64_t.
2349 2020-01-13 Alan Modra <amodra@gmail.com>
2351 * score-dis.c: Formatting.
2352 * score7-dis.c: Formatting.
2354 2020-01-13 Alan Modra <amodra@gmail.com>
2356 * score-dis.c (print_insn_score48): Use unsigned variables for
2357 unsigned values. Don't left shift negative values.
2358 (print_insn_score32): Likewise.
2359 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2361 2020-01-13 Alan Modra <amodra@gmail.com>
2363 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2365 2020-01-13 Alan Modra <amodra@gmail.com>
2367 * fr30-ibld.c: Regenerate.
2369 2020-01-13 Alan Modra <amodra@gmail.com>
2371 * xgate-dis.c (print_insn): Don't left shift signed value.
2372 (ripBits): Formatting, use 1u.
2374 2020-01-10 Alan Modra <amodra@gmail.com>
2376 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2377 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2379 2020-01-10 Alan Modra <amodra@gmail.com>
2381 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2382 and XRREG value earlier to avoid a shift with negative exponent.
2383 * m10200-dis.c (disassemble): Similarly.
2385 2020-01-09 Nick Clifton <nickc@redhat.com>
2388 * z80-dis.c (ld_ii_ii): Use correct cast.
2390 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2393 * z80-dis.c (ld_ii_ii): Use character constant when checking
2396 2020-01-09 Jan Beulich <jbeulich@suse.com>
2398 * i386-dis.c (SEP_Fixup): New.
2400 (dis386_twobyte): Use it for sysenter/sysexit.
2401 (enum x86_64_isa): Change amd64 enumerator to value 1.
2402 (OP_J): Compare isa64 against intel64 instead of amd64.
2403 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
2405 * i386-tbl.h: Re-generate.
2407 2020-01-08 Alan Modra <amodra@gmail.com>
2409 * z8k-dis.c: Include libiberty.h
2410 (instr_data_s): Make max_fetched unsigned.
2411 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
2412 Don't exceed byte_info bounds.
2413 (output_instr): Make num_bytes unsigned.
2414 (unpack_instr): Likewise for nibl_count and loop.
2415 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
2417 * z8k-opc.h: Regenerate.
2419 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
2421 * arc-tbl.h (llock): Use 'LLOCK' as class.
2423 (scond): Use 'SCOND' as class.
2425 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
2428 2020-01-06 Alan Modra <amodra@gmail.com>
2430 * m32c-ibld.c: Regenerate.
2432 2020-01-06 Alan Modra <amodra@gmail.com>
2435 * z80-dis.c (suffix): Don't use a local struct buffer copy.
2436 Peek at next byte to prevent recursion on repeated prefix bytes.
2437 Ensure uninitialised "mybuf" is not accessed.
2438 (print_insn_z80): Don't zero n_fetch and n_used here,..
2439 (print_insn_z80_buf): ..do it here instead.
2441 2020-01-04 Alan Modra <amodra@gmail.com>
2443 * m32r-ibld.c: Regenerate.
2445 2020-01-04 Alan Modra <amodra@gmail.com>
2447 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2449 2020-01-04 Alan Modra <amodra@gmail.com>
2451 * crx-dis.c (match_opcode): Avoid shift left of signed value.
2453 2020-01-04 Alan Modra <amodra@gmail.com>
2455 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2457 2020-01-03 Jan Beulich <jbeulich@suse.com>
2459 * aarch64-tbl.h (aarch64_opcode_table): Use
2460 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2462 2020-01-03 Jan Beulich <jbeulich@suse.com>
2464 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
2465 forms of SUDOT and USDOT.
2467 2020-01-03 Jan Beulich <jbeulich@suse.com>
2469 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
2471 * opcodes/aarch64-dis-2.c: Re-generate.
2473 2020-01-03 Jan Beulich <jbeulich@suse.com>
2475 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
2477 * opcodes/aarch64-dis-2.c: Re-generate.
2479 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
2481 * z80-dis.c: Add support for eZ80 and Z80 instructions.
2483 2020-01-01 Alan Modra <amodra@gmail.com>
2485 Update year range in copyright notice of all files.
2487 For older changes see ChangeLog-2019
2489 Copyright (C) 2020 Free Software Foundation, Inc.
2491 Copying and distribution of this file, with or without modification,
2492 are permitted in any medium without royalty provided the copyright
2493 notice and this notice are preserved.
2499 version-control: never
projects / binutils-gdb.git / blob