opcodes/ChangeLog

   1 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386-opc.tbl: Use CpuCET on rdsspq.
   4         * i386-tbl.h: Regenerated.
   5
   6 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
   7
   8         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
   9         <vsx>: Do not use PPC_OPCODE_VSX3;
  10
  11 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
  12
  13         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
  14
  15 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
  16
  17         * i386-dis.c (REG_0F1E_MOD_3): New enum.
  18         (MOD_0F1E_PREFIX_1): Likewise.
  19         (MOD_0F38F5_PREFIX_2): Likewise.
  20         (MOD_0F38F6_PREFIX_0): Likewise.
  21         (RM_0F1E_MOD_3_REG_7): Likewise.
  22         (PREFIX_MOD_0_0F01_REG_5): Likewise.
  23         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
  24         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
  25         (PREFIX_0F1E): Likewise.
  26         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
  27         (PREFIX_0F38F5): Likewise.
  28         (dis386_twobyte): Use PREFIX_0F1E.
  29         (reg_table): Add REG_0F1E_MOD_3.
  30         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
  31         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
  32         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
  33         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
  34         (three_byte_table): Use PREFIX_0F38F5.
  35         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
  36         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
  37         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
  38         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
  39         PREFIX_MOD_3_0F01_REG_5_RM_2.
  40         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
  41         (cpu_flags): Add CpuCET.
  42         * i386-opc.h (CpuCET): New enum.
  43         (CpuUnused): Commented out.
  44         (i386_cpu_flags): Add cpucet.
  45         * i386-opc.tbl: Add Intel CET instructions.
  46         * i386-init.h: Regenerated.
  47         * i386-tbl.h: Likewise.
  48
  49 2017-03-06  Alan Modra  <amodra@gmail.com>
  50
  51         PR 21124
  52         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
  53         (extract_raq, extract_ras, extract_rbx): New functions.
  54         (powerpc_operands): Use opposite corresponding insert function.
  55         (Q_MASK): Define.
  56         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
  57         register restriction.
  58
  59 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
  60
  61         * disassemble.c Include "safe-ctype.h".
  62         (disassemble_init_for_target): Handle s390 init.
  63         (remove_whitespace_and_extra_commas): New function.
  64         (disassembler_options_cmp): Likewise.
  65         * arm-dis.c: Include "libiberty.h".
  66         (NUM_ELEM): Delete.
  67         (regnames): Use long disassembler style names.
  68         Add force-thumb and no-force-thumb options.
  69         (NUM_ARM_REGNAMES): Rename from this...
  70         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
  71         (get_arm_regname_num_options): Delete.
  72         (set_arm_regname_option): Likewise.
  73         (get_arm_regnames): Likewise.
  74         (parse_disassembler_options): Likewise.
  75         (parse_arm_disassembler_option): Rename from this...
  76         (parse_arm_disassembler_options): ...to this.  Make static.
  77         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
  78         (print_insn): Use parse_arm_disassembler_options.
  79         (disassembler_options_arm): New function.
  80         (print_arm_disassembler_options): Handle updated regnames.
  81         * ppc-dis.c: Include "libiberty.h".
  82         (ppc_opts): Add "32" and "64" entries.
  83         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
  84         (powerpc_init_dialect): Add break to switch statement.
  85         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
  86         (disassembler_options_powerpc): New function.
  87         (print_ppc_disassembler_options): Use ARRAY_SIZE.
  88         Remove printing of "32" and "64".
  89         * s390-dis.c: Include "libiberty.h".
  90         (init_flag): Remove unneeded variable.
  91         (struct s390_options_t): New structure type.
  92         (options): New structure.
  93         (init_disasm): Rename from this...
  94         (disassemble_init_s390): ...to this.  Add initializations for
  95         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
  96         (print_insn_s390): Delete call to init_disasm.
  97         (disassembler_options_s390): New function.
  98         (print_s390_disassembler_options): Print using information from
  99         struct 'options'.
 100         * po/opcodes.pot: Regenerate.
 101
 102 2017-02-28  Jan Beulich  <jbeulich@suse.com>
 103
 104         * i386-dis.c (PCMPESTR_Fixup): New.
 105         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
 106         (prefix_table): Use PCMPESTR_Fixup.
 107         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
 108         PCMPESTR_Fixup.
 109         (vex_w_table): Delete VPCMPESTR{I,M} entries.
 110         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
 111         Split 64-bit and non-64-bit variants.
 112         * opcodes/i386-tbl.h: Re-generate.
 113
 114 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 115
 116         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
 117         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
 118         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
 119         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
 120         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
 121         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
 122         (OP_SVE_V_HSD): New macros.
 123         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
 124         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
 125         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
 126         (aarch64_opcode_table): Add new SVE instructions.
 127         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
 128         for rotation operands.  Add new SVE operands.
 129         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
 130         (ins_sve_quad_index): Likewise.
 131         (ins_imm_rotate): Split into...
 132         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
 133         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
 134         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
 135         functions.
 136         (aarch64_ins_sve_addr_ri_s4): New function.
 137         (aarch64_ins_sve_quad_index): Likewise.
 138         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
 139         * aarch64-asm-2.c: Regenerate.
 140         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
 141         (ext_sve_quad_index): Likewise.
 142         (ext_imm_rotate): Split into...
 143         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
 144         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
 145         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
 146         functions.
 147         (aarch64_ext_sve_addr_ri_s4): New function.
 148         (aarch64_ext_sve_quad_index): Likewise.
 149         (aarch64_ext_sve_index): Allow quad indices.
 150         (do_misc_decoding): Likewise.
 151         * aarch64-dis-2.c: Regenerate.
 152         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
 153         aarch64_field_kinds.
 154         (OPD_F_OD_MASK): Widen by one bit.
 155         (OPD_F_NO_ZR): Bump accordingly.
 156         (get_operand_field_width): New function.
 157         * aarch64-opc.c (fields): Add new SVE fields.
 158         (operand_general_constraint_met_p): Handle new SVE operands.
 159         (aarch64_print_operand): Likewise.
 160         * aarch64-opc-2.c: Regenerate.
 161
 162 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 163
 164         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
 165         (aarch64_feature_compnum): ...this.
 166         (SIMD_V8_3): Replace with...
 167         (COMPNUM): ...this.
 168         (CNUM_INSN): New macro.
 169         (aarch64_opcode_table): Use it for the complex number instructions.
 170
 171 2017-02-24  Jan Beulich  <jbeulich@suse.com>
 172
 173         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
 174
 175 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
 176
 177         Add support for associating SPARC ASIs with an architecture level.
 178         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
 179         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
 180         decoding of SPARC ASIs.
 181
 182 2017-02-23  Jan Beulich  <jbeulich@suse.com>
 183
 184         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
 185         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
 186
 187 2017-02-21  Jan Beulich  <jbeulich@suse.com>
 188
 189         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
 190         1 (instead of to itself). Correct typo.
 191
 192 2017-02-14  Andrew Waterman  <andrew@sifive.com>
 193
 194         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
 195         pseudoinstructions.
 196
 197 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
 198
 199         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
 200         (aarch64_sys_reg_supported_p): Handle them.
 201
 202 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
 203
 204         * arc-opc.c (UIMM6_20R): Define.
 205         (SIMM12_20): Use above.
 206         (SIMM12_20R): Define.
 207         (SIMM3_5_S): Use above.
 208         (UIMM7_A32_11R_S): Define.
 209         (UIMM7_9_S): Use above.
 210         (UIMM3_13R_S): Define.
 211         (SIMM11_A32_7_S): Use above.
 212         (SIMM9_8R): Define.
 213         (UIMM10_A32_8_S): Use above.
 214         (UIMM8_8R_S): Define.
 215         (W6): Use above.
 216         (arc_relax_opcodes): Use all above defines.
 217
 218 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
 219
 220         * arc-regs.h: Distinguish some of the registers different on
 221         ARC700 and HS38 cpus.
 222
 223 2017-02-14  Alan Modra  <amodra@gmail.com>
 224
 225         PR 21118
 226         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
 227         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
 228
 229 2017-02-11  Stafford Horne  <shorne@gmail.com>
 230             Alan Modra  <amodra@gmail.com>
 231
 232         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
 233         Use insn_bytes_value and insn_int_value directly instead.  Don't
 234         free allocated memory until function exit.
 235
 236 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
 237
 238         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
 239
 240 2017-02-03  Nick Clifton  <nickc@redhat.com>
 241
 242         PR 21096
 243         * aarch64-opc.c (print_register_list): Ensure that the register
 244         list index will fir into the tb buffer.
 245         (print_register_offset_address): Likewise.
 246         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
 247
 248 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
 249
 250         PR 21056
 251         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
 252         instructions when the previous fetch packet ends with a 32-bit
 253         instruction.
 254
 255 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
 256
 257         * pru-opc.c: Remove vague reference to a future GDB port.
 258
 259 2017-01-20  Nick Clifton  <nickc@redhat.com>
 260
 261         * po/ga.po: Updated Irish translation.
 262
 263 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 264
 265         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
 266
 267 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 268
 269         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
 270         if FETCH_DATA returns 0.
 271         (m68k_scan_mask): Likewise.
 272         (print_insn_m68k): Update code to handle -1 return value.
 273
 274 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 275
 276         * m68k-dis.c (enum print_insn_arg_error): New.
 277         (NEXTBYTE): Replace -3 with
 278         PRINT_INSN_ARG_MEMORY_ERROR.
 279         (NEXTULONG): Likewise.
 280         (NEXTSINGLE): Likewise.
 281         (NEXTDOUBLE): Likewise.
 282         (NEXTDOUBLE): Likewise.
 283         (NEXTPACKED): Likewise.
 284         (FETCH_ARG): Likewise.
 285         (FETCH_DATA): Update comments.
 286         (print_insn_arg): Update comments. Replace magic numbers with
 287         enum.
 288         (match_insn_m68k): Likewise.
 289
 290 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 291
 292         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
 293         * i386-dis-evex.h (evex_table): Updated.
 294         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
 295         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 296         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
 297         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
 298         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
 299         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
 300         * i386-init.h: Regenerate.
 301         * i386-tbl.h: Ditto.
 302
 303 2017-01-12  Yao Qi  <yao.qi@linaro.org>
 304
 305         * msp430-dis.c (msp430_singleoperand): Return -1 if
 306         msp430dis_opcode_signed returns false.
 307         (msp430_doubleoperand): Likewise.
 308         (msp430_branchinstr): Return -1 if
 309         msp430dis_opcode_unsigned returns false.
 310         (msp430x_calla_instr): Likewise.
 311         (print_insn_msp430): Likewise.
 312
 313 2017-01-05  Nick Clifton  <nickc@redhat.com>
 314
 315         PR 20946
 316         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
 317         could not be matched.
 318         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
 319         NULL.
 320
 321 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 322
 323         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
 324         (aarch64_opcode_table): Use RCPC_INSN.
 325
 326 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
 327
 328         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
 329         extension.
 330         * riscv-opcodes/all-opcodes: Likewise.
 331
 332 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
 333
 334         * riscv-dis.c (print_insn_args): Add fall through comment.
 335
 336 2017-01-03  Nick Clifton  <nickc@redhat.com>
 337
 338         * po/sr.po: New Serbian translation.
 339         * configure.ac (ALL_LINGUAS): Add sr.
 340         * configure: Regenerate.
 341
 342 2017-01-02  Alan Modra  <amodra@gmail.com>
 343
 344         * epiphany-desc.h: Regenerate.
 345         * epiphany-opc.h: Regenerate.
 346         * fr30-desc.h: Regenerate.
 347         * fr30-opc.h: Regenerate.
 348         * frv-desc.h: Regenerate.
 349         * frv-opc.h: Regenerate.
 350         * ip2k-desc.h: Regenerate.
 351         * ip2k-opc.h: Regenerate.
 352         * iq2000-desc.h: Regenerate.
 353         * iq2000-opc.h: Regenerate.
 354         * lm32-desc.h: Regenerate.
 355         * lm32-opc.h: Regenerate.
 356         * m32c-desc.h: Regenerate.
 357         * m32c-opc.h: Regenerate.
 358         * m32r-desc.h: Regenerate.
 359         * m32r-opc.h: Regenerate.
 360         * mep-desc.h: Regenerate.
 361         * mep-opc.h: Regenerate.
 362         * mt-desc.h: Regenerate.
 363         * mt-opc.h: Regenerate.
 364         * or1k-desc.h: Regenerate.
 365         * or1k-opc.h: Regenerate.
 366         * xc16x-desc.h: Regenerate.
 367         * xc16x-opc.h: Regenerate.
 368         * xstormy16-desc.h: Regenerate.
 369         * xstormy16-opc.h: Regenerate.
 370
 371 2017-01-02  Alan Modra  <amodra@gmail.com>
 372
 373         Update year range in copyright notice of all files.
 374
 375 For older changes see ChangeLog-2016
 376 \f
 377 Copyright (C) 2017 Free Software Foundation, Inc.
 378
 379 Copying and distribution of this file, with or without modification,
 380 are permitted in any medium without royalty provided the copyright
 381 notice and this notice are preserved.
 382
 383 Local Variables:
 384 mode: change-log
 385 left-margin: 8
 386 fill-column: 74
 387 version-control: never
 388 End: