opcodes/ChangeLog

   1 2015-10-27  Vinay  <Vinay.G@kpit.com>
   2
   3         PR binutils/19159
   4         * rl78-decode.opc (MOV): Added offset to DE register in index
   5         addressing mode.
   6         * rl78-decode.c: Regenerate.
   7
   8 2015-10-27  Vinay Kumar  <vinay.g@kpit.com>
   9
  10         PR binutils/19158
  11         * rl78-decode.opc: Add 's' print operator to instructions that
  12         access system registers.
  13         * rl78-decode.c: Regenerate.
  14         * rl78-dis.c (print_insn_rl78_common): Decode all system
  15         registers.
  16
  17 2015-10-27  Vinay Kumar  <vinay.g@kpit.com>
  18
  19         PR binutils/19157
  20         * rl78-decode.opc: Add 'a' print operator to mov instructions
  21         using stack pointer plus index addressing.
  22         * rl78-decode.c: Regenerate.
  23
  24 2015-10-14  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
  25
  26         * s390-opc.c: Fix comment.
  27         * s390-opc.txt: Change instruction type for troo, trot, trto, and
  28         trtt to RRF_U0RER since the second parameter does not need to be a
  29         register pair.
  30
  31 2015-10-08  Nick Clifton  <nickc@redhat.com>
  32
  33         * arc-dis.c (print_insn_arc): Initiallise insn array.
  34
  35 2015-10-07  Yao Qi  <yao.qi@linaro.org>
  36
  37         * aarch64-dis.c (aarch64_ext_sysins_op): Access field
  38         'name' rather than 'template'.
  39         * aarch64-opc.c (aarch64_print_operand): Likewise.
  40
  41 2015-10-07  Claudiu Zissulescu <claziss@synopsys.com>
  42
  43         * arc-dis.c: Revamped file for ARC support
  44         * arc-dis.h: Likewise.
  45         * arc-ext.c: Likewise.
  46         * arc-ext.h: Likewise.
  47         * arc-opc.c: Likewise.
  48         * arc-fxi.h: New file.
  49         * arc-regs.h: Likewise.
  50         * arc-tbl.h: Likewise.
  51
  52 2015-10-02  Yao Qi  <yao.qi@linaro.org>
  53
  54         * aarch64-dis.c (disas_aarch64_insn): Remove static.  Change
  55         argument insn type to aarch64_insn.  Rename to ...
  56         (aarch64_decode_insn): ... it.
  57         (print_insn_aarch64_word): Caller updated.
  58
  59 2015-10-02  Yao Qi  <yao.qi@linaro.org>
  60
  61         * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
  62         (print_insn_aarch64_word): Caller updated.
  63
  64 2015-09-29  Dominik Vogt  <vogt@linux.vnet.ibm.com>
  65
  66         * s390-mkopc.c (main): Parse htm and vx flag.
  67         * s390-opc.txt: Mark instructions from the hardware transactional
  68         memory and vector facilities with the "htm"/"vx" flag.
  69
  70 2015-09-28  Nick Clifton  <nickc@redhat.com>
  71
  72         * po/de.po: Updated German translation.
  73
  74 2015-09-28  Tom Rix  <tom@bumblecow.com>
  75
  76         * ppc-opc.c (PPC500): Mark some opcodes as invalid
  77
  78 2015-09-23  Nick Clifton  <nickc@redhat.com>
  79
  80         * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
  81         function.
  82         * tic30-dis.c (print_branch): Likewise.
  83         * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
  84         value before left shifting.
  85         * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
  86         * hppa-dis.c (print_insn_hppa): Likewise.
  87         * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
  88         array.
  89         * msp430-dis.c (msp430_singleoperand): Likewise.
  90         (msp430_doubleoperand): Likewise.
  91         (print_insn_msp430): Likewise.
  92         * nds32-asm.c (parse_operand): Likewise.
  93         * sh-opc.h (MASK): Likewise.
  94         * v850-dis.c (get_operand_value): Likewise.
  95
  96 2015-09-22  Nick Clifton  <nickc@redhat.com>
  97
  98         * rx-decode.opc (bwl): Use RX_Bad_Size.
  99         (sbwl): Likewise.
 100         (ubwl): Likewise.  Rename to ubw.
 101         (uBWL): Rename to uBW.
 102         Replace all references to uBWL with uBW.
 103         * rx-decode.c: Regenerate.
 104         * rx-dis.c (size_names): Add entry for RX_Bad_Size.
 105         (opsize_names): Likewise.
 106         (print_insn_rx): Detect and report RX_Bad_Size.
 107
 108 2015-09-22  Anton Blanchard  <anton@samba.org>
 109
 110         * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
 111
 112 2015-08-25  Jose E. Marchesi  <jose.marchesi@oracle.com>
 113
 114         * sparc-dis.c (print_insn_sparc): Handle the privileged register
 115         %pmcdper.
 116
 117 2015-08-24  Jan Stancek  <jstancek@redhat.com>
 118
 119         * i386-dis.c (print_insn): Fix decoding of three byte operands.
 120
 121 2015-08-21  Alexander Fomin  <alexander.fomin@intel.com>
 122
 123         PR binutils/18257
 124         * i386-dis.c: Use MOD_TABLE for most of mask instructions.
 125         (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
 126         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 127         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 128         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 129         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 130         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 131         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 132         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 133         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 134         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 135         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 136         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 137         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 138         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 139         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 140         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 141         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 142         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 143         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 144         MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
 145         MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
 146         MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
 147         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 148         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 149         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 150         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 151         MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 152         MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 153         MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 154         MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
 155         (vex_w_table): Replace terminals with MOD_TABLE entries for
 156         most of mask instructions.
 157
 158 2015-08-17  Alan Modra  <amodra@gmail.com>
 159
 160         * cgen.sh: Trim trailing space from cgen output.
 161         * ia64-gen.c (print_dependency_table): Don't generate trailing space.
 162         (print_dis_table): Likewise.
 163         * opc2c.c (dump_lines): Likewise.
 164         (orig_filename): Warning fix.
 165         * ia64-asmtab.c: Regenerate.
 166
 167 2015-08-13  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 168
 169         * arm-dis.c (print_insn_arm): Disassembling for all targets V6
 170         and higher with ARM instruction set will now mark the 26-bit
 171         versions of teq,tst,cmn and cmp as UNPREDICTABLE.
 172         (arm_opcodes): Fix for unpredictable nop being recognized as a
 173         teq.
 174
 175 2015-08-12  Simon Dardis  <simon.dardis@imgtec.com>
 176
 177         * micromips-opc.c (micromips_opcodes): Re-order table so that move
 178         based on 'or' is first.
 179         * mips-opc.c (mips_builtin_opcodes): Ditto.
 180
 181 2015-08-11  Nick Clifton  <nickc@redhat.com>
 182
 183         PR 18800
 184         * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
 185         instruction.
 186
 187 2015-08-10  Robert Suchanek  <robert.suchanek@imgtec.com>
 188
 189         * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
 190
 191 2015-08-07  Amit Pawar <Amit.Pawar@amd.com>
 192
 193         * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
 194         * i386-init.h: Regenerated.
 195
 196 2015-07-30  H.J. Lu  <hongjiu.lu@intel.com>
 197
 198         PR binutils/13571
 199         * i386-dis.c (MOD_0FC3): New.
 200         (PREFIX_0FC3): Renamed to ...
 201         (PREFIX_MOD_0_0FC3): This.
 202         (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
 203         (prefix_table): Replace Ma with Ev on movntiS.
 204         (mod_table): Add MOD_0FC3.
 205
 206 2015-07-27  H.J. Lu  <hongjiu.lu@intel.com>
 207
 208         * configure: Regenerated.
 209
 210 2015-07-23  Alan Modra  <amodra@gmail.com>
 211
 212         PR 18708
 213         * i386-dis.c (get64): Avoid signed integer overflow.
 214
 215 2015-07-22  Alexander Fomin  <alexander.fomin@intel.com>
 216
 217         PR binutils/18631
 218         * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
 219         "EXEvexHalfBcstXmmq" for the second operand.
 220         (EVEX_W_0F79_P_2): Likewise.
 221         (EVEX_W_0F7A_P_2): Likewise.
 222         (EVEX_W_0F7B_P_2): Likewise.
 223
 224 2015-07-16  Alessandro Marzocchi  <alessandro.marzocchi@gmail.com>
 225
 226         * arm-dis.c (print_insn_coprocessor): Added support for quarter
 227         float bitfield format.
 228         (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
 229         quarter float bitfield format.
 230
 231 2015-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 232
 233         * configure: Regenerated.
 234
 235 2015-07-03  Alan Modra  <amodra@gmail.com>
 236
 237         * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
 238         * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries.  Add
 239         PPC_OPCODE_7450 to 7450 entry.  Add PPC_OPCODE_750 to 750cl entry.
 240
 241 2015-07-01  Sandra Loosemore  <sandra@codesourcery.com>
 242             Cesar Philippidis  <cesar@codesourcery.com>
 243
 244         * nios2-dis.c (nios2_extract_opcode): New.
 245         (nios2_disassembler_state): New.
 246         (nios2_find_opcode_hash): Use mach parameter to select correct
 247         disassembler state.
 248         (nios2_print_insn_arg): Extend to support new R2 argument letters
 249         and formats.
 250         (print_insn_nios2): Check for 16-bit instruction at end of memory.
 251         * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
 252         (NIOS2_NUM_OPCODES): Rename to...
 253         (NIOS2_NUM_R1_OPCODES): This.
 254         (nios2_r2_opcodes): New.
 255         (NIOS2_NUM_R2_OPCODES): New.
 256         (nios2_num_r2_opcodes): New.
 257         (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
 258         (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
 259         (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
 260         (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
 261         (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
 262
 263 2015-06-30  Amit Pawar  <Amit.Pawar@amd.com>
 264
 265         * i386-dis.c (OP_Mwaitx): New.
 266         (rm_table): Add monitorx/mwaitx.
 267         * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
 268         and CPU_ZNVER1_FLAGS.  Add CPU_MWAITX_FLAGS.
 269         (operand_type_init): Add CpuMWAITX.
 270         * i386-opc.h (CpuMWAITX): New.
 271         (i386_cpu_flags): Add cpumwaitx.
 272         * i386-opc.tbl: Add monitorx and mwaitx.
 273         * i386-init.h: Regenerated.
 274         * i386-tbl.h: Likewise.
 275
 276 2015-06-22  Peter Bergner  <bergner@vnet.ibm.com>
 277
 278         * ppc-opc.c (insert_ls): Test for invalid LS operands.
 279         (insert_esync): New function.
 280         (LS, WC): Use insert_ls.
 281         (ESYNC): Use insert_esync.
 282
 283 2015-06-22  Nick Clifton  <nickc@redhat.com>
 284
 285         * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
 286         requested region lies beyond it.
 287         * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
 288         looking for 32-bit insns.
 289         * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
 290         data.
 291         * sh-dis.c (print_insn_sh): Likewise.
 292         * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
 293         blocks of instructions.
 294         * vax-dis.c (print_insn_vax): Check that the requested address
 295         does not clash with the stop_vma.
 296
 297 2015-06-19  Peter Bergner  <bergner@vnet.ibm.com>
 298
 299         * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
 300         * ppc-opc.c (FXM4): Add non-zero optional value.
 301         (TBR): Likewise.
 302         (SXL): Likewise.
 303         (insert_fxm): Handle new default operand value.
 304         (extract_fxm): Likewise.
 305         (insert_tbr): Likewise.
 306         (extract_tbr): Likewise.
 307
 308 2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
 309
 310         * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
 311
 312 2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 313
 314         * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
 315
 316 2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>
 317
 318         * ppc-opc.c: Add comment accidentally removed by old commit.
 319         (MTMSRD_L): Delete.
 320
 321 2015-06-04  Peter Bergner  <bergner@vnet.ibm.com>
 322
 323         * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
 324
 325 2015-06-04  Nick Clifton  <nickc@redhat.com>
 326
 327         PR 18474
 328         * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
 329
 330 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 331
 332         * arm-dis.c (arm_opcodes): Add "setpan".
 333         (thumb_opcodes): Add "setpan".
 334
 335 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 336
 337         * arm-dis.c (select_arm_features): Rework to avoid used of redefined
 338         macros.
 339
 340 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 341
 342         * aarch64-tbl.h (aarch64_feature_rdma): New.
 343         (RDMA): New.
 344         (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
 345         * aarch64-asm-2.c: Regenerate.
 346         * aarch64-dis-2.c: Regenerate.
 347         * aarch64-opc-2.c: Regenerate.
 348
 349 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 350
 351         * aarch64-tbl.h (aarch64_feature_lor): New.
 352         (LOR): New.
 353         (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
 354         "stllrb", "stllrh".
 355         * aarch64-asm-2.c: Regenerate.
 356         * aarch64-dis-2.c: Regenerate.
 357         * aarch64-opc-2.c: Regenerate.
 358
 359 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
 360
 361         * aarch64-opc.c (F_ARCHEXT): New.
 362         (aarch64_sys_regs): Add "pan".
 363         (aarch64_sys_reg_supported_p): New.
 364         (aarch64_pstatefields): Add "pan".
 365         (aarch64_pstatefield_supported_p): New.
 366
 367 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 368
 369         * i386-tbl.h: Regenerate.
 370
 371 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 372
 373         * i386-dis.c (print_insn): Swap rounding mode specifier and
 374         general purpose register in Intel mode.
 375
 376 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 377
 378         * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
 379         * i386-tbl.h: Regenerate.
 380
 381 2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
 382
 383         * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
 384         * i386-init.h: Regenerated.
 385
 386 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 387
 388         PR binutis/18386
 389         * i386-dis.c: Add comments for '@'.
 390         (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
 391         (enum x86_64_isa): New.
 392         (isa64): Likewise.
 393         (print_i386_disassembler_options): Add amd64 and intel64.
 394         (print_insn): Handle amd64 and intel64.
 395         (putop): Handle '@'.
 396         (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
 397         * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
 398         * i386-opc.h (AMD64): New.
 399         (CpuIntel64): Likewise.
 400         (i386_cpu_flags): Add cpuamd64 and cpuintel64.
 401         * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
 402         Mark direct call/jmp without Disp16|Disp32 as Intel64.
 403         * i386-init.h: Regenerated.
 404         * i386-tbl.h: Likewise.
 405
 406 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
 407
 408         * ppc-opc.c (IH) New define.
 409         (powerpc_opcodes) <wait>: Do not enable for POWER7.
 410         <tlbie>: Add RS operand for POWER7.
 411         <slbia>: Add IH operand for POWER6.
 412
 413 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 414
 415         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
 416         direct branch.
 417         (jmp): Likewise.
 418         * i386-tbl.h: Regenerated.
 419
 420 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 421
 422         * configure.ac: Support bfd_iamcu_arch.
 423         * disassemble.c (disassembler): Support bfd_iamcu_arch.
 424         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
 425         CPU_IAMCU_COMPAT_FLAGS.
 426         (cpu_flags): Add CpuIAMCU.
 427         * i386-opc.h (CpuIAMCU): New.
 428         (i386_cpu_flags): Add cpuiamcu.
 429         * configure: Regenerated.
 430         * i386-init.h: Likewise.
 431         * i386-tbl.h: Likewise.
 432
 433 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
 434
 435         PR binutis/18386
 436         * i386-dis.c (X86_64_E8): New.
 437         (X86_64_E9): Likewise.
 438         Update comments on 'T', 'U', 'V'.  Add comments for '^'.
 439         (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
 440         (x86_64_table): Add X86_64_E8 and X86_64_E9.
 441         (mod_table): Replace {T|} with ^ on Jcall/Jmp.
 442         (putop): Handle '^'.
 443         (OP_J): Ignore the operand size prefix in 64-bit.  Don't check
 444         REX_W.
 445
 446 2015-04-30  DJ Delorie  <dj@redhat.com>
 447
 448         * disassemble.c (disassembler): Choose suitable disassembler based
 449         on E_ABI.
 450         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
 451         it to decode mul/div insns.
 452         * rl78-decode.c: Regenerate.
 453         * rl78-dis.c (print_insn_rl78): Rename to...
 454         (print_insn_rl78_common): ...this, take ISA parameter.
 455         (print_insn_rl78): New.
 456         (print_insn_rl78_g10): New.
 457         (print_insn_rl78_g13): New.
 458         (print_insn_rl78_g14): New.
 459         (rl78_get_disassembler): New.
 460
 461 2015-04-29  Nick Clifton  <nickc@redhat.com>
 462
 463         * po/fr.po: Updated French translation.
 464
 465 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
 466
 467         * ppc-opc.c (DCBT_EO): New define.
 468         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
 469         <lharx>: Likewise.
 470         <stbcx.>: Likewise.
 471         <sthcx.>: Likewise.
 472         <waitrsv>: Do not enable for POWER7 and later.
 473         <waitimpl>: Likewise.
 474         <dcbt>: Default to the two operand form of the instruction for all
 475         "old" cpus.  For "new" cpus, use the operand ordering that matches
 476         whether the cpu is server or embedded.
 477         <dcbtst>: Likewise.
 478
 479 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 480
 481         * s390-opc.c: New instruction type VV0UU2.
 482         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
 483         and WFC.
 484
 485 2015-04-23  Jan Beulich  <jbeulich@suse.com>
 486
 487         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
 488         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
 489         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
 490         (vfpclasspd, vfpclassps): Add %XZ.
 491
 492 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 493
 494         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
 495         (PREFIX_UD_REPZ): Likewise.
 496         (PREFIX_UD_REPNZ): Likewise.
 497         (PREFIX_UD_DATA): Likewise.
 498         (PREFIX_UD_ADDR): Likewise.
 499         (PREFIX_UD_LOCK): Likewise.
 500
 501 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 502
 503         * i386-dis.c (prefix_requirement): Removed.
 504         (print_insn): Don't set prefix_requirement.  Check
 505         dp->prefix_requirement instead of prefix_requirement.
 506
 507 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 508
 509         PR binutils/17898
 510         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
 511         (PREFIX_MOD_0_0FC7_REG_6): This.
 512         (PREFIX_MOD_3_0FC7_REG_6): New.
 513         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
 514         (prefix_table): Replace PREFIX_0FC7_REG_6 with
 515         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
 516         PREFIX_MOD_3_0FC7_REG_7.
 517         (mod_table): Replace PREFIX_0FC7_REG_6 with
 518         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
 519         PREFIX_MOD_3_0FC7_REG_7.
 520
 521 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 522
 523         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
 524         (PREFIX_MANDATORY_REPNZ): Likewise.
 525         (PREFIX_MANDATORY_DATA): Likewise.
 526         (PREFIX_MANDATORY_ADDR): Likewise.
 527         (PREFIX_MANDATORY_LOCK): Likewise.
 528         (PREFIX_MANDATORY): Likewise.
 529         (PREFIX_UD_SHIFT): Set to 8
 530         (PREFIX_UD_REPZ): Updated.
 531         (PREFIX_UD_REPNZ): Likewise.
 532         (PREFIX_UD_DATA): Likewise.
 533         (PREFIX_UD_ADDR): Likewise.
 534         (PREFIX_UD_LOCK): Likewise.
 535         (PREFIX_IGNORED_SHIFT): New.
 536         (PREFIX_IGNORED_REPZ): Likewise.
 537         (PREFIX_IGNORED_REPNZ): Likewise.
 538         (PREFIX_IGNORED_DATA): Likewise.
 539         (PREFIX_IGNORED_ADDR): Likewise.
 540         (PREFIX_IGNORED_LOCK): Likewise.
 541         (PREFIX_OPCODE): Likewise.
 542         (PREFIX_IGNORED): Likewise.
 543         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 544         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 545         (three_byte_table): Likewise.
 546         (mod_table): Likewise.
 547         (mandatory_prefix): Renamed to ...
 548         (prefix_requirement): This.
 549         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 550         Update PREFIX_90 entry.
 551         (get_valid_dis386): Check prefix_requirement to see if a prefix
 552         should be ignored.
 553         (print_insn): Replace mandatory_prefix with prefix_requirement.
 554
 555 2015-04-15  Renlin Li  <renlin.li@arm.com>
 556
 557         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
 558         use it for ssat and ssat16.
 559         (print_insn_thumb32): Add handle case for 'D' control code.
 560
 561 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
 562             H.J. Lu  <hongjiu.lu@intel.com>
 563
 564         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
 565         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
 566         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
 567         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
 568         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
 569         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
 570         Fill prefix_requirement field.
 571         (struct dis386): Add prefix_requirement field.
 572         (dis386): Fill prefix_requirement field.
 573         (dis386_twobyte): Ditto.
 574         (twobyte_has_mandatory_prefix_: Remove.
 575         (reg_table): Fill prefix_requirement field.
 576         (prefix_table): Ditto.
 577         (x86_64_table): Ditto.
 578         (three_byte_table): Ditto.
 579         (xop_table): Ditto.
 580         (vex_table): Ditto.
 581         (vex_len_table): Ditto.
 582         (vex_w_table): Ditto.
 583         (mod_table): Ditto.
 584         (bad_opcode): Ditto.
 585         (print_insn): Use prefix_requirement.
 586         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
 587         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
 588         (float_reg): Ditto.
 589
 590 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
 591
 592         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
 593
 594 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 595
 596         * Makefile.in: Regenerated.
 597
 598 2015-03-25  Anton Blanchard  <anton@samba.org>
 599
 600         * ppc-dis.c (disassemble_init_powerpc): Only initialise
 601         powerpc_opcd_indices and vle_opcd_indices once.
 602
 603 2015-03-25  Anton Blanchard  <anton@samba.org>
 604
 605         * ppc-opc.c (powerpc_opcodes): Add slbfee.
 606
 607 2015-03-24  Terry Guo  <terry.guo@arm.com>
 608
 609         * arm-dis.c (opcode32): Updated to use new arm feature struct.
 610         (opcode16): Likewise.
 611         (coprocessor_opcodes): Replace bit with feature struct.
 612         (neon_opcodes): Likewise.
 613         (arm_opcodes): Likewise.
 614         (thumb_opcodes): Likewise.
 615         (thumb32_opcodes): Likewise.
 616         (print_insn_coprocessor): Likewise.
 617         (print_insn_arm): Likewise.
 618         (select_arm_features): Follow new feature struct.
 619
 620 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 621
 622         * i386-dis.c (rm_table): Add clzero.
 623         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
 624         Add CPU_CLZERO_FLAGS.
 625         (cpu_flags): Add CpuCLZERO.
 626         * i386-opc.h: Add CpuCLZERO.
 627         * i386-opc.tbl: Add clzero.
 628         * i386-init.h: Re-generated.
 629         * i386-tbl.h: Re-generated.
 630
 631 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 632
 633         * mips-opc.c (decode_mips_operand): Fix constraint issues
 634         with u and y operands.
 635
 636 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 637
 638         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
 639
 640 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 641
 642         * s390-opc.c: Add new IBM z13 instructions.
 643         * s390-opc.txt: Likewise.
 644
 645 2015-03-10  Renlin Li  <renlin.li@arm.com>
 646
 647         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
 648         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
 649         related alias.
 650         * aarch64-asm-2.c: Regenerate.
 651         * aarch64-dis-2.c: Likewise.
 652         * aarch64-opc-2.c: Likewise.
 653
 654 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
 655
 656         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
 657
 658 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
 659
 660         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
 661         arch_sh_up.
 662         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
 663         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
 664
 665 2015-02-23  Vinay  <Vinay.G@kpit.com>
 666
 667         * rl78-decode.opc (MOV): Added space between two operands for
 668         'mov' instruction in index addressing mode.
 669         * rl78-decode.c: Regenerate.
 670
 671 2015-02-19  Pedro Alves  <palves@redhat.com>
 672
 673         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
 674
 675 2015-02-10  Pedro Alves  <palves@redhat.com>
 676             Tom Tromey  <tromey@redhat.com>
 677
 678         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
 679         microblaze_and, microblaze_xor.
 680         * microblaze-opc.h (opcodes): Adjust.
 681
 682 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
 683
 684         * Makefile.am: Add FT32 files.
 685         * configure.ac: Handle FT32.
 686         * disassemble.c (disassembler): Call print_insn_ft32.
 687         * ft32-dis.c: New file.
 688         * ft32-opc.c: New file.
 689         * Makefile.in: Regenerate.
 690         * configure: Regenerate.
 691         * po/POTFILES.in: Regenerate.
 692
 693 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 694
 695         * nds32-asm.c (keyword_sr): Add new system registers.
 696
 697 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 698
 699         * s390-dis.c (s390_extract_operand): Support vector register
 700         operands.
 701         (s390_print_insn_with_opcode): Support new operands types and add
 702         new handling of optional operands.
 703         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
 704         and include opcode/s390.h instead.
 705         (struct op_struct): New field `flags'.
 706         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
 707         (dumpTable): Dump flags.
 708         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
 709         string.
 710         * s390-opc.c: Add new operands types, instruction formats, and
 711         instruction masks.
 712         (s390_opformats): Add new formats for .insn.
 713         * s390-opc.txt: Add new instructions.
 714
 715 2015-01-01  Alan Modra  <amodra@gmail.com>
 716
 717         Update year range in copyright notice of all files.
 718
 719 For older changes see ChangeLog-2014
 720 \f
 721 Copyright (C) 2015 Free Software Foundation, Inc.
 722
 723 Copying and distribution of this file, with or without modification,
 724 are permitted in any medium without royalty provided the copyright
 725 notice and this notice are preserved.
 726
 727 Local Variables:
 728 mode: change-log
 729 left-margin: 8
 730 fill-column: 74
 731 version-control: never
 732 End: