opcodes/ChangeLog

   1 2020-12-04  Andreas Krebbel  <krebbel@linux.ibm.com>
   2
   3         * s390-opc.txt: Add risbgz and risbgnz.
   4         * s390-opc.c (U6_26): New operand type.
   5         (INSTR_RIE_RRUUU2, MASK_RIE_RRUUU2): New instruction format and
   6         mask.
   7
   8 2020-12-03  Andreas Krebbel  <krebbel@linux.ibm.com>
   9
  10         * s390-opc.txt: Add extended mnemonics.
  11
  12 2020-12-01  Nelson Chu  <nelson.chu@sifive.com>
  13
  14         * riscv-opc.c (riscv_ext_version_table): Remove the p, v, n
  15         and their versions.
  16
  17 2020-12-01  Nelson Chu  <nelson.chu@sifive.com>
  18
  19         * riscv-opc.c (riscv_ext_version_table): Add zifencei.
  20
  21 2020-11-28 Borislav Petkov  <bp@suse.de>
  22
  23         * i386-dis.c (print_insn): Set active_seg_prefix for branch hint insns
  24         to not dump branch hint prefixes 0x2E and 0x3E as unused prefixes.
  25
  26 2020-11-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  27
  28         * aarch64-tbl.h (FLAGM): Handle for FLAGM feature.
  29         (struct aarch64_opcode):  Move FLAGM instructions from V8_4_INSN to
  30         FLAGM_INSN.
  31         (AARCH64_FEATURE_FLAGMANIP): Update comment for FEAT_FlagM2.
  32
  33 2020-11-14  Borislav Petkov  <bp@suse.de>
  34
  35         * i386-dis.c (ckprefix): Do not assign active_seg_prefix in
  36         64-bit addressing mode.
  37         (NOTRACK_Fixup): Test prefixes for PREFIX_DS, instead of
  38         active_seg_prefix.
  39
  40 2020-11-11  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  41
  42         * aarch64-tbl.h: Enable -march=armv8.6-a+ls64.
  43
  44 2020-11-09  Spencer E. Olson  <olsonse@umich.edu>
  45
  46         * pru-opc.c: Add opcode description for LMBD (left-most bit
  47         detect).
  48
  49 2020-11-09  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  50
  51         * aarch64-opc.c: Add ACCDATA_EL1 system register
  52
  53 2020-11-09  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  54
  55         * aarch64-opc.c (aarch64_print_operand): Support operand AARCH64_OPND_Rt_LS64
  56         print.
  57         * aarch64-tbl.h (struct aarch64_opcode): Update _LS64_INSN instructions with
  58         Rt_ls64 operands.
  59         * aarch64-asm-2.c: Regenerated.
  60         * aarch64-dis-2.c: Regenerated.
  61         * aarch64-opc-2.c: Regenerated.
  62
  63 2020-11-06  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  64
  65         * aarch64-tbl.h (PAC): Handle for PAC feature.
  66         (PAC_INSN): New PAC instruction.
  67         (struct aarch64_opcode):  Move PAC instructions from V8_3_INSN to
  68         PAC_INSN.
  69
  70 2020-11-04  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  71
  72         * aarch64-opc.c: Add RAS 1.1 new system registers: ERXPFGCTL_EL1,
  73         ERXPFGCDN_EL1, ERXMISC2_EL1, ERXMISC3_EL1 and ERXPFGF_EL1.
  74
  75 2020-11-03  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  76
  77         * aarch64-tbl.h (QL_X2NIL): New qualifier for 64-byte stores.
  78         (LS64): Handler with +ls64 feature flags.
  79         (_LS64_INSN): New instruction group macro.
  80         (struct aarch64_opcode): Add LS64 instructions.
  81         * aarch64-asm-2.c: Regenerated.
  82         * aarch64-dis-2.c: Regenerated.
  83         * aarch64-opc-2.c: Regenerated.
  84
  85 2020-10-30  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  86
  87         * aarch65-tbl.h (struct aarch64_opcode): New instruction WFIT.
  88         * aarch64-asm-2.c: Regenerated.
  89         * aarch64-dis-2.c: Regenerated.
  90         * aarch64-opc-2.c: Regenerated.
  91
  92 2020-10-27  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  93
  94         * aarch64-opc.c (aarch64_print_operand): CSR PDEC operand print-out.
  95         * aarch64-tbl.h (CSRE): New CSRE feature handler.
  96         (_CSRE_INSN): New CSRE instruction type.
  97         (struct aarch64_opcode): New 'csre' entry for a CSRE CLI feature.
  98         * aarch64-asm-2.c: Regenerated.
  99         * aarch64-dis-2.c: Regenerated.
 100         * aarch64-opc-2.c: Regenerated.
 101
 102 2020-10-27  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 103
 104         * aarch64-tbl.h (struct aarch64_opcode): Add new WFET instruction encoding
 105         and operand description.
 106         * aarch64-asm-2.c: Regenerated.
 107         * aarch64-dis-2.c: Regenerated.
 108         * aarch64-opc-2.c: Regenerated.
 109
 110 2020-10-26  Cooper Qu <cooper.qu@linux.alibaba.com>
 111
 112         * csky-opc.h (csky_v2_opcodes): Change plsl.u16 to plsl.16.
 113
 114 2020-10-26  Cooper Qu <cooper.qu@linux.alibaba.com>
 115
 116         * csky-dis.c (csky_output_operand): Add handler for
 117         OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX.
 118         * csky-opc.h (OPRND_TYPE_VREG_WITH_INDEX): New enum.
 119         (OPRND_TYPE_IMM5b_VSH): New enum. (csky_v2_opcodes): Fix and add
 120         some instructions for VDSPV1.
 121
 122 2020-10-26  Lili Cui  <lili.cui@intel.com>
 123
 124         * i386-dis.c: Change "XV" to print "{vex}" pseudo prefix.
 125
 126 2020-10-23  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 127
 128         * aarch64-asm.c (aarch64_ins_barrier_dsb_nxs): New inserter.
 129         * aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): New inserter
 130         ins_barrier_dsb_nx.
 131         * aarch64-dis.c (aarch64_ext_barrier_dsb_nxs): New extractor.
 132         * aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): New extractor
 133         ext_barrier_dsb_nx.
 134         * aarch64-opc.c (aarch64_print_operand): New options table
 135         aarch64_barrier_dsb_nxs_options.
 136         * aarch64-opc.h (enum aarch64_field_kind): New field name FLD_CRm_dsb_nxs.
 137         * aarch64-tbl.h (struct aarch64_opcode): Define DSB nXS barrier
 138         Armv8.7-a instruction.
 139         * aarch64-asm-2.c: Regenerated.
 140         * aarch64-dis-2.c: Regenerated.
 141         * aarch64-opc-2.c: Regenerated.
 142
 143 2020-10-22  H.J. Lu  <hongjiu.lu@intel.com>
 144
 145         * po/es.po: Remove the duplicated entry.
 146
 147 2020-10-20  Dr. David Alan Gilbert  <dgilbert@redhat.com>
 148
 149         * po/es.po: Fix printf format.
 150
 151 2020-10-20  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 152
 153         * i386-dis.c (rm_table): Add tlbsync, snp, invlpgb.
 154         * i386-gen.c (cpu_flag_init): Add new CPU_INVLPGB_FLAGS,
 155         CPU_TLBSYNC_FLAGS, and CPU_SNP_FLAGS.
 156         Add CPU_ZNVER3_FLAGS.
 157         (cpu_flags): Add CpuINVLPGB, CpuTLBSYNC, CpuSNP.
 158         * i386-opc.h: Add CpuINVLPGB, CpuTLBSYNC, CpuSNP.
 159         * i386-opc.tbl: Add invlpgb, tlbsync, psmash, pvalidate,
 160         rmpupdate, rmpadjust.
 161         * i386-init.h: Re-generated.
 162         * i386-tbl.h: Re-generated.
 163
 164 2020-10-16  Lili Cui  <lili.cui@intel.com>
 165
 166         * i386-opc.tbl: Rename CpuVEX_PREFIX to PseudoVexPrefix
 167         and move it from cpu_flags to opcode_modifiers.
 168         Use VexW0 and VexVVVV in the AVX-VNNI instructions.
 169         * i386-gen.c: Likewise.
 170         * i386-opc.h: Likewise.
 171         * i386-opc.h: Likewise.
 172         * i386-init.h: Regenerated.
 173         * i386-tbl.h: Likewise.
 174
 175 2020-10-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 176
 177         * aarch64-tbl.h (ARMV8_7): New macro.
 178
 179 2020-10-14  H.J. Lu  <hongjiu.lu@intel.com>
 180             Lili Cui  <lili.cui@intel.com>
 181
 182         * i386-dis.c (PREFIX_VEX_0F3850): New.
 183         (PREFIX_VEX_0F3851): Likewise.
 184         (PREFIX_VEX_0F3852): Likewise.
 185         (PREFIX_VEX_0F3853): Likewise.
 186         (VEX_W_0F3850_P_2): Likewise.
 187         (VEX_W_0F3851_P_2): Likewise.
 188         (VEX_W_0F3852_P_2): Likewise.
 189         (VEX_W_0F3853_P_2): Likewise.
 190         (prefix_table): Add PREFIX_VEX_0F3850, PREFIX_VEX_0F3851,
 191         PREFIX_VEX_0F3852 and PREFIX_VEX_0F3853.
 192         (vex_table): Add VEX_W_0F3850_P_2, VEX_W_0F3851_P_2,
 193         VEX_W_0F3852_P_2 and VEX_W_0F3853_P_2.
 194         (putop): Add support for "XV" to print "{vex3}" pseudo prefix.
 195         * i386-gen.c (cpu_flag_init): Clear the CpuAVX_VNNI bit in
 196         CPU_UNKNOWN_FLAGS.  Add CPU_AVX_VNNI_FLAGS and
 197         CPU_ANY_AVX_VNNI_FLAGS.
 198         (cpu_flags): Add CpuAVX_VNNI and CpuVEX_PREFIX.
 199         * i386-opc.h (CpuAVX_VNNI): New.
 200         (CpuVEX_PREFIX): Likewise.
 201         (i386_cpu_flags): Add cpuavx_vnni and cpuvex_prefix.
 202         * i386-opc.tbl: Add Intel AVX VNNI instructions.
 203         * i386-init.h: Regenerated.
 204         * i386-tbl.h: Likewise.
 205
 206 2020-10-14  Lili Cui  <lili.cui@intel.com>
 207             H.J. Lu  <hongjiu.lu@intel.com>
 208
 209         * i386-dis.c (PREFIX_0F3A0F): New.
 210         (MOD_0F3A0F_PREFIX_1): Likewise.
 211         (REG_0F3A0F_PREFIX_1_MOD_3): Likewise.
 212         (RM_0F3A0F_P_1_MOD_3_REG_0): Likewise.
 213         (prefix_table): Add PREFIX_0F3A0F.
 214         (mod_table): Add MOD_0F3A0F_PREFIX_1.
 215         (reg_table): Add REG_0F3A0F_PREFIX_1_MOD_3.
 216         (rm_table): Add RM_0F3A0F_P_1_MOD_3_REG_0.
 217         * i386-gen.c (cpu_flag_init): Add HRESET_FLAGS,
 218         CPU_ANY_HRESET_FLAGS.
 219         (cpu_flags): Add CpuHRESET.
 220         (output_i386_opcode): Allow 4 byte base_opcode.
 221         * i386-opc.h (enum): Add CpuHRESET.
 222         (i386_cpu_flags): Add cpuhreset.
 223         * i386-opc.tbl: Add Intel HRESET instruction.
 224         * i386-init.h: Regenerate.
 225         * i386-tbl.h: Likewise.
 226
 227 2020-10-14  Lili Cui  <lili.cui@intel.com>
 228
 229         * i386-dis.c (enum): Add
 230         PREFIX_MOD_3_0F01_REG_5_RM_4,
 231         PREFIX_MOD_3_0F01_REG_5_RM_5,
 232         PREFIX_MOD_3_0F01_REG_5_RM_6,
 233         PREFIX_MOD_3_0F01_REG_5_RM_7,
 234         X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
 235         X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
 236         X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
 237         X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
 238         X86_64_0FC7_REG_6_MOD_3_PREFIX_1.
 239         (prefix_table): New instructions (see prefixes above).
 240         (rm_table): Likewise
 241         * i386-gen.c (cpu_flag_init): Add CPU_UINTR_FLAGS,
 242         CPU_ANY_UINTR_FLAGS.
 243         (cpu_flags): Add CpuUINTR.
 244         * i386-opc.h (enum): Add CpuUINTR.
 245         (i386_cpu_flags): Add cpuuintr.
 246         * i386-opc.tbl: Add UINTR insns.
 247         * i386-init.h: Regenerate.
 248         * i386-tbl.h: Likewise.
 249
 250 2020-10-14  H.J. Lu  <hongjiu.lu@intel.com>
 251
 252         * i386-gen.c (process_i386_opcode_modifier): Return 1 for
 253         non-VEX/EVEX/prefix encoding.
 254         (output_i386_opcode): Fail if non-VEX/EVEX/prefix base_opcode
 255         has a prefix byte.
 256         * i386-opc.tbl: Replace the prefix byte in non-VEX/EVEX
 257         base_opcode with PREFIX_0X66, PREFIX_0XF2 or PREFIX_0XF3.
 258         * i386-tbl.h: Regenerated.
 259
 260 2020-10-13  H.J. Lu  <hongjiu.lu@intel.com>
 261
 262         * i386-gen.c (opcode_modifiers): Replace VexOpcode with
 263         OpcodePrefix.
 264         * i386-opc.h (VexOpcode): Renamed to ...
 265         (OpcodePrefix): This.
 266         (PREFIX_NONE): New.
 267         (PREFIX_0X66): Likewise.
 268         (PREFIX_0XF2): Likewise.
 269         (PREFIX_0XF3): Likewise.
 270         * i386-opc.tbl (Prefix_0X66): New.
 271         (Prefix_0XF2): Likewise.
 272         (Prefix_0XF3): Likewise.
 273         Replace VexOpcode= with OpcodePrefix=.  Use Prefix_0X66 on xorpd.
 274         Use Prefix_0XF3 on cvtdq2pd.  Use Prefix_0XF2 on cvtpd2dq.
 275         * i386-tbl.h: Regenerated.
 276
 277 2020-10-08  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 278
 279         * aarch64-opc.c: Add BRBE system registers.
 280
 281 2020-10-08  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 282
 283         * aarch64-opc.c: New CSRE system registers defined.
 284
 285 2020-10-05  Samanta Navarro  <ferivoz@riseup.net>
 286
 287         * cgen-asm.c: Fix spelling mistakes.
 288         * cgen-dis.c: Fix spelling mistakes.
 289         * tic30-dis.c: Fix spelling mistakes.
 290
 291 2020-10-05  H.J. Lu  <hongjiu.lu@intel.com>
 292
 293         PR binutils/26704
 294         * i386-dis.c (putop): Always display suffix for %LQ in 64bit.
 295
 296 2020-10-05  H.J. Lu  <hongjiu.lu@intel.com>
 297
 298         PR binutils/26705
 299         * i386-dis.c (print_insn): Clear modrm if not needed.
 300         (putop): Check need_modrm for modrm.mod != 3.  Don't check
 301         need_modrm for modrm.mod == 3.
 302
 303 2020-09-28  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 304
 305         * aarch64-opc.c: Added ETMv4 system registers TRCACATRn, TRCACVRn,
 306         TRCAUTHSTATUS, TRCAUXCTLR, TRCBBCTLR, TRCCCCTLR, TRCCIDCCTLR0, TRCCIDCCTLR1,
 307         TRCCIDCVRn, TRCCIDR0, TRCCIDR1, TRCCIDR2, TRCCIDR3, TRCCLAIMCLR, TRCCLAIMSET,
 308         TRCCNTCTLRn, TRCCNTRLDVRn, TRCCNTVRn, TRCCONFIGR, TRCDEVAFF0, TRCDEVAFF1,
 309         TRCDEVARCH, TRCDEVID, TRCDEVTYPE, TRCDVCMRn, TRCDVCVRn, TRCEVENTCTL0R,
 310         TRCEVENTCTL1R, TRCEXTINSELR, TRCIDR0, TRCIDR1, TRCIDR2, TRCIDR3, TRCIDR4,
 311         TRCIDR5, TRCIDR6, TRCIDR7, TRCIDR8, TRCIDR9, TRCIDR10, TRCIDR11, TRCIDR12,
 312         TRCIDR13, TRCIMSPEC0, TRCIMSPECn, TRCITCTRL, TRCLAR WOTRCLSR, TRCOSLAR
 313         WOTRCOSLSR, TRCPDCR, TRCPDSR, TRCPIDR0, TRCPIDR1, TRCPIDR2, TRCPIDR3,
 314         TRCPIDR4, TRCPIDR[5,6,7], TRCPRGCTLR, TRCP,CSELR, TRCQCTLR, TRCRSCTLRn,
 315         TRCSEQEVRn, TRCSEQRSTEVR, TRCSEQSTR, TRCSSCCRn, TRCSSCSRn, TRCSSPCICRn,
 316         TRCSTALLCTLR, TRCSTATR, TRCSYNCPR, TRCTRACEIDR,  TRCTSCTLR, TRCVDARCCTLR,
 317         TRCVDCTLR, TRCVDSACCTLR, TRCVICTLR, TRCVIIECTLR, TRCVIPCSSCTLR, TRCVISSCTLR,
 318         TRCVMIDCCTLR0, TRCVMIDCCTLR1 and TRCVMIDCVRn.
 319
 320 2020-09-28  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 321
 322         * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
 323
 324 2020-09-28  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 325
 326         * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,
 327         TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
 328
 329 2020-09-26  Alan Modra  <amodra@gmail.com>
 330
 331         * csky-opc.h: Formatting.
 332         (GENERAL_REG_BANK): Correct spelling.  Update use throughout file.
 333         (get_register_name): Mask arch with CSKY_ARCH_MASK for shift,
 334         and shift 1u.
 335         (get_register_number): Likewise.
 336         * csky-dis.c (get_gr_name, get_cr_name): Don't mask mach_flag.
 337
 338 2020-09-24  Lili Cui  <lili.cui@intel.com>
 339
 340         PR 26654
 341         * i386-dis.c (enum): Put MOD_VEX_0F38* together.
 342
 343 2020-09-24  Andrew Burgess <andrew.burgess@embecosm.com>
 344
 345         * csky-dis.c (csky_output_operand): Enclose body of if in curly
 346         braces.
 347
 348 2020-09-24  Lili Cui  <lili.cui@intel.com>
 349
 350         * i386-dis.c (enum): Add PREFIX_0F01_REG_1_RM_5,
 351         PREFIX_0F01_REG_1_RM_6, PREFIX_0F01_REG_1_RM_7,
 352         X86_64_0F01_REG_1_RM_5_P_2, X86_64_0F01_REG_1_RM_6_P_2,
 353         X86_64_0F01_REG_1_RM_7_P_2.
 354         (prefix_table): Likewise.
 355         (x86_64_table): Likewise.
 356         (rm_table): Likewise.
 357         * i386-gen.c (cpu_flag_init): Add CPU_TDX_FLAGS
 358         and CPU_ANY_TDX_FLAGS.
 359         (cpu_flags): Add CpuTDX.
 360         * i386-opc.h (enum): Add CpuTDX.
 361         (i386_cpu_flags): Add cputdx.
 362         * i386-opc.tbl: Add TDX insns.
 363         * i386-init.h: Regenerate.
 364         * i386-tbl.h: Likewise.
 365
 366 2020-09-17 Cooper Qu <<cooper.qu@linux.alibaba.com>>
 367
 368         * csky-dis.c (using_abi): New.
 369         (parse_csky_dis_options): New function.
 370         (get_gr_name): New function.
 371         (get_cr_name): New function.
 372         (csky_output_operand): Use get_gr_name and get_cr_name to
 373         disassemble and add handle of OPRND_TYPE_IMM5b_LS.
 374         (print_insn_csky): Parse disassembler options.
 375         * csky-opc.h (OPRND_TYPE_IMM5b_LS): New enum.
 376         (GENARAL_REG_BANK): Define.
 377         (REG_SUPPORT_ALL): Define.
 378         (REG_SUPPORT_ALL): New.
 379         (ASH): Define.
 380         (REG_SUPPORT_A): Define.
 381         (REG_SUPPORT_B): Define.
 382         (REG_SUPPORT_C): Define.
 383         (REG_SUPPORT_D): Define.
 384         (REG_SUPPORT_E): Define.
 385         (csky_abiv1_general_regs): New.
 386         (csky_abiv1_control_regs): New.
 387         (csky_abiv2_general_regs): New.
 388         (csky_abiv2_control_regs): New.
 389         (get_register_name): New function.
 390         (get_register_number): New function.
 391         (csky_get_general_reg_name): New function.
 392         (csky_get_general_regno): New function.
 393         (csky_get_control_reg_name): New function.
 394         (csky_get_control_regno): New function.
 395         (csky_v2_opcodes): Prefer two oprerans format for bclri and
 396         bseti, strengthen the operands legality check of addc, zext
 397         and sext.
 398
 399 2020-09-23  Lili Cui  <lili.cui@intel.com>
 400
 401         * i386-dis.c (enum): Add REG_0F38D8_PREFIX_1,
 402         MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1,
 403         MOD_0F38DC_PREFIX_1, MOD_0F38DD_PREFIX_1,
 404         MOD_0F38DE_PREFIX_1, MOD_0F38DF_PREFIX_1,
 405         PREFIX_0F38D8, PREFIX_0F38FA, PREFIX_0F38FB.
 406         (reg_table): New instructions (see prefixes above).
 407         (prefix_table): Likewise.
 408         (three_byte_table): Likewise.
 409         (mod_table): Likewise
 410         * i386-gen.c (cpu_flag_init): Add CPU_KL_FLAGS, CPU_WIDE_KL_FLAGS,
 411         CPU_ANY_KL_FLAGS and CPU_ANY_WIDE_KL_FLAGS.
 412         (cpu_flags): Likewise.
 413         (operand_type_init): Likewise.
 414         * i386-opc.h (enum): Add CpuKL and CpuWide_KL.
 415         (i386_cpu_flags): Add cpukl and cpuwide_kl.
 416         * i386-opc.tbl: Add KL and WIDE_KL insns.
 417         * i386-init.h: Regenerate.
 418         * i386-tbl.h: Likewise.
 419
 420 2020-09-21  Alan Modra  <amodra@gmail.com>
 421
 422         * rx-dis.c (flag_names): Add missing comma.
 423         (register_names, flag_names, double_register_names),
 424         (double_register_high_names, double_register_low_names),
 425         (double_control_register_names, double_condition_names): Remove
 426         trailing commas.
 427
 428 2020-09-18  David Faust  <david.faust@oracle.com>
 429
 430         * bpf-desc.c: Regenerate.
 431         * bpf-desc.h: Likewise.
 432         * bpf-opc.c: Likewise.
 433         * bpf-opc.h: Likewise.
 434
 435 2020-09-16  Andrew Burgess <andrew.burgess@embecosm.com>
 436
 437         * csky-dis.c (csky_get_disassembler): Don't return NULL when there
 438         is no BFD.
 439
 440 2020-09-16  Alan Modra  <amodra@gmail.com>
 441
 442         * ppc-dis.c (ppc_symbol_is_valid): Adjust elf_symbol_from invocation.
 443
 444 2020-09-10  Nick Clifton  <nickc@redhat.com>
 445
 446         * ppc-dis.c (ppc_symbol_is_valid): New function.  Returns false
 447         for hidden, local, no-type symbols.
 448         (disassemble_init_powerpc): Point the symbol_is_valid field in the
 449         info structure at the new function.
 450
 451 2020-09-10  Cooper Qu  <cooper.qu@linux.alibaba.com>
 452
 453         * csky-opc.h (csky_v2_opcodes): Add L2Cache instructions.
 454         * testsuite/gas/csky/cskyv2_ck860.d : Adjust to icache.iva
 455         opcode fixing.
 456
 457 2020-09-10  Nick Clifton  <nickc@redhat.com>
 458
 459         * csky-dis.c (csky_output_operand): Coerce the immediate values to
 460         long before printing.
 461
 462 2020-09-10  Alan Modra  <amodra@gmail.com>
 463
 464         * csky-dis.c (csky_output_operand): Don't sprintf str to itself.
 465
 466 2020-09-07  Cooper Qu  <cooper.qu@linux.alibaba.com>
 467
 468         * csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
 469         ISA flag.
 470
 471 2020-09-07  Cooper Qu  <cooper.qu@linux.alibaba.com>
 472
 473         * csky-dis.c (csky_output_operand): Add handlers for
 474         OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
 475         OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH
 476         to support FPUV3 instructions.
 477         * csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b,
 478         OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
 479         OPRND_TYPE_DFLOAT_FMOVI.
 480         (OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8,
 481          OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24,
 482          OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22,
 483          OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25,
 484          OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25,
 485          OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21,
 486          OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24,
 487          OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25,
 488          OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20,
 489          OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25,
 490          OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24,
 491          OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20,
 492          OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define.
 493         (csky_v2_opcodes): Add FPUV3 instructions.
 494
 495 2020-09-08  Alex Coplan  <alex.coplan@arm.com>
 496
 497         * aarch64-dis.c (print_operands): Pass CPU features to
 498         aarch64_print_operand().
 499         * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
 500         preferred disassembly of system registers.
 501         (SR_RNG): Refactor to use new SR_FEAT2 macro.
 502         (SR_FEAT2): New.
 503         (SR_V8_1_A): New.
 504         (SR_V8_4_A): New.
 505         (SR_V8_A): New.
 506         (SR_V8_R): New.
 507         (SR_EXPAND_ELx): New.
 508         (SR_EXPAND_EL12): New.
 509         (aarch64_sys_regs): Specify which registers are only on
 510         A-profile, add R-profile system registers.
 511         (ENC_BARLAR): New.
 512         (PRBARn_ELx): New.
 513         (PRLARn_ELx): New.
 514         (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
 515         Armv8-R AArch64.
 516
 517 2020-09-08  Alex Coplan  <alex.coplan@arm.com>
 518
 519         * aarch64-tbl.h (aarch64_feature_v8_r): New.
 520         (ARMV8_R): New.
 521         (V8_R_INSN): New.
 522         (aarch64_opcode_table): Add dfb.
 523         * aarch64-opc-2.c: Regenerate.
 524         * aarch64-asm-2.c: Regenerate.
 525         * aarch64-dis-2.c: Regenerate.
 526
 527 2020-09-08  Alex Coplan  <alex.coplan@arm.com>
 528
 529         * aarch64-dis.c (arch_variant): New.
 530         (determine_disassembling_preference): Disassemble according to
 531         arch variant.
 532         (select_aarch64_variant): New.
 533         (print_insn_aarch64): Set feature set.
 534
 535 2020-09-02  Alan Modra  <amodra@gmail.com>
 536
 537         * v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3),
 538         (insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9),
 539         (insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16),
 540         (insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9),
 541         (insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID),
 542         (insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP),
 543         (nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long
 544         for value parameter and update code to suit.
 545         (extract_d9, extract_d16_15, extract_d16_16, extract_d17_16),
 546         (extract_d22, extract_d23, extract_i9): Use unsigned long variables.
 547
 548 2020-09-02  Alan Modra  <amodra@gmail.com>
 549
 550         * i386-dis.c (OP_E_memory): Don't cast to signed type when
 551         negating.
 552         (get32, get32s): Use unsigned types in shift expressions.
 553
 554 2020-09-02  Alan Modra  <amodra@gmail.com>
 555
 556         * csky-dis.c (print_insn_csky): Use unsigned type for "given".
 557
 558 2020-09-02  Alan Modra  <amodra@gmail.com>
 559
 560         * crx-dis.c: Whitespace.
 561         (print_arg): Use unsigned type for longdisp and mask variables,
 562         and for left shift constant.
 563
 564 2020-09-02  Alan Modra  <amodra@gmail.com>
 565
 566         * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
 567         * bpf-ibld.c: Regenerate.
 568         * epiphany-ibld.c: Regenerate.
 569         * fr30-ibld.c: Regenerate.
 570         * frv-ibld.c: Regenerate.
 571         * ip2k-ibld.c: Regenerate.
 572         * iq2000-ibld.c: Regenerate.
 573         * lm32-ibld.c: Regenerate.
 574         * m32c-ibld.c: Regenerate.
 575         * m32r-ibld.c: Regenerate.
 576         * mep-ibld.c: Regenerate.
 577         * mt-ibld.c: Regenerate.
 578         * or1k-ibld.c: Regenerate.
 579         * xc16x-ibld.c: Regenerate.
 580         * xstormy16-ibld.c: Regenerate.
 581
 582 2020-09-02  Alan Modra  <amodra@gmail.com>
 583
 584         * bfin-dis.c (MASKBITS): Use SIGNBIT.
 585
 586 2020-09-02  Cooper Qu  <cooper.qu@linux.alibaba.com>
 587
 588         * csky-opc.h (csky_v2_opcodes): Move divul and divsl
 589         to CSKYV2_ISA_3E3R3 instruction set.
 590
 591 2020-09-02  Cooper Qu  <cooper.qu@linux.alibaba.com>
 592
 593         * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
 594
 595 2020-09-01  Alan Modra  <amodra@gmail.com>
 596
 597         * mep-ibld.c: Regenerate.
 598
 599 2020-08-31  Cooper Qu  <cooper.qu@linux.alibaba.com>
 600
 601         * csky-dis.c (csky_output_operand): Assign dis_info.value for
 602         OPRND_TYPE_VREG.
 603
 604 2020-08-30  Alan Modra  <amodra@gmail.com>
 605
 606         * cr16-dis.c: Formatting.
 607         (parameter): Delete struct typedef.  Use dwordU instead
 608         throughout file.
 609         (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
 610         and tbitb.
 611         (make_argument <arg_cr>): Extract 20-bit field not 16-bit.
 612
 613 2020-08-29  Alan Modra  <amodra@gmail.com>
 614
 615         PR 26446
 616         * csky-opc.h (MAX_OPRND_NUM): Define to 5.
 617         (union csky_operand): Use MAX_OPRND_NUM to size oprnds array.
 618
 619 2020-08-28  Alan Modra  <amodra@gmail.com>
 620
 621         PR 26449
 622         PR 26450
 623         * cgen-ibld.in (insert_1): Use 1UL in forming mask.
 624         (extract_normal): Likewise.
 625         (insert_normal): Likewise, and move past zero length test.
 626         (put_insn_int_value): Handle mask for zero length, use 1UL.
 627         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 628         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 629         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 630         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 631
 632 2020-08-28  Cooper Qu  <cooper.qu@linux.alibaba.com>
 633
 634         * csky-dis.c (CSKY_DEFAULT_ISA): Define.
 635         (csky_dis_info): Add member isa.
 636         (csky_find_inst_info): Skip instructions that do not belong to
 637         current CPU.
 638         (csky_get_disassembler): Get infomation from attribute section.
 639         (print_insn_csky): Set defualt ISA flag.
 640         * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
 641         * csky-opc.h (struct csky_opcode): Change isa_flag16 and
 642         isa_flag32'type to unsigned 64 bits.
 643
 644 2020-08-26  Jose E. Marchesi  <jemarch@gnu.org>
 645
 646         * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
 647
 648 2020-08-26  David Faust  <david.faust@oracle.com>
 649
 650         * bpf-desc.c: Regenerate.
 651         * bpf-desc.h: Likewise.
 652         * bpf-opc.c: Likewise.
 653         * bpf-opc.h: Likewise.
 654         * disassemble.c (disassemble_init_for_target): Set bits for xBPF
 655         ISA when appropriate.
 656
 657 2020-08-25  Alan Modra  <amodra@gmail.com>
 658
 659         PR 26504
 660         * vax-dis.c (parse_disassembler_options): Always add at least one
 661         to entry_addr_total_slots.
 662
 663 2020-08-24  Cooper Qu  <cooper.qu@linux.alibaba.com>
 664
 665         * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
 666         in other CPUs to speed up disassembling.
 667         * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
 668         Change plsli.u16 to plsli.16, change sync's operand format.
 669
 670 2020-08-21  Cooper Qu  <cooper.qu@linux.alibaba.com>
 671
 672         * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
 673
 674 2020-08-21  Nick Clifton  <nickc@redhat.com>
 675
 676         * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
 677         symbols.
 678
 679 2020-08-21  Cooper Qu  <cooper.qu@linux.alibaba.com>
 680
 681         * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
 682
 683 2020-08-19  Alan Modra  <amodra@gmail.com>
 684
 685         * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
 686         vcmpuq and xvtlsbb.
 687
 688 2020-08-18  Peter Bergner  <bergner@linux.ibm.com>
 689
 690         * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
 691         <xvcvbf16spn>: ...to this.
 692
 693 2020-08-12  Alex Coplan  <alex.coplan@arm.com>
 694
 695         * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
 696
 697 2020-08-12  Nick Clifton  <nickc@redhat.com>
 698
 699         * po/sr.po: Updated Serbian translation.
 700
 701 2020-08-11  Alan Modra  <amodra@gmail.com>
 702
 703         * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
 704
 705 2020-08-10  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 706
 707         * aarch64-opc.c (aarch64_print_operand):
 708         (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
 709         (aarch64_sys_reg_supported_p): Function removed.
 710         (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
 711         (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
 712         into this function.
 713
 714 2020-08-10  Alan Modra  <amodra@gmail.com>
 715
 716         * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
 717         instructions.
 718
 719 2020-08-10  Alan Modra  <amodra@gmail.com>
 720
 721         * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
 722         Enable icbt for power5, miso for power8.
 723
 724 2020-08-10  Alan Modra  <amodra@gmail.com>
 725
 726         * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
 727         mtvsrd, and similarly for mfvsrd.
 728
 729 2020-08-04  Christian Groessler  <chris@groessler.org>
 730             Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
 731
 732         * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
 733         opcodes (special "out" to absolute address).
 734         * z8k-opc.h: Regenerate.
 735
 736 2020-07-30  H.J. Lu  <hongjiu.lu@intel.com>
 737
 738         PR gas/26305
 739         * i386-opc.h (Prefix_Disp8): New.
 740         (Prefix_Disp16): Likewise.
 741         (Prefix_Disp32): Likewise.
 742         (Prefix_Load): Likewise.
 743         (Prefix_Store): Likewise.
 744         (Prefix_VEX): Likewise.
 745         (Prefix_VEX3): Likewise.
 746         (Prefix_EVEX): Likewise.
 747         (Prefix_REX): Likewise.
 748         (Prefix_NoOptimize): Likewise.
 749         * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes.  Add {disp16}.
 750         * i386-tbl.h: Regenerated.
 751
 752 2020-07-29  Andreas Arnez  <arnez@linux.ibm.com>
 753
 754         * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
 755         default case with abort() instead of printing an error message and
 756         continuing, to avoid a maybe-uninitialized warning.
 757
 758 2020-07-24  Nick Clifton  <nickc@redhat.com>
 759
 760         * po/de.po: Updated German translation.
 761
 762 2020-07-21  Jan Beulich  <jbeulich@suse.com>
 763
 764         * i386-dis.c (OP_E_memory): Revert previous change.
 765
 766 2020-07-15  H.J. Lu  <hongjiu.lu@intel.com>
 767
 768         PR gas/26237
 769         * i386-dis.c (OP_E_memory): Don't display eiz with no scale
 770         without base nor index registers.
 771
 772 2020-07-15  Jan Beulich  <jbeulich@suse.com>
 773
 774         * i386-dis.c (putop): Move 'V' and 'W' handling.
 775
 776 2020-07-15  Jan Beulich  <jbeulich@suse.com>
 777
 778         * i386-dis.c (dis386): Adjust 'V' description. Use P-based
 779         construct for push/pop of register.
 780         (putop): Honor cond when handling 'P'. Drop handling of plain
 781         'V'.
 782
 783 2020-07-15  Jan Beulich  <jbeulich@suse.com>
 784
 785         * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
 786         description. Drop '&' description. Use P for push of immediate,
 787         pushf/popf, enter, and leave. Use %LP for lret/retf.
 788         (dis386_twobyte): Use P for push/pop of fs/gs.
 789         (reg_table): Use P for push/pop. Use @ for near call/jmp.
 790         (x86_64_table): Use P for far call/jmp.
 791         (putop): Drop handling of 'U' and '&'. Move and adjust handling
 792         of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
 793         labels.
 794         (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
 795         and dqw_mode (unconditional).
 796
 797 2020-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 798
 799         PR gas/26237
 800         * i386-dis.c (OP_E_memory): Without base nor index registers,
 801         32-bit displacement to 64 bits.
 802
 803 2020-07-14  Claudiu Zissulescu  <claziss@gmail.com>
 804
 805         * arc-dis.c (print_insn_arc): Detect and emit a warning when a
 806         faulty double register pair is detected.
 807
 808 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 809
 810         * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
 811
 812 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 813
 814         * i386-dis.c (OP_R, Rm): Delete.
 815         (MOD_0F24, MOD_0F26): Rename to ...
 816         (X86_64_0F24, X86_64_0F26): ... respectively.
 817         (dis386): Update 'L' and 'Z' comments.
 818         (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
 819         table references.
 820         (mod_table): Move opcode 0F24 and 0F26 entries ...
 821         (x86_64_table): ... here.
 822         (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
 823         'Z' case block.
 824
 825 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 826
 827         * i386-dis.c (Rd, Rdq, MaskR): Delete.
 828         (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
 829         MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
 830         MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
 831         MOD_EVEX_0F387C): New enumerators.
 832         (reg_table): Use Edq for rdssp.
 833         (prefix_table): Use Edq for incssp.
 834         (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
 835         kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
 836         ktest*, and kshift*. Use Edq / MaskE for kmov*.
 837         * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
 838         * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
 839         0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
 840         * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
 841         0F3828_P_1 and 0F3838_P_1.
 842         * i386-dis-evex-w.h: Reference mod_table[] for opcodes
 843         0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
 844
 845 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 846
 847         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
 848         PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
 849         PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
 850         PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
 851         PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
 852         PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
 853         (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
 854         VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
 855         VEX_LEN_0F38F3_R_3_P_0): Rename to ...
 856         (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
 857         VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
 858         (reg_table, prefix_table, three_byte_table, vex_table,
 859         vex_len_table, mod_table, rm_table): Replace / remove respective
 860         entries.
 861         (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
 862         of PREFIX_DATA in used_prefixes.
 863
 864 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 865
 866         * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
 867         MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
 868         MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
 869         MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
 870         (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
 871         MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
 872         (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
 873         VEX_W_0F3A33_L_0): Delete.
 874         (dis386): Adjust "BW" description.
 875         (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
 876         0F3A31, 0F3A32, and 0F3A33.
 877         (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
 878         entries.
 879         (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
 880         entries.
 881
 882 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 883
 884         * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
 885         PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
 886         PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
 887         PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
 888         PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
 889         PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
 890         PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
 891         PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
 892         PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
 893         PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
 894         PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
 895         PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
 896         PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
 897         PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
 898         PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
 899         PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
 900         PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
 901         PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
 902         PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
 903         PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
 904         PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
 905         PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
 906         PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
 907         PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
 908         PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
 909         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
 910         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
 911         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
 912         PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
 913         PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
 914         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
 915         PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
 916         PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
 917         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
 918         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
 919         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
 920         PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
 921         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
 922         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
 923         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
 924         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
 925         PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
 926         PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
 927         PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
 928         PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
 929         PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
 930         PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
 931         PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
 932         PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
 933         PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
 934         PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
 935         PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
 936         PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
 937         PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
 938         PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
 939         PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
 940         PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
 941         PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
 942         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
 943         PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
 944         PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
 945         PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
 946         PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
 947         PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
 948         PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
 949         PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
 950         PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
 951         PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
 952         PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
 953         PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
 954         PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
 955         PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
 956         PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
 957         PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
 958         PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
 959         PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
 960         PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
 961         PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
 962         PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
 963         PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
 964         PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
 965         PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
 966         PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
 967         PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
 968         PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
 969         PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
 970         PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
 971         PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
 972         PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
 973         PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
 974         PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
 975         PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
 976         PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
 977         PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
 978         PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
 979         PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
 980         PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
 981         PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
 982         PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
 983         PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
 984         PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
 985         PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
 986         PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
 987         PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
 988         PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
 989         PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
 990         PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
 991         PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
 992         PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
 993         PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
 994         PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
 995         PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
 996         PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
 997         PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
 998         PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
 999         PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
1000         PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
1001         PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
1002         PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
1003         PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
1004         PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
1005         PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
1006         PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
1007         PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
1008         PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
1009         PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
1010         PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
1011         PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
1012         PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
1013         PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
1014         PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
1015         PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
1016         PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
1017         PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
1018         PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
1019         PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
1020         PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
1021         PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
1022         PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
1023         PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
1024         PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
1025         PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
1026         PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
1027         PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
1028         PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
1029         PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
1030         PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
1031         PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
1032         PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
1033         PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
1034         PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
1035         PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
1036         PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
1037         PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
1038         PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
1039         PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
1040         PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
1041         (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
1042         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
1043         MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
1044         MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
1045         MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
1046         MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
1047         MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
1048         MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
1049         MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
1050         MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
1051         MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
1052         MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1053         MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1054         MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
1055         MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
1056         VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
1057         VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
1058         VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
1059         VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
1060         VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
1061         VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
1062         VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
1063         VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
1064         VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
1065         VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
1066         VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
1067         VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
1068         VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
1069         EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
1070         EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
1071         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
1072         EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
1073         EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
1074         EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1075         EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
1076         EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1077         EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1078         EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
1079         EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
1080         EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
1081         EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
1082         EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
1083         EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1084         EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
1085         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1086         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1087         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1088         EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
1089         EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
1090         EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
1091         EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
1092         EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
1093         EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
1094         EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
1095         EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
1096         VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
1097         VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
1098         VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
1099         VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
1100         VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
1101         VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
1102         VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
1103         VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
1104         VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
1105         VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
1106         VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
1107         VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
1108         VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
1109         VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
1110         VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
1111         VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
1112         VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
1113         VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
1114         EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
1115         EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
1116         EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
1117         EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
1118         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
1119         EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
1120         EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
1121         EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
1122         EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
1123         EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
1124         EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
1125         EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
1126         EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
1127         EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
1128         EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
1129         EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
1130         EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
1131         EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
1132         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
1133         EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
1134         EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
1135         EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1136         EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
1137         EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
1138         EVEX_W_0F3A72_P_2): Rename to ...
1139         (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
1140         MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
1141         MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
1142         MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
1143         MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
1144         MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
1145         MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
1146         MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
1147         MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
1148         MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
1149         MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
1150         VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
1151         VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
1152         VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
1153         VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
1154         VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
1155         VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
1156         VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
1157         VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
1158         VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
1159         EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
1160         EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
1161         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
1162         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
1163         EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
1164         EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
1165         EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
1166         EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
1167         EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
1168         EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
1169         EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
1170         EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
1171         EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
1172         EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
1173         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
1174         EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
1175         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
1176         EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
1177         EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
1178         EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
1179         EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
1180         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
1181         EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
1182         EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
1183         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
1184         VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
1185         VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
1186         VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
1187         VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
1188         VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
1189         VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
1190         VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
1191         VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
1192         VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
1193         VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
1194         VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
1195         VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
1196         VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
1197         EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
1198         EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
1199         EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
1200         EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
1201         EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
1202         EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
1203         EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
1204         EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
1205         EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
1206         EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
1207         EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
1208         EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
1209         EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
1210         EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
1211         respectively.
1212         (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
1213         vex_w_table, mod_table): Replace / remove respective entries.
1214         (print_insn): Move up dp->prefix_requirement handling. Handle
1215         PREFIX_DATA.
1216         * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
1217         i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
1218         Replace / remove respective entries.
1219
1220 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1221
1222         * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
1223         PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
1224         (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
1225         vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
1226         Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
1227         the latter two.
1228         * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1229         0F2C, 0F2D, 0F2E, and 0F2F.
1230         * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
1231         0F2F table entries.
1232
1233 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1234
1235         * i386-dis.c (OP_VexR, VexScalarR): New.
1236         (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
1237         XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
1238         need_vex_reg): Delete.
1239         (prefix_table): Replace VexScalar by VexScalarR and
1240         XMVexScalar by XMScalar for vmovss and vmovsd. Replace
1241         EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
1242         (vex_len_table): Replace EXqVexScalarS by EXqS.
1243         (get_valid_dis386): Don't set need_vex_reg.
1244         (print_insn): Don't initialize need_vex_reg.
1245         (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
1246         q_scalar_swap_mode cases.
1247         (OP_EX): Don't check for d_scalar_swap_mode and
1248         q_scalar_swap_mode.
1249         (OP_VEX): Done check need_vex_reg.
1250         * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
1251         XMVexScalar by XMScalar for vmovss and vmovsd. Replace
1252         EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
1253
1254 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1255
1256         * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
1257         (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
1258         VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
1259         VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
1260         (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
1261         VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
1262         VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
1263         VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
1264         (vex_table): Replace Vex128 by Vex.
1265         (vex_len_table): Likewise. Adjust referenced enum names.
1266         (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
1267         referenced enum names.
1268         (OP_VEX): Drop vex128_mode and vex256_mode cases.
1269         * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
1270
1271 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1272
1273         * i386-dis.c (dis386): "LW" description now applies to "DQ".
1274         (putop): Handle "DQ". Don't handle "LW" anymore.
1275         (prefix_table, mod_table): Replace %LW by %DQ.
1276         * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
1277
1278 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1279
1280         * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
1281         dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
1282         d_scalar_swap_mode case handling. Move shift adjsutment into
1283         the case its applicable to.
1284
1285 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1286
1287         * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
1288         (EXbScalar, EXwScalar): Fold to ...
1289         (EXbwUnit): ... this.
1290         (b_scalar_mode, w_scalar_mode): Fold to ...
1291         (bw_unit_mode): ... this.
1292         (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
1293         w_scalar_mode handling by bw_unit_mode one.
1294         * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
1295         ...
1296         * i386-dis-evex-prefix.h: ... here.
1297
1298 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1299
1300         * i386-dis.c (PCMPESTR_Fixup): Delete.
1301         (dis386): Adjust "LQ" description.
1302         (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
1303         cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
1304         PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
1305         vpcmpestrm, and vpcmpestri.
1306         (putop): Honor "cond" when handling LQ.
1307         * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
1308         vcvtsi2ss and vcvtusi2ss.
1309         * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
1310         vcvtsi2sd and vcvtusi2sd.
1311
1312 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1313
1314         * i386-dis.c (VCMP_Fixup, VCMP): Delete.
1315         (simd_cmp_op): Add const.
1316         (vex_cmp_op): Move up and drop initial 8 entries. Add const.
1317         (CMP_Fixup): Handle VEX case.
1318         (prefix_table): Replace VCMP by CMP.
1319         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
1320
1321 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1322
1323         * i386-dis.c (MOVBE_Fixup): Delete.
1324         (Mv): Define.
1325         (prefix_table): Use Mv for movbe entries.
1326
1327 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1328
1329         * i386-dis.c (CRC32_Fixup): Delete.
1330         (prefix_table): Use Eb/Ev for crc32 entries.
1331
1332 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1333
1334         * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
1335         Conditionalize invocations of "USED_REX (0)".
1336
1337 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1338
1339         * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
1340         CH, DH, BH, AX, DX): Delete.
1341         (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
1342         eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
1343         dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
1344
1345 2020-07-10  Lili Cui  <lili.cui@intel.com>
1346
1347         * i386-dis.c (TMM): New.
1348         (EXtmm): Likewise.
1349         (VexTmm): Likewise.
1350         (MVexSIBMEM): Likewise.
1351         (tmm_mode): Likewise.
1352         (vex_sibmem_mode): Likewise.
1353         (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
1354         (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
1355         (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
1356         (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
1357         (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
1358         (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
1359         (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
1360         (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
1361         (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
1362         (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
1363         (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
1364         (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
1365         (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
1366         (PREFIX_VEX_0F3849_X86_64): Likewise.
1367         (PREFIX_VEX_0F384B_X86_64): Likewise.
1368         (PREFIX_VEX_0F385C_X86_64): Likewise.
1369         (PREFIX_VEX_0F385E_X86_64): Likewise.
1370         (X86_64_VEX_0F3849): Likewise.
1371         (X86_64_VEX_0F384B): Likewise.
1372         (X86_64_VEX_0F385C): Likewise.
1373         (X86_64_VEX_0F385E): Likewise.
1374         (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
1375         (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
1376         (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
1377         (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
1378         (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
1379         (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
1380         (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
1381         (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
1382         (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
1383         (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
1384         (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
1385         (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
1386         (VEX_W_0F3849_X86_64_P_0): Likewise.
1387         (VEX_W_0F3849_X86_64_P_2): Likewise.
1388         (VEX_W_0F3849_X86_64_P_3): Likewise.
1389         (VEX_W_0F384B_X86_64_P_1): Likewise.
1390         (VEX_W_0F384B_X86_64_P_2): Likewise.
1391         (VEX_W_0F384B_X86_64_P_3): Likewise.
1392         (VEX_W_0F385C_X86_64_P_1): Likewise.
1393         (VEX_W_0F385E_X86_64_P_0): Likewise.
1394         (VEX_W_0F385E_X86_64_P_1): Likewise.
1395         (VEX_W_0F385E_X86_64_P_2): Likewise.
1396         (VEX_W_0F385E_X86_64_P_3): Likewise.
1397         (names_tmm): Likewise.
1398         (att_names_tmm): Likewise.
1399         (intel_operand_size): Handle void_mode.
1400         (OP_XMM): Handle tmm_mode.
1401         (OP_EX): Likewise.
1402         (OP_VEX): Likewise.
1403         * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
1404         CpuAMX_BF16 and CpuAMX_TILE.
1405         (operand_type_shorthands): Add RegTMM.
1406         (operand_type_init): Likewise.
1407         (operand_types): Add Tmmword.
1408         (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1409         (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1410         * i386-opc.h (CpuAMX_INT8): New.
1411         (CpuAMX_BF16): Likewise.
1412         (CpuAMX_TILE): Likewise.
1413         (SIBMEM): Likewise.
1414         (Tmmword): Likewise.
1415         (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
1416         (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
1417         (i386_operand_type): Add tmmword.
1418         * i386-opc.tbl: Add AMX instructions.
1419         * i386-reg.tbl: Add AMX registers.
1420         * i386-init.h: Regenerated.
1421         * i386-tbl.h: Likewise.
1422
1423 2020-07-08  Jan Beulich  <jbeulich@suse.com>
1424
1425         * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
1426         (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
1427         Rename to ...
1428         (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
1429         REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
1430         respectively.
1431         (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
1432         VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
1433         VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
1434         VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
1435         VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
1436         VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
1437         VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
1438         VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
1439         VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
1440         VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
1441         VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
1442         VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
1443         VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
1444         VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
1445         VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
1446         VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
1447         VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
1448         VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
1449         VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
1450         VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
1451         VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
1452         VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
1453         VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
1454         VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
1455         VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
1456         VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
1457         VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
1458         VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
1459         VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
1460         VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
1461         VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
1462         VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
1463         VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
1464         VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
1465         VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
1466         VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
1467         (reg_table): Re-order XOP entries. Adjust their operands.
1468         (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
1469         08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
1470         08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
1471         09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
1472         09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
1473         09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
1474         entries by references ...
1475         (vex_len_table): ... to resepctive new entries here. For several
1476         new and existing entries reference ...
1477         (vex_w_table): ... new entries here.
1478         (mod_table): New MOD_VEX_0FXOP_09_12 entry.
1479
1480 2020-07-08  Jan Beulich  <jbeulich@suse.com>
1481
1482         * i386-dis.c (XMVexScalarI4): Define.
1483         (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
1484         VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
1485         VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
1486         (vex_len_table): Move scalar FMA4 entries ...
1487         (prefix_table): ... here.
1488         (OP_REG_VexI4): Handle scalar_mode.
1489         * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
1490         * i386-tbl.h: Re-generate.
1491
1492 2020-07-08  Jan Beulich  <jbeulich@suse.com>
1493
1494         * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
1495         Vex_2src_2): Delete.
1496         (OP_VexW, VexW): New.
1497         (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
1498         for shifts and rotates by register.
1499
1500 2020-07-08  Jan Beulich  <jbeulich@suse.com>
1501
1502         * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
1503         VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
1504         OP_EX_VexReg): Delete.
1505         (OP_VexI4, VexI4): New.
1506         (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
1507         (prefix_table): ... here.
1508         (print_insn): Drop setting of vex_w_done.
1509
1510 2020-07-08  Jan Beulich  <jbeulich@suse.com>
1511
1512         * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
1513         (prefix_table, vex_len_table): Replace operands for FMA4 insns.
1514         (xop_table): Replace operands of 4-operand insns.
1515         (OP_REG_VexI4): Move VEX.W based operand swaping here.
1516
1517 2020-07-07  Claudiu Zissulescu  <claziss@synopsys.com>
1518
1519         * arc-opc.c (insert_rbd): New function.
1520         (RBD): Define.
1521         (RBDdup): Likewise.
1522         * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
1523         instructions.
1524
1525 2020-07-07  Jan Beulich  <jbeulich@suse.com>
1526
1527         * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
1528         EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
1529         EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
1530         EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
1531         Delete.
1532         (putop): Handle "BW".
1533         * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
1534         0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
1535         and 0F3A3F ...
1536         * i386-dis-evex-prefix.h: ... here.
1537
1538 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1539
1540         * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
1541         (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
1542         VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
1543         VEX_W_0FXOP_09_83): New enumerators.
1544         (xop_table): Reference the above.
1545         (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
1546         (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
1547         VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
1548         (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
1549
1550 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1551
1552         * i386-dis.c (EVEX_W_0F3838_P_1,
1553         EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
1554         EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
1555         EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
1556         EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
1557         EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
1558         (putop): Centralize management of last[]. Delete SAVE_LAST.
1559         * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
1560         0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
1561         0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
1562         * i386-dis-evex-prefix.h: here.
1563
1564 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1565
1566         * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
1567         MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
1568         MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
1569         MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
1570         enumerators.
1571         (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
1572         EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
1573         EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
1574         EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
1575         (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
1576         EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
1577         EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1578         EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
1579         these, respectively.
1580         * i386-dis-evex-len.h: Adjust comments.
1581         * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
1582         MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1583         MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1584         MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
1585         MOD_EVEX_0F385B_P_2_W_1 table entries.
1586         * i386-dis-evex-w.h: Reference mod_table[] for
1587         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
1588         EVEX_W_0F385B_P_2.
1589
1590 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1591
1592         * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
1593         vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
1594         EXymm.
1595         (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
1596         Likewise. Mark 256-bit entries invalid.
1597
1598 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1599
1600         * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1601         PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1602         PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1603         PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1604         PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1605         PREFIX_EVEX_0F382B): Delete.
1606         (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
1607         EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
1608         EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
1609         EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
1610         EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
1611         to ...
1612         (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
1613         EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
1614         EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
1615         EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
1616         respectively.
1617         * i386-dis-evex.h (evex_table): Reference VEX_W table entries
1618         for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
1619         0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1620         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1621         PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1622         PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1623         PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1624         PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1625         PREFIX_EVEX_0F382B): Remove table entries.
1626         * i386-dis-evex-w.h: Reference VEX table entries for opcodes
1627         0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
1628         0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1629
1630 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1631
1632         * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
1633         EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
1634         enumerators.
1635         * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
1636         EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
1637         EVEX_LEN_0F3A01_P_2_W_1 table entries.
1638         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1639         entries.
1640
1641 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1642
1643         * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
1644         EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1645         EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1646         EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
1647         * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
1648         EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
1649         EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1650         EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
1651         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1652         entries.
1653
1654 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1655
1656         * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
1657         (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
1658         (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
1659         respectively.
1660         (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
1661         entries.
1662         * i386-dis-evex.h (evex_table): Reference VEX table entry for
1663         opcode 0F3A1D.
1664         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
1665         entry.
1666         * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
1667
1668 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1669
1670         * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1671         PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1672         PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1673         PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1674         PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1675         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1676         PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1677         PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1678         PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1679         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1680         PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1681         PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1682         PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1683         PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1684         PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1685         PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1686         PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1687         PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1688         PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1689         PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1690         PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1691         PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1692         PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1693         PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1694         PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1695         PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1696         PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1697         EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1698         EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1699         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1700         (prefix_table): Add EXxEVexR to FMA table entries.
1701         (OP_Rounding): Move abort() invocation.
1702         * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1703         0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1704         0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1705         0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1706         0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1707         0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1708         0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1709         0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1710         0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1711         0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1712         0F3ACE, 0F3ACF.
1713         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1714         PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1715         PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1716         PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1717         PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1718         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1719         PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1720         PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1721         PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1722         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1723         PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1724         PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1725         PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1726         PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1727         PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1728         PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1729         PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1730         PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1731         PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1732         PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1733         PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1734         PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1735         PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1736         PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1737         PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1738         PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1739         PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1740         Delete table entries.
1741         * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1742         EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1743         EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1744         Likewise.
1745
1746 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1747
1748         * i386-dis.c (EXqScalarS): Delete.
1749         (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1750         * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1751
1752 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1753
1754         * i386-dis.c (safe-ctype.h): Include.
1755         (EXdScalar, EXqScalar): Delete.
1756         (d_scalar_mode, q_scalar_mode): Delete.
1757         (prefix_table, vex_len_table): Use EXxmm_md in place of
1758         EXdScalar and EXxmm_mq in place of EXqScalar.
1759         (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1760         d_scalar_mode and q_scalar_mode.
1761         * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1762         (vmovsd): Use EXxmm_mq.
1763
1764 2020-07-06  Yuri Chornoivan  <yurchor@ukr.net>
1765
1766         PR 26204
1767         * arc-dis.c: Fix spelling mistake.
1768         * po/opcodes.pot: Regenerate.
1769
1770 2020-07-06  Nick Clifton  <nickc@redhat.com>
1771
1772         * po/pt_BR.po: Updated Brazilian Portugugese translation.
1773         * po/uk.po: Updated Ukranian translation.
1774
1775 2020-07-04  Nick Clifton  <nickc@redhat.com>
1776
1777         * configure: Regenerate.
1778         * po/opcodes.pot: Regenerate.
1779
1780 2020-07-04  Nick Clifton  <nickc@redhat.com>
1781
1782         Binutils 2.35 branch created.
1783
1784 2020-07-02  H.J. Lu  <hongjiu.lu@intel.com>
1785
1786         * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1787         * i386-opc.h (VexSwapSources): New.
1788         (i386_opcode_modifier): Add vexswapsources.
1789         * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1790         with two source operands swapped.
1791         * i386-tbl.h: Regenerated.
1792
1793 2020-06-30  Nelson Chu  <nelson.chu@sifive.com>
1794
1795         * riscv-dis.c (print_insn_args, case 'E'): Updated.  Let the
1796         unprivileged CSR can also be initialized.
1797
1798 2020-06-29  Alan Modra  <amodra@gmail.com>
1799
1800         * arm-dis.c: Use C style comments.
1801         * cr16-opc.c: Likewise.
1802         * ft32-dis.c: Likewise.
1803         * moxie-opc.c: Likewise.
1804         * tic54x-dis.c: Likewise.
1805         * s12z-opc.c: Remove useless comment.
1806         * xgate-dis.c: Likewise.
1807
1808 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
1809
1810         * i386-opc.tbl: Add a blank line.
1811
1812 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
1813
1814         * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1815         (VecSIB128): Renamed to ...
1816         (VECSIB128): This.
1817         (VecSIB256): Renamed to ...
1818         (VECSIB256): This.
1819         (VecSIB512): Renamed to ...
1820         (VECSIB512): This.
1821         (VecSIB): Renamed to ...
1822         (SIB): This.
1823         (i386_opcode_modifier): Replace vecsib with sib.
1824         * i386-opc.tbl (VecSIB128): New.
1825         (VecSIB256): Likewise.
1826         (VecSIB512): Likewise.
1827         Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
1828         and VecSIB512, respectively.
1829
1830 2020-06-26  Jan Beulich  <jbeulich@suse.com>
1831
1832         * i386-dis.c: Adjust description of I macro.
1833         (x86_64_table): Drop use of I.
1834         (float_mem): Replace use of I.
1835         (putop): Remove handling of I. Adjust setting/clearing of "alt".
1836
1837 2020-06-26  Jan Beulich  <jbeulich@suse.com>
1838
1839         * i386-dis.c: (print_insn): Avoid straight assignment to
1840         priv.orig_sizeflag when processing -M sub-options.
1841
1842 2020-06-25  Jan Beulich  <jbeulich@suse.com>
1843
1844         * i386-dis.c: Adjust description of J macro.
1845         (dis386, x86_64_table, mod_table): Replace J.
1846         (putop): Remove handling of J.
1847
1848 2020-06-25  Jan Beulich  <jbeulich@suse.com>
1849
1850         * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1851
1852 2020-06-25  Jan Beulich  <jbeulich@suse.com>
1853
1854         * i386-dis.c: Adjust description of "LQ" macro.
1855         (dis386_twobyte): Use LQ for sysret.
1856         (putop): Adjust handling of LQ.
1857
1858 2020-06-22  Nelson Chu  <nelson.chu@sifive.com>
1859
1860         * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1861         * riscv-dis.c: Include elfxx-riscv.h.
1862
1863 2020-06-18  H.J. Lu  <hongjiu.lu@intel.com>
1864
1865         * i386-dis.c (prefix_table): Revert the last vmgexit change.
1866
1867 2020-06-17  Lili Cui  <lili.cui@intel.com>
1868
1869         * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1870
1871 2020-06-14  H.J. Lu  <hongjiu.lu@intel.com>
1872
1873         PR gas/26115
1874         * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1875         * i386-opc.tbl: Likewise.
1876         * i386-tbl.h: Regenerated.
1877
1878 2020-06-12  Nelson Chu  <nelson.chu@sifive.com>
1879
1880         * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1881
1882 2020-06-11  Alex Coplan  <alex.coplan@arm.com>
1883
1884         * aarch64-opc.c (SYSREG): New macro for describing system registers.
1885         (SR_CORE): Likewise.
1886         (SR_FEAT): Likewise.
1887         (SR_RNG): Likewise.
1888         (SR_V8_1): Likewise.
1889         (SR_V8_2): Likewise.
1890         (SR_V8_3): Likewise.
1891         (SR_V8_4): Likewise.
1892         (SR_PAN): Likewise.
1893         (SR_RAS): Likewise.
1894         (SR_SSBS): Likewise.
1895         (SR_SVE): Likewise.
1896         (SR_ID_PFR2): Likewise.
1897         (SR_PROFILE): Likewise.
1898         (SR_MEMTAG): Likewise.
1899         (SR_SCXTNUM): Likewise.
1900         (aarch64_sys_regs): Refactor to store feature information in the table.
1901         (aarch64_sys_reg_supported_p): Collapse logic for system registers
1902         that now describe their own features.
1903         (aarch64_pstatefield_supported_p): Likewise.
1904
1905 2020-06-09  H.J. Lu  <hongjiu.lu@intel.com>
1906
1907         * i386-dis.c (prefix_table): Fix a typo in comments.
1908
1909 2020-06-09  Jan Beulich  <jbeulich@suse.com>
1910
1911         * i386-dis.c (rex_ignored): Delete.
1912         (ckprefix): Drop rex_ignored initialization.
1913         (get_valid_dis386): Drop setting of rex_ignored.
1914         (print_insn): Drop checking of rex_ignored. Don't record data
1915         size prefix as used with VEX-and-alike encodings.
1916
1917 2020-06-09  Jan Beulich  <jbeulich@suse.com>
1918
1919         * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1920         MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1921         (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1922         (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1923         (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1924         VEX_0F12, and VEX_0F16.
1925         (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1926         VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1927         (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1928         from movlps and movhlps. New MOD_0F12_PREFIX_2,
1929         MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1930         MOD_VEX_0F16_PREFIX_2 entries.
1931
1932 2020-06-09  Jan Beulich  <jbeulich@suse.com>
1933
1934         * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1935         MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1936         (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1937         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1938         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1939         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1940         EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1941         EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1942         EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1943         EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1944         EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1945         EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1946         EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1947         EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1948         EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1949         EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1950         EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1951         EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1952         EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1953         EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1954         EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1955         EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1956         EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1957         EVEX_W_0FC6_P_2): Delete.
1958         (print_insn): Add EVEX.W vs embedded prefix consistency check
1959         to prefix validation.
1960         * i386-dis-evex.h (evex_table): Don't further descend for
1961         vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1962         and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1963         and 0F2B.
1964         * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1965         * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1966         vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1967         vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1968         2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1969         Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1970         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1971         PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1972         PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1973         * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1974         EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1975         EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1976         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1977         EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1978         EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1979         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1980         EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1981         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1982         EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1983         EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1984         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1985         EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1986         EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1987         EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1988         EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1989         EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1990         EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1991
1992 2020-06-09  Jan Beulich  <jbeulich@suse.com>
1993
1994         * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1995         vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1996         (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1997         vmovmskpX.
1998         (print_insn): Drop pointless check against bad_opcode. Split
1999         prefix validation into legacy and VEX-and-alike parts.
2000         (putop): Re-work 'X' macro handling.
2001
2002 2020-06-09  Jan Beulich  <jbeulich@suse.com>
2003
2004         * i386-dis.c (MOD_0F51): Rename to ...
2005         (MOD_0F50): ... this.
2006
2007 2020-06-08  Alex Coplan  <alex.coplan@arm.com>
2008
2009         * arm-dis.c (arm_opcodes): Add dfb.
2010         (thumb32_opcodes): Add dfb.
2011
2012 2020-06-08  Jan Beulich  <jbeulich@suse.com>
2013
2014         * i386-opc.h (reg_entry): Const-qualify reg_name field.
2015
2016 2020-06-06  Alan Modra  <amodra@gmail.com>
2017
2018         * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
2019
2020 2020-06-05  Alan Modra  <amodra@gmail.com>
2021
2022         * cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
2023         size is large enough.
2024
2025 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
2026
2027         * disassemble.c (disassemble_init_for_target): Set endian_code for
2028         bpf targets.
2029         * bpf-desc.c: Regenerate.
2030         * bpf-opc.c: Likewise.
2031         * bpf-dis.c: Likewise.
2032
2033 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
2034
2035         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
2036         (cgen_put_insn_value): Likewise.
2037         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
2038         * cgen-dis.in (print_insn): Likewise.
2039         * cgen-ibld.in (insert_1): Likewise.
2040         (insert_1): Likewise.
2041         (insert_insn_normal): Likewise.
2042         (extract_1): Likewise.
2043         * bpf-dis.c: Regenerate.
2044         * bpf-ibld.c: Likewise.
2045         * bpf-ibld.c: Likewise.
2046         * cgen-dis.in: Likewise.
2047         * cgen-ibld.in: Likewise.
2048         * cgen-opc.c: Likewise.
2049         * epiphany-dis.c: Likewise.
2050         * epiphany-ibld.c: Likewise.
2051         * fr30-dis.c: Likewise.
2052         * fr30-ibld.c: Likewise.
2053         * frv-dis.c: Likewise.
2054         * frv-ibld.c: Likewise.
2055         * ip2k-dis.c: Likewise.
2056         * ip2k-ibld.c: Likewise.
2057         * iq2000-dis.c: Likewise.
2058         * iq2000-ibld.c: Likewise.
2059         * lm32-dis.c: Likewise.
2060         * lm32-ibld.c: Likewise.
2061         * m32c-dis.c: Likewise.
2062         * m32c-ibld.c: Likewise.
2063         * m32r-dis.c: Likewise.
2064         * m32r-ibld.c: Likewise.
2065         * mep-dis.c: Likewise.
2066         * mep-ibld.c: Likewise.
2067         * mt-dis.c: Likewise.
2068         * mt-ibld.c: Likewise.
2069         * or1k-dis.c: Likewise.
2070         * or1k-ibld.c: Likewise.
2071         * xc16x-dis.c: Likewise.
2072         * xc16x-ibld.c: Likewise.
2073         * xstormy16-dis.c: Likewise.
2074         * xstormy16-ibld.c: Likewise.
2075
2076 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
2077
2078         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
2079         (print_insn_): Handle instruction endian.
2080         * bpf-dis.c: Regenerate.
2081         * bpf-desc.c: Regenerate.
2082         * epiphany-dis.c: Likewise.
2083         * epiphany-desc.c: Likewise.
2084         * fr30-dis.c: Likewise.
2085         * fr30-desc.c: Likewise.
2086         * frv-dis.c: Likewise.
2087         * frv-desc.c: Likewise.
2088         * ip2k-dis.c: Likewise.
2089         * ip2k-desc.c: Likewise.
2090         * iq2000-dis.c: Likewise.
2091         * iq2000-desc.c: Likewise.
2092         * lm32-dis.c: Likewise.
2093         * lm32-desc.c: Likewise.
2094         * m32c-dis.c: Likewise.
2095         * m32c-desc.c: Likewise.
2096         * m32r-dis.c: Likewise.
2097         * m32r-desc.c: Likewise.
2098         * mep-dis.c: Likewise.
2099         * mep-desc.c: Likewise.
2100         * mt-dis.c: Likewise.
2101         * mt-desc.c: Likewise.
2102         * or1k-dis.c: Likewise.
2103         * or1k-desc.c: Likewise.
2104         * xc16x-dis.c: Likewise.
2105         * xc16x-desc.c: Likewise.
2106         * xstormy16-dis.c: Likewise.
2107         * xstormy16-desc.c: Likewise.
2108
2109 2020-06-03  Nick Clifton  <nickc@redhat.com>
2110
2111         * po/sr.po: Updated Serbian translation.
2112
2113 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
2114
2115         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
2116         (riscv_get_priv_spec_class): Likewise.
2117
2118 2020-06-01  Alan Modra  <amodra@gmail.com>
2119
2120         * bpf-desc.c: Regenerate.
2121
2122 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
2123             David Faust <david.faust@oracle.com>
2124
2125         * bpf-desc.c: Regenerate.
2126         * bpf-opc.h: Likewise.
2127         * bpf-opc.c: Likewise.
2128         * bpf-dis.c: Likewise.
2129
2130 2020-05-28  Alan Modra  <amodra@gmail.com>
2131
2132         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
2133         values.
2134
2135 2020-05-28  Alan Modra  <amodra@gmail.com>
2136
2137         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
2138         immediates.
2139         (print_insn_ns32k): Revert last change.
2140
2141 2020-05-28  Nick Clifton  <nickc@redhat.com>
2142
2143         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
2144         static.
2145
2146 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
2147
2148         Fix extraction of signed constants in nios2 disassembler (again).
2149
2150         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
2151         extractions of signed fields.
2152
2153 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
2154
2155         * s390-opc.txt: Relocate vector load/store instructions with
2156         additional alignment parameter and change architecture level
2157         constraint from z14 to z13.
2158
2159 2020-05-21  Alan Modra  <amodra@gmail.com>
2160
2161         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
2162         * sparc-dis.c: Likewise.
2163         * tic4x-dis.c: Likewise.
2164         * xtensa-dis.c: Likewise.
2165         * bpf-desc.c: Regenerate.
2166         * epiphany-desc.c: Regenerate.
2167         * fr30-desc.c: Regenerate.
2168         * frv-desc.c: Regenerate.
2169         * ip2k-desc.c: Regenerate.
2170         * iq2000-desc.c: Regenerate.
2171         * lm32-desc.c: Regenerate.
2172         * m32c-desc.c: Regenerate.
2173         * m32r-desc.c: Regenerate.
2174         * mep-asm.c: Regenerate.
2175         * mep-desc.c: Regenerate.
2176         * mt-desc.c: Regenerate.
2177         * or1k-desc.c: Regenerate.
2178         * xc16x-desc.c: Regenerate.
2179         * xstormy16-desc.c: Regenerate.
2180
2181 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
2182
2183         * riscv-opc.c (riscv_ext_version_table): The table used to store
2184         all information about the supported spec and the corresponding ISA
2185         versions.  Currently, only Zicsr is supported to verify the
2186         correctness of Z sub extension settings.  Others will be supported
2187         in the future patches.
2188         (struct isa_spec_t, isa_specs): List for all supported ISA spec
2189         classes and the corresponding strings.
2190         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
2191         spec class by giving a ISA spec string.
2192         * riscv-opc.c (struct priv_spec_t): New structure.
2193         (struct priv_spec_t priv_specs): List for all supported privilege spec
2194         classes and the corresponding strings.
2195         (riscv_get_priv_spec_class): New function.  Get the corresponding
2196         privilege spec class by giving a spec string.
2197         (riscv_get_priv_spec_name): New function.  Get the corresponding
2198         privilege spec string by giving a CSR version class.
2199         * riscv-dis.c: Updated since DECLARE_CSR is changed.
2200         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
2201         according to the chosen version.  Build a hash table riscv_csr_hash to
2202         store the valid CSR for the chosen pirv verison.  Dump the direct
2203         CSR address rather than it's name if it is invalid.
2204         (parse_riscv_dis_option_without_args): New function.  Parse the options
2205         without arguments.
2206         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
2207         parse the options without arguments first, and then handle the options
2208         with arguments.  Add the new option -Mpriv-spec, which has argument.
2209         * riscv-dis.c (print_riscv_disassembler_options): Add description
2210         about the new OBJDUMP option.
2211
2212 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
2213
2214         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
2215         WC values on POWER10 sync, dcbf  and wait instructions.
2216         (insert_pl, extract_pl): New functions.
2217         (L2OPT, LS, WC): Use insert_ls and extract_ls.
2218         (LS3): New , 3-bit L for sync.
2219         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
2220         (SC2, PL): New, 2-bit SC and PL for sync and wait.
2221         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
2222         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
2223         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
2224         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
2225         <wait>: Enable PL operand on POWER10.
2226         <dcbf>: Enable L3OPT operand on POWER10.
2227         <sync>: Enable SC2 operand on POWER10.
2228
2229 2020-05-19  Stafford Horne  <shorne@gmail.com>
2230
2231         PR 25184
2232         * or1k-asm.c: Regenerate.
2233         * or1k-desc.c: Regenerate.
2234         * or1k-desc.h: Regenerate.
2235         * or1k-dis.c: Regenerate.
2236         * or1k-ibld.c: Regenerate.
2237         * or1k-opc.c: Regenerate.
2238         * or1k-opc.h: Regenerate.
2239         * or1k-opinst.c: Regenerate.
2240
2241 2020-05-11  Alan Modra  <amodra@gmail.com>
2242
2243         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
2244         xsmaxcqp, xsmincqp.
2245
2246 2020-05-11  Alan Modra  <amodra@gmail.com>
2247
2248         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
2249         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
2250
2251 2020-05-11  Alan Modra  <amodra@gmail.com>
2252
2253         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
2254
2255 2020-05-11  Alan Modra  <amodra@gmail.com>
2256
2257         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
2258         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
2259
2260 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
2261
2262         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
2263         mnemonics.
2264
2265 2020-05-11  Alan Modra  <amodra@gmail.com>
2266
2267         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
2268         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
2269         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
2270         (prefix_opcodes): Add xxeval.
2271
2272 2020-05-11  Alan Modra  <amodra@gmail.com>
2273
2274         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
2275         xxgenpcvwm, xxgenpcvdm.
2276
2277 2020-05-11  Alan Modra  <amodra@gmail.com>
2278
2279         * ppc-opc.c (MP, VXVAM_MASK): Define.
2280         (VXVAPS_MASK): Use VXVA_MASK.
2281         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
2282         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
2283         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
2284         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
2285
2286 2020-05-11  Alan Modra  <amodra@gmail.com>
2287             Peter Bergner  <bergner@linux.ibm.com>
2288
2289         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
2290         New functions.
2291         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
2292         YMSK2, XA6a, XA6ap, XB6a entries.
2293         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
2294         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
2295         (PPCVSX4): Define.
2296         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
2297         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
2298         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
2299         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
2300         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
2301         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
2302         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
2303         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
2304         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
2305         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
2306         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
2307         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
2308         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
2309         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
2310
2311 2020-05-11  Alan Modra  <amodra@gmail.com>
2312
2313         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
2314         (insert_xts, extract_xts): New functions.
2315         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
2316         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
2317         (VXRC_MASK, VXSH_MASK): Define.
2318         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
2319         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
2320         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
2321         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
2322         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
2323         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
2324         xxblendvh, xxblendvw, xxblendvd, xxpermx.
2325
2326 2020-05-11  Alan Modra  <amodra@gmail.com>
2327
2328         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
2329         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
2330         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
2331         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
2332         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
2333
2334 2020-05-11  Alan Modra  <amodra@gmail.com>
2335
2336         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
2337         (XTP, DQXP, DQXP_MASK): Define.
2338         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
2339         (prefix_opcodes): Add plxvp and pstxvp.
2340
2341 2020-05-11  Alan Modra  <amodra@gmail.com>
2342
2343         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
2344         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
2345         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
2346
2347 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
2348
2349         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
2350
2351 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
2352
2353         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
2354         (L1OPT): Define.
2355         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
2356
2357 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
2358
2359         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
2360
2361 2020-05-11  Alan Modra  <amodra@gmail.com>
2362
2363         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
2364
2365 2020-05-11  Alan Modra  <amodra@gmail.com>
2366
2367         * ppc-dis.c (ppc_opts): Add "power10" entry.
2368         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
2369         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
2370
2371 2020-05-11  Nick Clifton  <nickc@redhat.com>
2372
2373         * po/fr.po: Updated French translation.
2374
2375 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
2376
2377         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
2378         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
2379         (operand_general_constraint_met_p): validate
2380         AARCH64_OPND_UNDEFINED.
2381         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
2382         for FLD_imm16_2.
2383         * aarch64-asm-2.c: Regenerated.
2384         * aarch64-dis-2.c: Regenerated.
2385         * aarch64-opc-2.c: Regenerated.
2386
2387 2020-04-29  Nick Clifton  <nickc@redhat.com>
2388
2389         PR 22699
2390         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
2391         and SETRC insns.
2392
2393 2020-04-29  Nick Clifton  <nickc@redhat.com>
2394
2395         * po/sv.po: Updated Swedish translation.
2396
2397 2020-04-29  Nick Clifton  <nickc@redhat.com>
2398
2399         PR 22699
2400         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
2401         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
2402         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
2403         IMM0_8U case.
2404
2405 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
2406
2407         PR 25848
2408         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
2409         cmpi only on m68020up and cpu32.
2410
2411 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
2412
2413         * aarch64-asm.c (aarch64_ins_none): New.
2414         * aarch64-asm.h (ins_none): New declaration.
2415         * aarch64-dis.c (aarch64_ext_none): New.
2416         * aarch64-dis.h (ext_none): New declaration.
2417         * aarch64-opc.c (aarch64_print_operand): Update case for
2418         AARCH64_OPND_BARRIER_PSB.
2419         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
2420         (AARCH64_OPERANDS): Update inserter/extracter for
2421         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
2422         * aarch64-asm-2.c: Regenerated.
2423         * aarch64-dis-2.c: Regenerated.
2424         * aarch64-opc-2.c: Regenerated.
2425
2426 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
2427
2428         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
2429         (aarch64_feature_ras, RAS): Likewise.
2430         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
2431         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
2432         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
2433         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
2434         * aarch64-asm-2.c: Regenerated.
2435         * aarch64-dis-2.c: Regenerated.
2436         * aarch64-opc-2.c: Regenerated.
2437
2438 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
2439
2440         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
2441         (print_insn_neon): Support disassembly of conditional
2442         instructions.
2443
2444 2020-02-16  David Faust  <david.faust@oracle.com>
2445
2446         * bpf-desc.c: Regenerate.
2447         * bpf-desc.h: Likewise.
2448         * bpf-opc.c: Regenerate.
2449         * bpf-opc.h: Likewise.
2450
2451 2020-04-07  Lili Cui  <lili.cui@intel.com>
2452
2453         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
2454         (prefix_table): New instructions (see prefixes above).
2455         (rm_table): Likewise
2456         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
2457         CPU_ANY_TSXLDTRK_FLAGS.
2458         (cpu_flags): Add CpuTSXLDTRK.
2459         * i386-opc.h (enum): Add CpuTSXLDTRK.
2460         (i386_cpu_flags): Add cputsxldtrk.
2461         * i386-opc.tbl: Add XSUSPLDTRK insns.
2462         * i386-init.h: Regenerate.
2463         * i386-tbl.h: Likewise.
2464
2465 2020-04-02  Lili Cui  <lili.cui@intel.com>
2466
2467         * i386-dis.c (prefix_table): New instructions serialize.
2468         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
2469         CPU_ANY_SERIALIZE_FLAGS.
2470         (cpu_flags): Add CpuSERIALIZE.
2471         * i386-opc.h (enum): Add CpuSERIALIZE.
2472         (i386_cpu_flags): Add cpuserialize.
2473         * i386-opc.tbl: Add SERIALIZE insns.
2474         * i386-init.h: Regenerate.
2475         * i386-tbl.h: Likewise.
2476
2477 2020-03-26  Alan Modra  <amodra@gmail.com>
2478
2479         * disassemble.h (opcodes_assert): Declare.
2480         (OPCODES_ASSERT): Define.
2481         * disassemble.c: Don't include assert.h.  Include opintl.h.
2482         (opcodes_assert): New function.
2483         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
2484         (bfd_h8_disassemble): Reduce size of data array.  Correctly
2485         calculate maxlen.  Omit insn decoding when insn length exceeds
2486         maxlen.  Exit from nibble loop when looking for E, before
2487         accessing next data byte.  Move processing of E outside loop.
2488         Replace tests of maxlen in loop with assertions.
2489
2490 2020-03-26  Alan Modra  <amodra@gmail.com>
2491
2492         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
2493
2494 2020-03-25  Alan Modra  <amodra@gmail.com>
2495
2496         * z80-dis.c (suffix): Init mybuf.
2497
2498 2020-03-22  Alan Modra  <amodra@gmail.com>
2499
2500         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
2501         successflly read from section.
2502
2503 2020-03-22  Alan Modra  <amodra@gmail.com>
2504
2505         * arc-dis.c (find_format): Use ISO C string concatenation rather
2506         than line continuation within a string.  Don't access needs_limm
2507         before testing opcode != NULL.
2508
2509 2020-03-22  Alan Modra  <amodra@gmail.com>
2510
2511         * ns32k-dis.c (print_insn_arg): Update comment.
2512         (print_insn_ns32k): Reduce size of index_offset array, and
2513         initialize, passing -1 to print_insn_arg for args that are not
2514         an index.  Don't exit arg loop early.  Abort on bad arg number.
2515
2516 2020-03-22  Alan Modra  <amodra@gmail.com>
2517
2518         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
2519         * s12z-opc.c: Formatting.
2520         (operands_f): Return an int.
2521         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
2522         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
2523         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
2524         (exg_sex_discrim): Likewise.
2525         (create_immediate_operand, create_bitfield_operand),
2526         (create_register_operand_with_size, create_register_all_operand),
2527         (create_register_all16_operand, create_simple_memory_operand),
2528         (create_memory_operand, create_memory_auto_operand): Don't
2529         segfault on malloc failure.
2530         (z_ext24_decode): Return an int status, negative on fail, zero
2531         on success.
2532         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
2533         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
2534         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
2535         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
2536         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
2537         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
2538         (loop_primitive_decode, shift_decode, psh_pul_decode),
2539         (bit_field_decode): Similarly.
2540         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
2541         to return value, update callers.
2542         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
2543         Don't segfault on NULL operand.
2544         (decode_operation): Return OP_INVALID on first fail.
2545         (decode_s12z): Check all reads, returning -1 on fail.
2546
2547 2020-03-20  Alan Modra  <amodra@gmail.com>
2548
2549         * metag-dis.c (print_insn_metag): Don't ignore status from
2550         read_memory_func.
2551
2552 2020-03-20  Alan Modra  <amodra@gmail.com>
2553
2554         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
2555         Initialize parts of buffer not written when handling a possible
2556         2-byte insn at end of section.  Don't attempt decoding of such
2557         an insn by the 4-byte machinery.
2558
2559 2020-03-20  Alan Modra  <amodra@gmail.com>
2560
2561         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
2562         partially filled buffer.  Prevent lookup of 4-byte insns when
2563         only VLE 2-byte insns are possible due to section size.  Print
2564         ".word" rather than ".long" for 2-byte leftovers.
2565
2566 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
2567
2568         PR 25641
2569         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
2570
2571 2020-03-13  Jan Beulich  <jbeulich@suse.com>
2572
2573         * i386-dis.c (X86_64_0D): Rename to ...
2574         (X86_64_0E): ... this.
2575
2576 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
2577
2578         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
2579         * Makefile.in: Regenerated.
2580
2581 2020-03-09  Jan Beulich  <jbeulich@suse.com>
2582
2583         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
2584         3-operand pseudos.
2585         * i386-tbl.h: Re-generate.
2586
2587 2020-03-09  Jan Beulich  <jbeulich@suse.com>
2588
2589         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
2590         vprot*, vpsha*, and vpshl*.
2591         * i386-tbl.h: Re-generate.
2592
2593 2020-03-09  Jan Beulich  <jbeulich@suse.com>
2594
2595         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
2596         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
2597         * i386-tbl.h: Re-generate.
2598
2599 2020-03-09  Jan Beulich  <jbeulich@suse.com>
2600
2601         * i386-gen.c (set_bitfield): Ignore zero-length field names.
2602         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
2603         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
2604         * i386-tbl.h: Re-generate.
2605
2606 2020-03-09  Jan Beulich  <jbeulich@suse.com>
2607
2608         * i386-gen.c (struct template_arg, struct template_instance,
2609         struct template_param, struct template, templates,
2610         parse_template, expand_templates): New.
2611         (process_i386_opcodes): Various local variables moved to
2612         expand_templates. Call parse_template and expand_templates.
2613         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
2614         * i386-tbl.h: Re-generate.
2615
2616 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2617
2618         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
2619         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
2620         register and memory source templates. Replace VexW= by VexW*
2621         where applicable.
2622         * i386-tbl.h: Re-generate.
2623
2624 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2625
2626         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
2627         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
2628         * i386-tbl.h: Re-generate.
2629
2630 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2631
2632         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
2633         * i386-tbl.h: Re-generate.
2634
2635 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2636
2637         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2638         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
2639         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
2640         VexW0 on SSE2AVX variants.
2641         (vmovq): Drop NoRex64 from XMM/XMM variants.
2642         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
2643         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
2644         applicable use VexW0.
2645         * i386-tbl.h: Re-generate.
2646
2647 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2648
2649         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
2650         * i386-opc.h (Rex64): Delete.
2651         (struct i386_opcode_modifier): Remove rex64 field.
2652         * i386-opc.tbl (crc32): Drop Rex64.
2653         Replace Rex64 with Size64 everywhere else.
2654         * i386-tbl.h: Re-generate.
2655
2656 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2657
2658         * i386-dis.c (OP_E_memory): Exclude recording of used address
2659         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
2660         addressed memory operands for MPX insns.
2661
2662 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2663
2664         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
2665         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
2666         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
2667         (ptwrite): Split into non-64-bit and 64-bit forms.
2668         * i386-tbl.h: Re-generate.
2669
2670 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2671
2672         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
2673         template.
2674         * i386-tbl.h: Re-generate.
2675
2676 2020-03-04  Jan Beulich  <jbeulich@suse.com>
2677
2678         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2679         (prefix_table): Move vmmcall here. Add vmgexit.
2680         (rm_table): Replace vmmcall entry by prefix_table[] escape.
2681         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2682         (cpu_flags): Add CpuSEV_ES entry.
2683         * i386-opc.h (CpuSEV_ES): New.
2684         (union i386_cpu_flags): Add cpusev_es field.
2685         * i386-opc.tbl (vmgexit): New.
2686         * i386-init.h, i386-tbl.h: Re-generate.
2687
2688 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
2689
2690         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2691         with MnemonicSize.
2692         * i386-opc.h (IGNORESIZE): New.
2693         (DEFAULTSIZE): Likewise.
2694         (IgnoreSize): Removed.
2695         (DefaultSize): Likewise.
2696         (MnemonicSize): New.
2697         (i386_opcode_modifier): Replace ignoresize/defaultsize with
2698         mnemonicsize.
2699         * i386-opc.tbl (IgnoreSize): New.
2700         (DefaultSize): Likewise.
2701         * i386-tbl.h: Regenerated.
2702
2703 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
2704
2705         PR 25627
2706         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2707         instructions.
2708
2709 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
2710
2711         PR gas/25622
2712         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2713         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2714         * i386-tbl.h: Regenerated.
2715
2716 2020-02-26  Alan Modra  <amodra@gmail.com>
2717
2718         * aarch64-asm.c: Indent labels correctly.
2719         * aarch64-dis.c: Likewise.
2720         * aarch64-gen.c: Likewise.
2721         * aarch64-opc.c: Likewise.
2722         * alpha-dis.c: Likewise.
2723         * i386-dis.c: Likewise.
2724         * nds32-asm.c: Likewise.
2725         * nfp-dis.c: Likewise.
2726         * visium-dis.c: Likewise.
2727
2728 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
2729
2730         * arc-regs.h (int_vector_base): Make it available for all ARC
2731         CPUs.
2732
2733 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
2734
2735         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2736         changed.
2737
2738 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
2739
2740         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2741         c.mv/c.li if rs1 is zero.
2742
2743 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
2744
2745         * i386-gen.c (cpu_flag_init): Replace CpuABM with
2746         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
2747         CPU_POPCNT_FLAGS.
2748         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
2749         * i386-opc.h (CpuABM): Removed.
2750         (CpuPOPCNT): New.
2751         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
2752         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2753         popcnt.  Remove CpuABM from lzcnt.
2754         * i386-init.h: Regenerated.
2755         * i386-tbl.h: Likewise.
2756
2757 2020-02-17  Jan Beulich  <jbeulich@suse.com>
2758
2759         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2760         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2761         VexW1 instead of open-coding them.
2762         * i386-tbl.h: Re-generate.
2763
2764 2020-02-17  Jan Beulich  <jbeulich@suse.com>
2765
2766         * i386-opc.tbl (AddrPrefixOpReg): Define.
2767         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2768         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2769         templates. Drop NoRex64.
2770         * i386-tbl.h: Re-generate.
2771
2772 2020-02-17  Jan Beulich  <jbeulich@suse.com>
2773
2774         PR gas/6518
2775         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2776         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2777         into Intel syntax instance (with Unpsecified) and AT&T one
2778         (without).
2779         (vcvtneps2bf16): Likewise, along with folding the two so far
2780         separate ones.
2781         * i386-tbl.h: Re-generate.
2782
2783 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
2784
2785         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2786         CPU_ANY_SSE4A_FLAGS.
2787
2788 2020-02-17  Alan Modra  <amodra@gmail.com>
2789
2790         * i386-gen.c (cpu_flag_init): Correct last change.
2791
2792 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
2793
2794         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
2795         CPU_ANY_SSE4_FLAGS.
2796
2797 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
2798
2799         * i386-opc.tbl (movsx): Remove Intel syntax comments.
2800         (movzx): Likewise.
2801
2802 2020-02-14  Jan Beulich  <jbeulich@suse.com>
2803
2804         PR gas/25438
2805         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2806         destination for Cpu64-only variant.
2807         (movzx): Fold patterns.
2808         * i386-tbl.h: Re-generate.
2809
2810 2020-02-13  Jan Beulich  <jbeulich@suse.com>
2811
2812         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2813         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2814         CPU_ANY_SSE4_FLAGS entry.
2815         * i386-init.h: Re-generate.
2816
2817 2020-02-12  Jan Beulich  <jbeulich@suse.com>
2818
2819         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2820         with Unspecified, making the present one AT&T syntax only.
2821         * i386-tbl.h: Re-generate.
2822
2823 2020-02-12  Jan Beulich  <jbeulich@suse.com>
2824
2825         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2826         * i386-tbl.h: Re-generate.
2827
2828 2020-02-12  Jan Beulich  <jbeulich@suse.com>
2829
2830         PR gas/24546
2831         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2832         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2833         Amd64 and Intel64 templates.
2834         (call, jmp): Likewise for far indirect variants. Dro
2835         Unspecified.
2836         * i386-tbl.h: Re-generate.
2837
2838 2020-02-11  Jan Beulich  <jbeulich@suse.com>
2839
2840         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2841         * i386-opc.h (ShortForm): Delete.
2842         (struct i386_opcode_modifier): Remove shortform field.
2843         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2844         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2845         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2846         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2847         Drop ShortForm.
2848         * i386-tbl.h: Re-generate.
2849
2850 2020-02-11  Jan Beulich  <jbeulich@suse.com>
2851
2852         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2853         fucompi): Drop ShortForm from operand-less templates.
2854         * i386-tbl.h: Re-generate.
2855
2856 2020-02-11  Alan Modra  <amodra@gmail.com>
2857
2858         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2859         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2860         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2861         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2862         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2863
2864 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
2865
2866         * arm-dis.c (print_insn_cde): Define 'V' parse character.
2867         (cde_opcodes): Add VCX* instructions.
2868
2869 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
2870             Matthew Malcomson  <matthew.malcomson@arm.com>
2871
2872         * arm-dis.c (struct cdeopcode32): New.
2873         (CDE_OPCODE): New macro.
2874         (cde_opcodes): New disassembly table.
2875         (regnames): New option to table.
2876         (cde_coprocs): New global variable.
2877         (print_insn_cde): New
2878         (print_insn_thumb32): Use print_insn_cde.
2879         (parse_arm_disassembler_options): Parse coprocN args.
2880
2881 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
2882
2883         PR gas/25516
2884         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2885         with ISA64.
2886         * i386-opc.h (AMD64): Removed.
2887         (Intel64): Likewose.
2888         (AMD64): New.
2889         (INTEL64): Likewise.
2890         (INTEL64ONLY): Likewise.
2891         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2892         * i386-opc.tbl (Amd64): New.
2893         (Intel64): Likewise.
2894         (Intel64Only): Likewise.
2895         Replace AMD64 with Amd64.  Update sysenter/sysenter with
2896         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
2897         * i386-tbl.h: Regenerated.
2898
2899 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
2900
2901         PR 25469
2902         * z80-dis.c: Add support for GBZ80 opcodes.
2903
2904 2020-02-04  Alan Modra  <amodra@gmail.com>
2905
2906         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2907
2908 2020-02-03  Alan Modra  <amodra@gmail.com>
2909
2910         * m32c-ibld.c: Regenerate.
2911
2912 2020-02-01  Alan Modra  <amodra@gmail.com>
2913
2914         * frv-ibld.c: Regenerate.
2915
2916 2020-01-31  Jan Beulich  <jbeulich@suse.com>
2917
2918         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2919         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2920         (OP_E_memory): Replace xmm_mdq_mode case label by
2921         vex_scalar_w_dq_mode one.
2922         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2923
2924 2020-01-31  Jan Beulich  <jbeulich@suse.com>
2925
2926         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2927         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2928         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2929         (intel_operand_size): Drop vex_w_dq_mode case label.
2930
2931 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
2932
2933         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2934         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2935
2936 2020-01-30  Alan Modra  <amodra@gmail.com>
2937
2938         * m32c-ibld.c: Regenerate.
2939
2940 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
2941
2942         * bpf-opc.c: Regenerate.
2943
2944 2020-01-30  Jan Beulich  <jbeulich@suse.com>
2945
2946         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2947         (dis386): Use them to replace C2/C3 table entries.
2948         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2949         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2950         ones. Use Size64 instead of DefaultSize on Intel64 ones.
2951         * i386-tbl.h: Re-generate.
2952
2953 2020-01-30  Jan Beulich  <jbeulich@suse.com>
2954
2955         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2956         forms.
2957         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2958         DefaultSize.
2959         * i386-tbl.h: Re-generate.
2960
2961 2020-01-30  Alan Modra  <amodra@gmail.com>
2962
2963         * tic4x-dis.c (tic4x_dp): Make unsigned.
2964
2965 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
2966             Jan Beulich  <jbeulich@suse.com>
2967
2968         PR binutils/25445
2969         * i386-dis.c (MOVSXD_Fixup): New function.
2970         (movsxd_mode): New enum.
2971         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2972         (intel_operand_size): Handle movsxd_mode.
2973         (OP_E_register): Likewise.
2974         (OP_G): Likewise.
2975         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2976         register on movsxd.  Add movsxd with 16-bit destination register
2977         for AMD64 and Intel64 ISAs.
2978         * i386-tbl.h: Regenerated.
2979
2980 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
2981
2982         PR 25403
2983         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2984         * aarch64-asm-2.c: Regenerate
2985         * aarch64-dis-2.c: Likewise.
2986         * aarch64-opc-2.c: Likewise.
2987
2988 2020-01-21  Jan Beulich  <jbeulich@suse.com>
2989
2990         * i386-opc.tbl (sysret): Drop DefaultSize.
2991         * i386-tbl.h: Re-generate.
2992
2993 2020-01-21  Jan Beulich  <jbeulich@suse.com>
2994
2995         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2996         Dword.
2997         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2998         * i386-tbl.h: Re-generate.
2999
3000 2020-01-20  Nick Clifton  <nickc@redhat.com>
3001
3002         * po/de.po: Updated German translation.
3003         * po/pt_BR.po: Updated Brazilian Portuguese translation.
3004         * po/uk.po: Updated Ukranian translation.
3005
3006 2020-01-20  Alan Modra  <amodra@gmail.com>
3007
3008         * hppa-dis.c (fput_const): Remove useless cast.
3009
3010 2020-01-20  Alan Modra  <amodra@gmail.com>
3011
3012         * arm-dis.c (print_insn_arm): Wrap 'T' value.
3013
3014 2020-01-18  Nick Clifton  <nickc@redhat.com>
3015
3016         * configure: Regenerate.
3017         * po/opcodes.pot: Regenerate.
3018
3019 2020-01-18  Nick Clifton  <nickc@redhat.com>
3020
3021         Binutils 2.34 branch created.
3022
3023 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
3024
3025         * opintl.h: Fix spelling error (seperate).
3026
3027 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
3028
3029         * i386-opc.tbl: Add {vex} pseudo prefix.
3030         * i386-tbl.h: Regenerated.
3031
3032 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
3033
3034         PR 25376
3035         * arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
3036         (neon_opcodes): Likewise.
3037         (select_arm_features): Make sure we enable MVE bits when selecting
3038         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
3039         any architecture.
3040
3041 2020-01-16  Jan Beulich  <jbeulich@suse.com>
3042
3043         * i386-opc.tbl: Drop stale comment from XOP section.
3044
3045 2020-01-16  Jan Beulich  <jbeulich@suse.com>
3046
3047         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
3048         (extractps): Add VexWIG to SSE2AVX forms.
3049         * i386-tbl.h: Re-generate.
3050
3051 2020-01-16  Jan Beulich  <jbeulich@suse.com>
3052
3053         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
3054         Size64 from and use VexW1 on SSE2AVX forms.
3055         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
3056         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
3057         * i386-tbl.h: Re-generate.
3058
3059 2020-01-15  Alan Modra  <amodra@gmail.com>
3060
3061         * tic4x-dis.c (tic4x_version): Make unsigned long.
3062         (optab, optab_special, registernames): New file scope vars.
3063         (tic4x_print_register): Set up registernames rather than
3064         malloc'd registertable.
3065         (tic4x_disassemble): Delete optable and optable_special.  Use
3066         optab and optab_special instead.  Throw away old optab,
3067         optab_special and registernames when info->mach changes.
3068
3069 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
3070
3071         PR 25377
3072         * z80-dis.c (suffix): Use .db instruction to generate double
3073         prefix.
3074
3075 2020-01-14  Alan Modra  <amodra@gmail.com>
3076
3077         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
3078         values to unsigned before shifting.
3079
3080 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
3081
3082         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
3083         flow instructions.
3084         (print_insn_thumb16, print_insn_thumb32): Likewise.
3085         (print_insn): Initialize the insn info.
3086         * i386-dis.c (print_insn): Initialize the insn info fields, and
3087         detect jumps.
3088
3089 2020-01-13  Claudiu Zissulescu <claziss@gmail.com>
3090
3091         * arc-opc.c (C_NE): Make it required.
3092
3093 2020-01-13  Claudiu Zissulescu <claziss@gmail.com>
3094
3095         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
3096         reserved register name.
3097
3098 2020-01-13  Alan Modra  <amodra@gmail.com>
3099
3100         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
3101         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
3102
3103 2020-01-13  Alan Modra  <amodra@gmail.com>
3104
3105         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
3106         result of wasm_read_leb128 in a uint64_t and check that bits
3107         are not lost when copying to other locals.  Use uint32_t for
3108         most locals.  Use PRId64 when printing int64_t.
3109
3110 2020-01-13  Alan Modra  <amodra@gmail.com>
3111
3112         * score-dis.c: Formatting.
3113         * score7-dis.c: Formatting.
3114
3115 2020-01-13  Alan Modra  <amodra@gmail.com>
3116
3117         * score-dis.c (print_insn_score48): Use unsigned variables for
3118         unsigned values.  Don't left shift negative values.
3119         (print_insn_score32): Likewise.
3120         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
3121
3122 2020-01-13  Alan Modra  <amodra@gmail.com>
3123
3124         * tic4x-dis.c (tic4x_print_register): Remove dead code.
3125
3126 2020-01-13  Alan Modra  <amodra@gmail.com>
3127
3128         * fr30-ibld.c: Regenerate.
3129
3130 2020-01-13  Alan Modra  <amodra@gmail.com>
3131
3132         * xgate-dis.c (print_insn): Don't left shift signed value.
3133         (ripBits): Formatting, use 1u.
3134
3135 2020-01-10  Alan Modra  <amodra@gmail.com>
3136
3137         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
3138         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
3139
3140 2020-01-10  Alan Modra  <amodra@gmail.com>
3141
3142         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
3143         and XRREG value earlier to avoid a shift with negative exponent.
3144         * m10200-dis.c (disassemble): Similarly.
3145
3146 2020-01-09  Nick Clifton  <nickc@redhat.com>
3147
3148         PR 25224
3149         * z80-dis.c (ld_ii_ii): Use correct cast.
3150
3151 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
3152
3153         PR 25224
3154         * z80-dis.c (ld_ii_ii): Use character constant when checking
3155         opcode byte value.
3156
3157 2020-01-09  Jan Beulich  <jbeulich@suse.com>
3158
3159         * i386-dis.c (SEP_Fixup): New.
3160         (SEP): Define.
3161         (dis386_twobyte): Use it for sysenter/sysexit.
3162         (enum x86_64_isa): Change amd64 enumerator to value 1.
3163         (OP_J): Compare isa64 against intel64 instead of amd64.
3164         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
3165         forms.
3166         * i386-tbl.h: Re-generate.
3167
3168 2020-01-08  Alan Modra  <amodra@gmail.com>
3169
3170         * z8k-dis.c: Include libiberty.h
3171         (instr_data_s): Make max_fetched unsigned.
3172         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
3173         Don't exceed byte_info bounds.
3174         (output_instr): Make num_bytes unsigned.
3175         (unpack_instr): Likewise for nibl_count and loop.
3176         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
3177         idx unsigned.
3178         * z8k-opc.h: Regenerate.
3179
3180 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
3181
3182         * arc-tbl.h (llock): Use 'LLOCK' as class.
3183         (llockd): Likewise.
3184         (scond): Use 'SCOND' as class.
3185         (scondd): Likewise.
3186         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
3187         (scondd): Likewise.
3188
3189 2020-01-06  Alan Modra  <amodra@gmail.com>
3190
3191         * m32c-ibld.c: Regenerate.
3192
3193 2020-01-06  Alan Modra  <amodra@gmail.com>
3194
3195         PR 25344
3196         * z80-dis.c (suffix): Don't use a local struct buffer copy.
3197         Peek at next byte to prevent recursion on repeated prefix bytes.
3198         Ensure uninitialised "mybuf" is not accessed.
3199         (print_insn_z80): Don't zero n_fetch and n_used here,..
3200         (print_insn_z80_buf): ..do it here instead.
3201
3202 2020-01-04  Alan Modra  <amodra@gmail.com>
3203
3204         * m32r-ibld.c: Regenerate.
3205
3206 2020-01-04  Alan Modra  <amodra@gmail.com>
3207
3208         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
3209
3210 2020-01-04  Alan Modra  <amodra@gmail.com>
3211
3212         * crx-dis.c (match_opcode): Avoid shift left of signed value.
3213
3214 2020-01-04  Alan Modra  <amodra@gmail.com>
3215
3216         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
3217
3218 2020-01-03  Jan Beulich  <jbeulich@suse.com>
3219
3220         * aarch64-tbl.h (aarch64_opcode_table): Use
3221         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
3222
3223 2020-01-03  Jan Beulich  <jbeulich@suse.com>
3224
3225         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
3226         forms of SUDOT and USDOT.
3227
3228 2020-01-03  Jan Beulich  <jbeulich@suse.com>
3229
3230         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
3231         uzip{1,2}.
3232         * aarch64-dis-2.c: Re-generate.
3233
3234 2020-01-03  Jan Beulich  <jbeulich@suse.com>
3235
3236         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
3237         FMMLA encoding.
3238         * aarch64-dis-2.c: Re-generate.
3239
3240 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
3241
3242         * z80-dis.c: Add support for eZ80 and Z80 instructions.
3243
3244 2020-01-01  Alan Modra  <amodra@gmail.com>
3245
3246         Update year range in copyright notice of all files.
3247
3248 For older changes see ChangeLog-2019
3249 \f
3250 Copyright (C) 2020 Free Software Foundation, Inc.
3251
3252 Copying and distribution of this file, with or without modification,
3253 are permitted in any medium without royalty provided the copyright
3254 notice and this notice are preserved.
3255
3256 Local Variables:
3257 mode: change-log
3258 left-margin: 8
3259 fill-column: 74
3260 version-control: never
3261 End: