opcodes/ChangeLog

   1 2013-09-30  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
   2
   3         * i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS.
   4         * i386-init.h: Regenerated.
   5
   6 2013-09-20  Alan Modra  <amodra@gmail.com>
   7
   8         * configure: Regenerate.
   9
  10 2013-09-17  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
  11
  12         * s390-opc.txt (clih): Make the immediate unsigned.
  13
  14 2013-09-04  Roland McGrath  <mcgrathr@google.com>
  15
  16         PR gas/15914
  17         * arm-dis.c (arm_opcodes): Add udf.
  18         (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
  19         (thumb32_opcodes): Add udf.w.
  20         (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
  21
  22 2013-09-02  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  23
  24         * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
  25         For the load fp integer instructions only the suppression flag was
  26         new with z196 version.
  27
  28 2013-08-28  Nick Clifton  <nickc@redhat.com>
  29
  30         * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
  31         immediate is not suitable for the 32-bit ABI.
  32
  33 2013-08-23  Maciej W. Rozycki  <macro@codesourcery.com>
  34
  35         * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
  36         replacing NODS.
  37
  38 2013-08-23  Yuri Chornoivan  <yurchor@ukr.net>
  39
  40         PR binutils/15834
  41         * aarch64-asm.c: Fix typos.
  42         * aarch64-dis.c: Likewise.
  43         * msp430-dis.c: Likewise.
  44
  45 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
  46
  47         * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
  48         macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
  49         Use +H rather than +C for the real "dext".
  50         * mips-opc.c (mips_builtin_opcodes): Likewise.
  51
  52 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
  53
  54         * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
  55         * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
  56         and OPTIONAL_MAPPED_REG.
  57         * mips-opc.c (decode_mips_operand): Likewise.
  58         * mips16-opc.c (decode_mips16_operand): Likewise.
  59         * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
  60
  61 2013-08-19  H.J. Lu  <hongjiu.lu@intel.com>
  62
  63         * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
  64         (PREFIX_EVEX_0F3A3F): Likewise.
  65         * i386-dis-evex.h (evex_table): Updated.
  66
  67 2013-08-06  Jürgen Urban  <JuergenUrban@gmx.de>
  68
  69         * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
  70         VCLIPW.
  71
  72 2013-08-05  Eric Botcazou  <ebotcazou@adacore.com>
  73             Konrad Eisele  <konrad@gaisler.com>
  74
  75         * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
  76         bfd_mach_sparc.
  77         * sparc-opc.c (MASK_LEON): Define.
  78         (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
  79         (letandleon): New macro.
  80         (v9andleon): Likewise.
  81         (sparc_opc): Add leon.
  82         (umac): Enable for letandleon.
  83         (smac): Likewise.
  84         (casa): Enable for v9andleon.
  85         (cas): Likewise.
  86         (casl): Likewise.
  87
  88 2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
  89             Richard Sandiford  <rdsandiford@googlemail.com>
  90
  91         * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
  92         OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
  93         (print_vu0_channel): New function.
  94         (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
  95         (print_insn_args): Handle '#'.
  96         (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
  97         * mips-opc.c (mips_vu0_channel_mask): New constant.
  98         (decode_mips_operand): Handle new VU0 operand types.
  99         (VU0, VU0CH): New macros.
 100         (mips_builtin_opcodes): Add VU0 opcodes.  Use "+7" rather than "E"
 101         for LQC2 and SQC2.  Use "+9" rather than "G" for EE CFC2 and CTC2.
 102         Use "+6" rather than "G" for QMFC2 and QMTC2.
 103
 104 2013-08-03  Richard Sandiford  <rdsandiford@googlemail.com>
 105
 106         * mips-formats.h (PCREL): Reorder parameters and update the definition
 107         to match new mips_pcrel_operand layout.
 108         (JUMP, JALX, BRANCH): Update accordingly.
 109         * mips16-opc.c (decode_mips16_operand): Likewise.
 110
 111 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 112
 113         * micromips-opc.c (WR_s): Delete.
 114
 115 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 116
 117         * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
 118         New macros.
 119         (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
 120         (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
 121         (mips_builtin_opcodes): Use the new position-based read-write flags
 122         instead of field-based ones.  Use UDI for "udi..." instructions.
 123         * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
 124         New macros.
 125         (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
 126         (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
 127         (WR_SP, RD_16): New macros.
 128         (RD_SP): Redefine as an INSN2_* flag.
 129         (MOD_SP): Redefine in terms of RD_SP and WR_SP.
 130         (mips16_opcodes): Use the new position-based read-write flags
 131         instead of field-based ones.  Use RD_16 for "nop".  Move RD_SP to
 132         pinfo2 field.
 133         * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
 134         New macros.
 135         (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
 136         (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
 137         (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
 138         (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
 139         (micromips_opcodes): Use the new position-based read-write flags
 140         instead of field-based ones.
 141         * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
 142         (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
 143         of field-based flags.
 144
 145 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 146
 147         * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
 148         (WR_SP): Replace with...
 149         (MOD_SP): ...this.
 150         (mips16_opcodes): Update accordingly.
 151         * mips-dis.c (print_insn_mips16): Likewise.
 152
 153 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 154
 155         * mips16-opc.c (mips16_opcodes): Reformat.
 156
 157 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 158
 159         * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
 160         for operands that are hard-coded to $0.
 161         * micromips-opc.c (micromips_opcodes): Likewise.
 162
 163 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 164
 165         * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
 166         for the single-operand forms of JALR and JALR.HB.
 167         * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
 168         and JALRS.HB.
 169
 170 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 171
 172         * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
 173         instructions.  Fix them to use WR_MACC instead of WR_CC and
 174         add missing RD_MACCs.
 175
 176 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 177
 178         * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
 179
 180 2013-07-29  Peter Bergner <bergner@vnet.ibm.com>
 181
 182         * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
 183
 184 2013-07-26  Sergey Guriev  <sergey.s.guriev@intel.com>
 185             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 186             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 187             Sergey Lega  <sergey.s.lega@intel.com>
 188             Anna Tikhonova  <anna.tikhonova@intel.com>
 189             Ilya Tocar  <ilya.tocar@intel.com>
 190             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 191             Ilya Verbin  <ilya.verbin@intel.com>
 192             Kirill Yukhin  <kirill.yukhin@intel.com>
 193             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 194
 195         * i386-dis-evex.h: New.
 196         * i386-dis.c (OP_Rounding): New.
 197         (VPCMP_Fixup): New.
 198         (OP_Mask): New.
 199         (Rdq): New.
 200         (XMxmmq): New.
 201         (EXdScalarS): New.
 202         (EXymm): New.
 203         (EXEvexHalfBcstXmmq): New.
 204         (EXxmm_mdq): New.
 205         (EXEvexXGscat): New.
 206         (EXEvexXNoBcst): New.
 207         (VPCMP): New.
 208         (EXxEVexR): New.
 209         (EXxEVexS): New.
 210         (XMask): New.
 211         (MaskG): New.
 212         (MaskE): New.
 213         (MaskR): New.
 214         (MaskVex): New.
 215         (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
 216         evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
 217         evex_rounding_mode, evex_sae_mode, mask_mode.
 218         (USE_EVEX_TABLE): New.
 219         (EVEX_TABLE): New.
 220         (EVEX enum): New.
 221         (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
 222         REG_EVEX_0F38C7.
 223         (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
 224         MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
 225         MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
 226         MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 227         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,  MOD_EVEX_0F38C7_REG_5,
 228         MOD_EVEX_0F38C7_REG_6.
 229         (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 230         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
 231         PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 232         PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
 233         PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
 234         PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
 235         PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
 236         PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
 237         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
 238         PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
 239         PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
 240         PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
 241         PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
 242         PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
 243         PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
 244         PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
 245         PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
 246         PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
 247         PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
 248         PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
 249         PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
 250         PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
 251         PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
 252         PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
 253         PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
 254         PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
 255         PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
 256         PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
 257         PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
 258         PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
 259         PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
 260         PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
 261         PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
 262         PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
 263         PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
 264         PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
 265         PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
 266         PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
 267         PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
 268         PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
 269         PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
 270         PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
 271         PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
 272         PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
 273         PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
 274         PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
 275         PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
 276         PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
 277         PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
 278         PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
 279         PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
 280         PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
 281         PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
 282         PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
 283         PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
 284         PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
 285         PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
 286         PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
 287         PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
 288         PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
 289         PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
 290         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
 291         PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
 292         PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
 293         PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
 294         PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
 295         PREFIX_EVEX_0F3A00,  PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
 296         PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
 297         PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
 298         PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
 299         PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
 300         PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
 301         PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
 302         PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
 303         PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
 304         PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
 305         PREFIX_EVEX_0F3A55.
 306         (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
 307         VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
 308         VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
 309         VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
 310         VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
 311         VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
 312         VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
 313         VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
 314         VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
 315         VEX_W_0F3A32_P_2_LEN_0.
 316         (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
 317         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
 318         EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
 319         EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
 320         EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
 321         EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 322         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
 323         EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
 324         EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 325         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
 326         EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 327         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
 328         EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
 329         EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
 330         EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
 331         EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
 332         EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
 333         EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
 334         EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
 335         EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
 336         EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
 337         EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
 338         EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
 339         EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
 340         EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
 341         EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
 342         EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
 343         EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
 344         EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
 345         EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
 346         EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
 347         EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
 348         EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
 349         EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
 350         EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
 351         EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
 352         EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
 353         EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
 354         EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
 355         EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
 356         EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
 357         EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
 358         EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
 359         EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
 360         EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
 361         EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
 362         EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
 363         EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
 364         EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
 365         EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
 366         EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
 367         EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
 368         EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
 369         EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
 370         (struct vex): Add fields evex, r, v, mask_register_specifier,
 371         zeroing, ll, b.
 372         (intel_names_xmm): Add upper 16 registers.
 373         (att_names_xmm): Ditto.
 374         (intel_names_ymm): Ditto.
 375         (att_names_ymm): Ditto.
 376         (names_zmm): New.
 377         (intel_names_zmm): Ditto.
 378         (att_names_zmm): Ditto.
 379         (names_mask): Ditto.
 380         (intel_names_mask): Ditto.
 381         (att_names_mask): Ditto.
 382         (names_rounding): Ditto.
 383         (names_broadcast): Ditto.
 384         (x86_64_table): Add escape to evex-table.
 385         (reg_table): Include reg_table evex-entries from
 386         i386-dis-evex.h.  Fix prefetchwt1 instruction.
 387         (prefix_table): Add entries for new instructions.
 388         (vex_table): Ditto.
 389         (vex_len_table): Ditto.
 390         (vex_w_table): Ditto.
 391         (mod_table): Ditto.
 392         (get_valid_dis386): Properly handle new instructions.
 393         (print_insn): Handle zmm and mask registers, print mask operand.
 394         (intel_operand_size): Support EVEX, new modes and sizes.
 395         (OP_E_register): Handle new modes.
 396         (OP_E_memory): Ditto.
 397         (OP_G): Ditto.
 398         (OP_XMM): Ditto.
 399         (OP_EX): Ditto.
 400         (OP_VEX): Ditto.
 401         * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
 402         CPU_ANY_AVX_FLAGS.  Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
 403         CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 404         (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
 405         CpuAVX512PF and CpuVREX.
 406         (operand_type_init): Add OPERAND_TYPE_REGZMM,
 407         OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
 408         (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
 409         StaticRounding, SAE, Disp8MemShift, NoDefMask.
 410         (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
 411         * i386-init.h: Regenerate.
 412         * i386-opc.h (CpuAVX512F): New.
 413         (CpuAVX512CD): New.
 414         (CpuAVX512ER): New.
 415         (CpuAVX512PF): New.
 416         (CpuVREX): New.
 417         (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
 418         cpuavx512pf and cpuvrex fields.
 419         (VecSIB): Add VecSIB512.
 420         (EVex): New.
 421         (Masking): New.
 422         (VecESize): New.
 423         (Broadcast): New.
 424         (StaticRounding): New.
 425         (SAE): New.
 426         (Disp8MemShift): New.
 427         (NoDefMask): New.
 428         (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
 429         staticrounding, sae, disp8memshift and nodefmask.
 430         (RegZMM): New.
 431         (Zmmword): Ditto.
 432         (Vec_Disp8): Ditto.
 433         (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
 434         fields.
 435         (RegVRex): New.
 436         * i386-opc.tbl: Add AVX512 instructions.
 437         * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
 438         registers, mask registers.
 439         * i386-tbl.h: Regenerate.
 440
 441 2013-07-25  Aaro Koskinen  <aaro.koskinen@iki.fi>
 442
 443         PR gas/15220
 444         * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
 445         Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
 446
 447 2013-07-25  Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 448
 449         * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
 450         PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
 451         PREFIX_0F3ACC.
 452         (prefix_table): Updated.
 453         (three_byte_table): Likewise.
 454         * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
 455         (cpu_flags): Add CpuSHA.
 456         (i386_cpu_flags): Add cpusha.
 457         * i386-init.h: Regenerate.
 458         * i386-opc.h (CpuSHA): New.
 459         (CpuUnused): Restored.
 460         (i386_cpu_flags): Add cpusha.
 461         * i386-opc.tbl: Add SHA instructions.
 462         * i386-tbl.h: Regenerate.
 463
 464 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
 465             Kirill Yukhin  <kirill.yukhin@intel.com>
 466             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 467
 468         * i386-dis.c (BND_Fixup): New.
 469         (Ebnd): New.
 470         (Ev_bnd): New.
 471         (Gbnd): New.
 472         (BND): New.
 473         (v_bnd_mode): New.
 474         (bnd_mode): New.
 475         (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
 476         MOD_0F1B_PREFIX_1.
 477         (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
 478         (dis tables): Replace XX with BND for near branch and call
 479         instructions.
 480         (prefix_table): Add new entries.
 481         (mod_table): Likewise.
 482         (names_bnd): New.
 483         (intel_names_bnd): New.
 484         (att_names_bnd): New.
 485         (BND_PREFIX): New.
 486         (prefix_name): Handle BND_PREFIX.
 487         (print_insn): Initialize names_bnd.
 488         (intel_operand_size): Handle new modes.
 489         (OP_E_register): Likewise.
 490         (OP_E_memory): Likewise.
 491         (OP_G): Likewise.
 492         * i386-gen.c (cpu_flag_init): Add CpuMPX.
 493         (cpu_flags): Add CpuMPX.
 494         (operand_type_init): Add RegBND.
 495         (opcode_modifiers): Add BNDPrefixOk.
 496         (operand_types): Add RegBND.
 497         * i386-init.h: Regenerate.
 498         * i386-opc.h (CpuMPX): New.
 499         (CpuUnused): Comment out.
 500         (i386_cpu_flags): Add cpumpx.
 501         (BNDPrefixOk): New.
 502         (i386_opcode_modifier): Add bndprefixok.
 503         (RegBND): New.
 504         (i386_operand_type): Add regbnd.
 505         * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
 506         Add MPX instructions and bnd prefix.
 507         * i386-reg.tbl: Add bnd0-bnd3 registers.
 508         * i386-tbl.h: Regenerate.
 509
 510 2013-07-17  Richard Sandiford  <rdsandiford@googlemail.com>
 511
 512         * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
 513         ATTRIBUTE_UNUSED.
 514
 515 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 516
 517         * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
 518         special rules.
 519         * Makefile.in: Regenerate.
 520         * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
 521         all fields.  Reformat.
 522
 523 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 524
 525         * mips16-opc.c: Include mips-formats.h.
 526         (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
 527         static arrays.
 528         (decode_mips16_operand): New function.
 529         * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
 530         (print_insn_arg): Handle OP_ENTRY_EXIT list.
 531         Abort for OP_SAVE_RESTORE_LIST.
 532         (print_mips16_insn_arg): Change interface.  Use mips_operand
 533         structures.  Delete GET_OP_S.  Move GET_OP definition to...
 534         (print_insn_mips16): ...here.  Call init_print_arg_state.
 535         Update the call to print_mips16_insn_arg.
 536
 537 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 538
 539         * mips-formats.h: New file.
 540         * mips-opc.c: Include mips-formats.h.
 541         (reg_0_map): New static array.
 542         (decode_mips_operand): New function.
 543         * micromips-opc.c: Remove <stdio.h> include.  Include mips-formats.h.
 544         (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
 545         (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
 546         (int_c_map): New static arrays.
 547         (decode_micromips_operand): New function.
 548         * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
 549         (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
 550         (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
 551         (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
 552         (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
 553         (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
 554         (micromips_imm_b_map, micromips_imm_c_map): Delete.
 555         (print_reg): New function.
 556         (mips_print_arg_state): New structure.
 557         (init_print_arg_state, print_insn_arg): New functions.
 558         (print_insn_args): Change interface and use mips_operand structures.
 559         Delete GET_OP_S.  Move GET_OP definition to...
 560         (print_insn_mips): ...here.  Update the call to print_insn_args.
 561         (print_insn_micromips): Use print_insn_args.
 562
 563 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 564
 565         * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
 566         in macros.
 567
 568 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 569
 570         * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
 571         ADDA.S, MULA.S and SUBA.S.
 572
 573 2013-07-08  H.J. Lu  <hongjiu.lu@intel.com>
 574
 575         PR gas/13572
 576         * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
 577         * i386-tbl.h: Regenerated.
 578
 579 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 580
 581         * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros.  Move LD
 582         and SD A(B) macros up.
 583         * micromips-opc.c (micromips_opcodes): Likewise.
 584
 585 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 586
 587         * mips16-opc.c: Add entries for argumentless "entry" and "exit"
 588         instructions.
 589
 590 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 591
 592         * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
 593         MDMX-like instructions.
 594         * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
 595         printing "Q" operands for INSN_5400 instructions.
 596
 597 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 598
 599         * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
 600         "+S" for "cins".
 601         * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
 602         Combine cases.
 603
 604 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 605
 606         * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
 607         "jalx".
 608         * mips16-opc.c (mips16_opcodes): Likewise.
 609         * micromips-opc.c (micromips_opcodes): Likewise.
 610         * mips-dis.c (print_insn_args, print_mips16_insn_arg)
 611         (print_insn_mips16): Handle "+i".
 612         (print_insn_micromips): Likewise.  Conditionally preserve the
 613         ISA bit for "a" but not for "+i".
 614
 615 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 616
 617         * micromips-opc.c (WR_mhi): Rename to..
 618         (WR_mh): ...this.
 619         (micromips_opcodes): Update "movep" entry accordingly.  Replace
 620         "mh,mi" with "mh".
 621         * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
 622         (micromips_to_32_reg_h_map1): ...this.
 623         (micromips_to_32_reg_i_map): Rename to...
 624         (micromips_to_32_reg_h_map2): ...this.
 625         (print_micromips_insn): Remove "mi" case.  Print both registers
 626         in the pair for "mh".
 627
 628 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 629
 630         * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
 631         * micromips-opc.c (micromips_opcodes): Likewise.
 632         * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
 633         and "+T" handling.  Check for a "0" suffix when deciding whether to
 634         use coprocessor 0 names.  In that case, also check for ",H" selectors.
 635
 636 2013-07-05  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 637
 638         * s390-opc.c (J12_12, J24_24): New macros.
 639         (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
 640         (MASK_MII_UPI): Rename to MASK_MII_UPP.
 641         * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
 642
 643 2013-07-04  Alan Modra  <amodra@gmail.com>
 644
 645         * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
 646
 647 2013-06-26  Nick Clifton  <nickc@redhat.com>
 648
 649         * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
 650         field when checking for type 2 nop.
 651         * rx-decode.c: Regenerate.
 652
 653 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
 654
 655         * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
 656         and "movep" macros.
 657
 658 2013-06-24  Maciej W. Rozycki  <macro@codesourcery.com>
 659
 660         * mips-dis.c (is_mips16_plt_tail): New function.
 661         (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
 662         word.
 663         (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
 664
 665 2013-06-21  DJ Delorie  <dj@redhat.com>
 666
 667         * msp430-decode.opc: New.
 668         * msp430-decode.c: New/generated.
 669         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
 670         (MAINTAINER_CLEANFILES): Likewise.
 671         Add rule to build msp430-decode.c frommsp430decode.opc
 672         using the opc2c program.
 673         * Makefile.in: Regenerate.
 674         * configure.in: Add msp430-decode.lo to msp430 architecture files.
 675         * configure: Regenerate.
 676
 677 2013-06-20  Yufeng Zhang  <yufeng.zhang@arm.com>
 678
 679         * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
 680         (SYMTAB_AVAILABLE): Removed.
 681         (#include "elf/aarch64.h): Ditto.
 682
 683 2013-06-17  Catherine Moore  <clm@codesourcery.com>
 684             Maciej W. Rozycki  <macro@codesourcery.com>
 685             Chao-Ying Fu  <fu@mips.com>
 686
 687         * micromips-opc.c (EVA): Define.
 688         (TLBINV): Define.
 689         (micromips_opcodes): Add EVA opcodes.
 690         * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
 691         (print_insn_args): Handle EVA offsets.
 692         (print_insn_micromips): Likewise.
 693         * mips-opc.c (EVA): Define.
 694         (TLBINV): Define.
 695         (mips_builtin_opcodes): Add EVA opcodes.
 696
 697 2013-06-17  Alan Modra  <amodra@gmail.com>
 698
 699         * Makefile.am (mips-opc.lo): Add rules to create automatic
 700         dependency files.  Pass archdefs.
 701         (micromips-opc.lo, mips16-opc.lo): Likewise.
 702         * Makefile.in: Regenerate.
 703
 704 2013-06-14  DJ Delorie  <dj@redhat.com>
 705
 706         * rx-decode.opc (rx_decode_opcode): Bit operations on
 707         registers are 32-bit operations, not 8-bit operations.
 708         * rx-decode.c: Regenerate.
 709
 710 2013-06-13  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 711
 712         * micromips-opc.c (IVIRT): New define.
 713         (IVIRT64): New define.
 714         (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 715         tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
 716
 717         * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
 718         dmtgc0 to print cp0 names.
 719
 720 2013-06-09  Sandra Loosemore  <sandra@codesourcery.com>
 721
 722         * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
 723         argument.
 724
 725 2013-06-08  Catherine Moore  <clm@codesourcery.com>
 726             Richard Sandiford  <rdsandiford@googlemail.com>
 727
 728         * micromips-opc.c (D32, D33, MC): Update definitions.
 729         (micromips_opcodes):  Initialize ase field.
 730         * mips-dis.c (mips_arch_choice): Add ase field.
 731         (mips_arch_choices): Initialize ase field.
 732         (set_default_mips_dis_options): Declare and setup mips_ase.
 733         * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
 734         MT32, MC): Update definitions.
 735         (mips_builtin_opcodes): Initialize ase field.
 736
 737 2013-05-24  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 738
 739         * s390-opc.txt (flogr): Require a register pair destination.
 740
 741 2013-05-23  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 742
 743         * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
 744         instruction format.
 745
 746 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 747
 748         * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
 749
 750 2013-05-20  Peter Bergner <bergner@vnet.ibm.com>
 751
 752         * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
 753         * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
 754         XLS_MASK, PPCVSX2): New defines.
 755         (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
 756         fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
 757         mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
 758         mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
 759         mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
 760         vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
 761         vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
 762         vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
 763         vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
 764         vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
 765         vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
 766         vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
 767         vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
 768         vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
 769         xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
 770         xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
 771         xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
 772         xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
 773         <lxvx, stxvx>: New extended mnemonics.
 774
 775 2013-05-17  Alan Modra  <amodra@gmail.com>
 776
 777         * ia64-raw.tbl: Replace non-ASCII char.
 778         * ia64-waw.tbl: Likewise.
 779         * ia64-asmtab.c: Regenerate.
 780
 781 2013-05-15  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 782
 783         * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
 784         * i386-init.h: Regenerated.
 785
 786 2013-05-13  Yufeng Zhang  <yufeng.zhang@arm.com>
 787
 788         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
 789         * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
 790         check from [0, 255] to [-128, 255].
 791
 792 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 793
 794         * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
 795         Add INSN_VIRT and INSN_VIRT64 to mips64r2.
 796         (parse_mips_dis_option): Handle the virt option.
 797         (print_insn_args): Handle "+J".
 798         (print_mips_disassembler_options): Print out message about virt64.
 799         * mips-opc.c (IVIRT): New define.
 800         (IVIRT64): New define.
 801         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 802         tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
 803         Move rfe to the bottom as it conflicts with tlbgp.
 804
 805 2013-05-09  Alan Modra  <amodra@gmail.com>
 806
 807         * ppc-opc.c (extract_vlesi): Properly sign extend.
 808         (extract_vlensi): Likewise.  Comment reason for setting invalid.
 809
 810 2013-05-02  Nick Clifton  <nickc@redhat.com>
 811
 812         * msp430-dis.c: Add support for MSP430X instructions.
 813
 814 2013-04-24  Sandra Loosemore  <sandra@codesourcery.com>
 815
 816         * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
 817         to "eccinj".
 818
 819 2013-04-17  Wei-chen Wang  <cole945@gmail.com>
 820
 821         PR binutils/15369
 822         * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
 823         of CGEN_CPU_ENDIAN.
 824         (hash_insns_list): Likewise.
 825
 826 2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>
 827
 828         * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
 829         warning workaround.
 830
 831 2013-04-08  Jan Beulich <jbeulich@suse.com>
 832
 833         * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
 834         * i386-tbl.h: Re-generate.
 835
 836 2013-04-06  David S. Miller  <davem@davemloft.net>
 837
 838         * sparc-dis.c (compare_opcodes): When encountering multiple aliases
 839         of an opcode, prefer the one with F_PREFERRED set.
 840         * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
 841         lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
 842         ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
 843         mark existing mnenomics as aliases.  Add "cc" suffix to edge
 844         instructions generating condition codes, mark existing mnenomics
 845         as aliases.  Add "fp" prefix to VIS compare instructions, mark
 846         existing mnenomics as aliases.
 847
 848 2013-04-03  Nick Clifton  <nickc@redhat.com>
 849
 850         * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
 851         destination address by subtracting the operand from the current
 852         address.
 853         * v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
 854         a positive value in the insn.
 855         (extract_u16_loop): Do not negate the returned value.
 856         (D16_LOOP): Add V850_INVERSE_PCREL flag.
 857
 858         (ceilf.sw): Remove duplicate entry.
 859         (cvtf.hs): New entry.
 860         (cvtf.sh): Likewise.
 861         (fmaf.s): Likewise.
 862         (fmsf.s): Likewise.
 863         (fnmaf.s): Likewise.
 864         (fnmsf.s): Likewise.
 865         (maddf.s): Restrict to E3V5 architectures.
 866         (msubf.s): Likewise.
 867         (nmaddf.s): Likewise.
 868         (nmsubf.s): Likewise.
 869
 870 2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>
 871
 872         * i386-dis.c (get_sib): Add the sizeflag argument.  Properly
 873         check address mode.
 874         (print_insn): Pass sizeflag to get_sib.
 875
 876 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 877
 878         PR binutils/15068
 879         * tic6x-dis.c: Add support for displaying 16-bit insns.
 880
 881 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 882
 883         PR gas/15095
 884         * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
 885         individual msb and lsb halves in src1 & src2 fields.  Discard the
 886         src1 (lsb) value and only use src2 (msb), discarding bit 0, to
 887         follow what Ti SDK does in that case as any value in the src1
 888         field yields the same output with SDK disassembler.
 889
 890 2013-03-12  Michael Eager <eager@eagercon.com>
 891
 892         * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
 893
 894 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 895
 896         * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
 897
 898 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 899
 900         * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
 901
 902 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 903
 904         * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
 905
 906 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 907
 908         * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
 909         (thumb32_opcodes): Likewise.
 910         (print_insn_thumb32): Handle 'S' control char.
 911
 912 2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
 913
 914         * lm32-desc.c: Regenerate.
 915
 916 2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 917
 918         * i386-reg.tbl (riz): Add RegRex64.
 919         * i386-tbl.h: Regenerated.
 920
 921 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 922
 923         * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
 924         (aarch64_feature_crc): New static.
 925         (CRC): New macro.
 926         (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
 927         crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
 928         * aarch64-asm-2.c: Re-generate.
 929         * aarch64-dis-2.c: Ditto.
 930         * aarch64-opc-2.c: Ditto.
 931
 932 2013-02-27  Alan Modra  <amodra@gmail.com>
 933
 934         * rl78-decode.opc (rl78_decode_opcode): Fix typo.
 935         * rl78-decode.c: Regenerate.
 936
 937 2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
 938
 939         * rl78-decode.opc: Fix encoding of DIVWU insn.
 940         * rl78-decode.c: Regenerate.
 941
 942 2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 943
 944         PR gas/15159
 945         * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
 946
 947         * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
 948         (cpu_flags): Add CpuSMAP.
 949
 950         * i386-opc.h (CpuSMAP): New.
 951         (i386_cpu_flags): Add cpusmap.
 952
 953         * i386-opc.tbl: Add clac and stac.
 954
 955         * i386-init.h: Regenerated.
 956         * i386-tbl.h: Likewise.
 957
 958 2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
 959
 960         * metag-dis.c: Initialize outf->bytes_per_chunk to 4
 961         which also makes the disassembler output be in little
 962         endian like it should be.
 963
 964 2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
 965
 966         * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
 967         fields to NULL.
 968         (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
 969
 970 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
 971
 972         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
 973         section disassembled.
 974
 975 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 976
 977         * arm-dis.c: Update strht pattern.
 978
 979 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
 980
 981         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
 982         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
 983         trunc.w.s macro for EE.
 984
 985 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
 986             Andrew Jenner <andrew@codesourcery.com>
 987
 988         Based on patches from Altera Corporation.
 989
 990         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
 991         nios2-opc.c.
 992         * Makefile.in: Regenerated.
 993         * configure.in: Add case for bfd_nios2_arch.
 994         * configure: Regenerated.
 995         * disassemble.c (ARCH_nios2): Define.
 996         (disassembler): Add case for bfd_arch_nios2.
 997         * nios2-dis.c: New file.
 998         * nios2-opc.c: New file.
 999
1000 2013-02-04  Alan Modra  <amodra@gmail.com>
1001
1002         * po/POTFILES.in: Regenerate.
1003         * rl78-decode.c: Regenerate.
1004         * rx-decode.c: Regenerate.
1005
1006 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
1007
1008         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
1009         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
1010         * aarch64-asm.c (convert_xtl_to_shll): New function.
1011         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1012         calling convert_xtl_to_shll.
1013         * aarch64-dis.c (convert_shll_to_xtl): New function.
1014         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1015         calling convert_shll_to_xtl.
1016         * aarch64-gen.c: Update copyright year.
1017         * aarch64-asm-2.c: Re-generate.
1018         * aarch64-dis-2.c: Re-generate.
1019         * aarch64-opc-2.c: Re-generate.
1020
1021 2013-01-24  Nick Clifton  <nickc@redhat.com>
1022
1023         * v850-dis.c: Add support for e3v5 architecture.
1024         * v850-opc.c: Likewise.
1025
1026 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
1027
1028         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
1029         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
1030         * aarch64-opc.c (operand_general_constraint_met_p): For
1031         AARCH64_MOD_LSL, move the range check on the shift amount before the
1032         alignment check; change to call set_sft_amount_out_of_range_error
1033         instead of set_imm_out_of_range_error.
1034         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
1035         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
1036         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
1037         SIMD_IMM_SFT.
1038
1039 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
1040
1041         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
1042
1043         * i386-init.h: Regenerated.
1044         * i386-tbl.h: Likewise.
1045
1046 2013-01-15  Nick Clifton  <nickc@redhat.com>
1047
1048         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
1049         values.
1050         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1051
1052 2013-01-14  Will Newton <will.newton@imgtec.com>
1053
1054         * metag-dis.c (REG_WIDTH): Increase to 64.
1055
1056 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
1057
1058         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1059         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1060         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1061         (SH6): Update.
1062         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1063         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1064         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1065         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1066
1067 2013-01-10  Will Newton <will.newton@imgtec.com>
1068
1069         * Makefile.am: Add Meta.
1070         * configure.in: Add Meta.
1071         * disassemble.c: Add Meta support.
1072         * metag-dis.c: New file.
1073         * Makefile.in: Regenerate.
1074         * configure: Regenerate.
1075
1076 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1077
1078         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1079         (match_opcode): Rename to cr16_match_opcode.
1080
1081 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
1082
1083         * mips-dis.c: Add names for CP0 registers of r5900.
1084         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1085         instructions sq and lq.
1086         Add support for MIPS r5900 CPU.
1087         Add support for 128 bit MMI (Multimedia Instructions).
1088         Add support for EE instructions (Emotion Engine).
1089         Disable unsupported floating point instructions (64 bit and
1090         undefined compare operations).
1091         Enable instructions of MIPS ISA IV which are supported by r5900.
1092         Disable 64 bit co processor instructions.
1093         Disable 64 bit multiplication and division instructions.
1094         Disable instructions for co-processor 2 and 3, because these are
1095         not supported (preparation for later VU0 support (Vector Unit)).
1096         Disable cvt.w.s because this behaves like trunc.w.s and the
1097         correct execution can't be ensured on r5900.
1098         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1099         will confuse less developers and compilers.
1100
1101 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1102
1103         * aarch64-opc.c (aarch64_print_operand): Change to print
1104         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1105         in comment.
1106         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1107         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1108         OP_MOV_IMM_WIDE.
1109
1110 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1111
1112         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1113         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
1114
1115 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
1116
1117         * i386-gen.c (process_copyright): Update copyright year to 2013.
1118
1119 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1120
1121         * cr16-dis.c (match_opcode,make_instruction): Remove static
1122         declaration.
1123         (dwordU,wordU): Moved typedefs to opcode/cr16.h
1124         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
1125
1126 For older changes see ChangeLog-2012
1127 \f
1128 Copyright (C) 2013 Free Software Foundation, Inc.
1129
1130 Copying and distribution of this file, with or without modification,
1131 are permitted in any medium without royalty provided the copyright
1132 notice and this notice are preserved.
1133
1134 Local Variables:
1135 mode: change-log
1136 left-margin: 8
1137 fill-column: 74
1138 version-control: never
1139 End: