opcodes/ChangeLog

   1 2015-07-01  Sandra Loosemore  <sandra@codesourcery.com>
   2             Cesar Philippidis  <cesar@codesourcery.com>
   3
   4         * nios2-dis.c (nios2_extract_opcode): New.
   5         (nios2_disassembler_state): New.
   6         (nios2_find_opcode_hash): Use mach parameter to select correct
   7         disassembler state.
   8         (nios2_print_insn_arg): Extend to support new R2 argument letters
   9         and formats.
  10         (print_insn_nios2): Check for 16-bit instruction at end of memory.
  11         * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
  12         (NIOS2_NUM_OPCODES): Rename to...
  13         (NIOS2_NUM_R1_OPCODES): This.
  14         (nios2_r2_opcodes): New.
  15         (NIOS2_NUM_R2_OPCODES): New.
  16         (nios2_num_r2_opcodes): New.
  17         (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
  18         (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
  19         (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
  20         (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
  21         (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
  22
  23 2015-06-30  Amit Pawar  <Amit.Pawar@amd.com>
  24
  25         * i386-dis.c (OP_Mwaitx): New.
  26         (rm_table): Add monitorx/mwaitx.
  27         * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
  28         and CPU_ZNVER1_FLAGS.  Add CPU_MWAITX_FLAGS.
  29         (operand_type_init): Add CpuMWAITX.
  30         * i386-opc.h (CpuMWAITX): New.
  31         (i386_cpu_flags): Add cpumwaitx.
  32         * i386-opc.tbl: Add monitorx and mwaitx.
  33         * i386-init.h: Regenerated.
  34         * i386-tbl.h: Likewise.
  35
  36 2015-06-22  Peter Bergner  <bergner@vnet.ibm.com>
  37
  38         * ppc-opc.c (insert_ls): Test for invalid LS operands.
  39         (insert_esync): New function.
  40         (LS, WC): Use insert_ls.
  41         (ESYNC): Use insert_esync.
  42
  43 2015-06-22  Nick Clifton  <nickc@redhat.com>
  44
  45         * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
  46         requested region lies beyond it.
  47         * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
  48         looking for 32-bit insns.
  49         * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
  50         data.
  51         * sh-dis.c (print_insn_sh): Likewise.
  52         * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
  53         blocks of instructions.
  54         * vax-dis.c (print_insn_vax): Check that the requested address
  55         does not clash with the stop_vma.
  56
  57 2015-06-19  Peter Bergner  <bergner@vnet.ibm.com>
  58
  59         * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
  60         * ppc-opc.c (FXM4): Add non-zero optional value.
  61         (TBR): Likewise.
  62         (SXL): Likewise.
  63         (insert_fxm): Handle new default operand value.
  64         (extract_fxm): Likewise.
  65         (insert_tbr): Likewise.
  66         (extract_tbr): Likewise.
  67
  68 2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
  69
  70         * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
  71
  72 2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  73
  74         * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
  75
  76 2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>
  77
  78         * ppc-opc.c: Add comment accidentally removed by old commit.
  79         (MTMSRD_L): Delete.
  80
  81 2015-06-04  Nick Clifton  <nickc@redhat.com>
  82
  83         PR 18474
  84         * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
  85
  86 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
  87
  88         * arm-dis.c (arm_opcodes): Add "setpan".
  89         (thumb_opcodes): Add "setpan".
  90
  91 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
  92
  93         * arm-dis.c (select_arm_features): Rework to avoid used of redefined
  94         macros.
  95
  96 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
  97
  98         * aarch64-tbl.h (aarch64_feature_rdma): New.
  99         (RDMA): New.
 100         (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
 101         * aarch64-asm-2.c: Regenerate.
 102         * aarch64-dis-2.c: Regenerate.
 103         * aarch64-opc-2.c: Regenerate.
 104
 105 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 106
 107         * aarch64-tbl.h (aarch64_feature_lor): New.
 108         (LOR): New.
 109         (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
 110         "stllrb", "stllrh".
 111         * aarch64-asm-2.c: Regenerate.
 112         * aarch64-dis-2.c: Regenerate.
 113         * aarch64-opc-2.c: Regenerate.
 114
 115 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
 116
 117         * aarch64-opc.c (F_ARCHEXT): New.
 118         (aarch64_sys_regs): Add "pan".
 119         (aarch64_sys_reg_supported_p): New.
 120         (aarch64_pstatefields): Add "pan".
 121         (aarch64_pstatefield_supported_p): New.
 122
 123 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 124
 125         * i386-tbl.h: Regenerate.
 126
 127 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 128
 129         * i386-dis.c (print_insn): Swap rounding mode specifier and
 130         general purpose register in Intel mode.
 131
 132 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 133
 134         * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
 135         * i386-tbl.h: Regenerate.
 136
 137 2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
 138
 139         * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
 140         * i386-init.h: Regenerated.
 141
 142 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 143
 144         PR binutis/18386
 145         * i386-dis.c: Add comments for '@'.
 146         (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
 147         (enum x86_64_isa): New.
 148         (isa64): Likewise.
 149         (print_i386_disassembler_options): Add amd64 and intel64.
 150         (print_insn): Handle amd64 and intel64.
 151         (putop): Handle '@'.
 152         (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
 153         * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
 154         * i386-opc.h (AMD64): New.
 155         (CpuIntel64): Likewise.
 156         (i386_cpu_flags): Add cpuamd64 and cpuintel64.
 157         * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
 158         Mark direct call/jmp without Disp16|Disp32 as Intel64.
 159         * i386-init.h: Regenerated.
 160         * i386-tbl.h: Likewise.
 161
 162 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
 163
 164         * ppc-opc.c (IH) New define.
 165         (powerpc_opcodes) <wait>: Do not enable for POWER7.
 166         <tlbie>: Add RS operand for POWER7.
 167         <slbia>: Add IH operand for POWER6.
 168
 169 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 170
 171         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
 172         direct branch.
 173         (jmp): Likewise.
 174         * i386-tbl.h: Regenerated.
 175
 176 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 177
 178         * configure.ac: Support bfd_iamcu_arch.
 179         * disassemble.c (disassembler): Support bfd_iamcu_arch.
 180         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
 181         CPU_IAMCU_COMPAT_FLAGS.
 182         (cpu_flags): Add CpuIAMCU.
 183         * i386-opc.h (CpuIAMCU): New.
 184         (i386_cpu_flags): Add cpuiamcu.
 185         * configure: Regenerated.
 186         * i386-init.h: Likewise.
 187         * i386-tbl.h: Likewise.
 188
 189 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
 190
 191         PR binutis/18386
 192         * i386-dis.c (X86_64_E8): New.
 193         (X86_64_E9): Likewise.
 194         Update comments on 'T', 'U', 'V'.  Add comments for '^'.
 195         (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
 196         (x86_64_table): Add X86_64_E8 and X86_64_E9.
 197         (mod_table): Replace {T|} with ^ on Jcall/Jmp.
 198         (putop): Handle '^'.
 199         (OP_J): Ignore the operand size prefix in 64-bit.  Don't check
 200         REX_W.
 201
 202 2015-04-30  DJ Delorie  <dj@redhat.com>
 203
 204         * disassemble.c (disassembler): Choose suitable disassembler based
 205         on E_ABI.
 206         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
 207         it to decode mul/div insns.
 208         * rl78-decode.c: Regenerate.
 209         * rl78-dis.c (print_insn_rl78): Rename to...
 210         (print_insn_rl78_common): ...this, take ISA parameter.
 211         (print_insn_rl78): New.
 212         (print_insn_rl78_g10): New.
 213         (print_insn_rl78_g13): New.
 214         (print_insn_rl78_g14): New.
 215         (rl78_get_disassembler): New.
 216
 217 2015-04-29  Nick Clifton  <nickc@redhat.com>
 218
 219         * po/fr.po: Updated French translation.
 220
 221 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
 222
 223         * ppc-opc.c (DCBT_EO): New define.
 224         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
 225         <lharx>: Likewise.
 226         <stbcx.>: Likewise.
 227         <sthcx.>: Likewise.
 228         <waitrsv>: Do not enable for POWER7 and later.
 229         <waitimpl>: Likewise.
 230         <dcbt>: Default to the two operand form of the instruction for all
 231         "old" cpus.  For "new" cpus, use the operand ordering that matches
 232         whether the cpu is server or embedded.
 233         <dcbtst>: Likewise.
 234
 235 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 236
 237         * s390-opc.c: New instruction type VV0UU2.
 238         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
 239         and WFC.
 240
 241 2015-04-23  Jan Beulich  <jbeulich@suse.com>
 242
 243         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
 244         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
 245         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
 246         (vfpclasspd, vfpclassps): Add %XZ.
 247
 248 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 249
 250         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
 251         (PREFIX_UD_REPZ): Likewise.
 252         (PREFIX_UD_REPNZ): Likewise.
 253         (PREFIX_UD_DATA): Likewise.
 254         (PREFIX_UD_ADDR): Likewise.
 255         (PREFIX_UD_LOCK): Likewise.
 256
 257 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 258
 259         * i386-dis.c (prefix_requirement): Removed.
 260         (print_insn): Don't set prefix_requirement.  Check
 261         dp->prefix_requirement instead of prefix_requirement.
 262
 263 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 264
 265         PR binutils/17898
 266         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
 267         (PREFIX_MOD_0_0FC7_REG_6): This.
 268         (PREFIX_MOD_3_0FC7_REG_6): New.
 269         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
 270         (prefix_table): Replace PREFIX_0FC7_REG_6 with
 271         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
 272         PREFIX_MOD_3_0FC7_REG_7.
 273         (mod_table): Replace PREFIX_0FC7_REG_6 with
 274         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
 275         PREFIX_MOD_3_0FC7_REG_7.
 276
 277 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 278
 279         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
 280         (PREFIX_MANDATORY_REPNZ): Likewise.
 281         (PREFIX_MANDATORY_DATA): Likewise.
 282         (PREFIX_MANDATORY_ADDR): Likewise.
 283         (PREFIX_MANDATORY_LOCK): Likewise.
 284         (PREFIX_MANDATORY): Likewise.
 285         (PREFIX_UD_SHIFT): Set to 8
 286         (PREFIX_UD_REPZ): Updated.
 287         (PREFIX_UD_REPNZ): Likewise.
 288         (PREFIX_UD_DATA): Likewise.
 289         (PREFIX_UD_ADDR): Likewise.
 290         (PREFIX_UD_LOCK): Likewise.
 291         (PREFIX_IGNORED_SHIFT): New.
 292         (PREFIX_IGNORED_REPZ): Likewise.
 293         (PREFIX_IGNORED_REPNZ): Likewise.
 294         (PREFIX_IGNORED_DATA): Likewise.
 295         (PREFIX_IGNORED_ADDR): Likewise.
 296         (PREFIX_IGNORED_LOCK): Likewise.
 297         (PREFIX_OPCODE): Likewise.
 298         (PREFIX_IGNORED): Likewise.
 299         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 300         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 301         (three_byte_table): Likewise.
 302         (mod_table): Likewise.
 303         (mandatory_prefix): Renamed to ...
 304         (prefix_requirement): This.
 305         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 306         Update PREFIX_90 entry.
 307         (get_valid_dis386): Check prefix_requirement to see if a prefix
 308         should be ignored.
 309         (print_insn): Replace mandatory_prefix with prefix_requirement.
 310
 311 2015-04-15  Renlin Li  <renlin.li@arm.com>
 312
 313         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
 314         use it for ssat and ssat16.
 315         (print_insn_thumb32): Add handle case for 'D' control code.
 316
 317 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
 318             H.J. Lu  <hongjiu.lu@intel.com>
 319
 320         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
 321         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
 322         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
 323         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
 324         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
 325         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
 326         Fill prefix_requirement field.
 327         (struct dis386): Add prefix_requirement field.
 328         (dis386): Fill prefix_requirement field.
 329         (dis386_twobyte): Ditto.
 330         (twobyte_has_mandatory_prefix_: Remove.
 331         (reg_table): Fill prefix_requirement field.
 332         (prefix_table): Ditto.
 333         (x86_64_table): Ditto.
 334         (three_byte_table): Ditto.
 335         (xop_table): Ditto.
 336         (vex_table): Ditto.
 337         (vex_len_table): Ditto.
 338         (vex_w_table): Ditto.
 339         (mod_table): Ditto.
 340         (bad_opcode): Ditto.
 341         (print_insn): Use prefix_requirement.
 342         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
 343         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
 344         (float_reg): Ditto.
 345
 346 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
 347
 348         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
 349
 350 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 351
 352         * Makefile.in: Regenerated.
 353
 354 2015-03-25  Anton Blanchard  <anton@samba.org>
 355
 356         * ppc-dis.c (disassemble_init_powerpc): Only initialise
 357         powerpc_opcd_indices and vle_opcd_indices once.
 358
 359 2015-03-25  Anton Blanchard  <anton@samba.org>
 360
 361         * ppc-opc.c (powerpc_opcodes): Add slbfee.
 362
 363 2015-03-24  Terry Guo  <terry.guo@arm.com>
 364
 365         * arm-dis.c (opcode32): Updated to use new arm feature struct.
 366         (opcode16): Likewise.
 367         (coprocessor_opcodes): Replace bit with feature struct.
 368         (neon_opcodes): Likewise.
 369         (arm_opcodes): Likewise.
 370         (thumb_opcodes): Likewise.
 371         (thumb32_opcodes): Likewise.
 372         (print_insn_coprocessor): Likewise.
 373         (print_insn_arm): Likewise.
 374         (select_arm_features): Follow new feature struct.
 375
 376 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 377
 378         * i386-dis.c (rm_table): Add clzero.
 379         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
 380         Add CPU_CLZERO_FLAGS.
 381         (cpu_flags): Add CpuCLZERO.
 382         * i386-opc.h: Add CpuCLZERO.
 383         * i386-opc.tbl: Add clzero.
 384         * i386-init.h: Re-generated.
 385         * i386-tbl.h: Re-generated.
 386
 387 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 388
 389         * mips-opc.c (decode_mips_operand): Fix constraint issues
 390         with u and y operands.
 391
 392 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 393
 394         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
 395
 396 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 397
 398         * s390-opc.c: Add new IBM z13 instructions.
 399         * s390-opc.txt: Likewise.
 400
 401 2015-03-10  Renlin Li  <renlin.li@arm.com>
 402
 403         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
 404         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
 405         related alias.
 406         * aarch64-asm-2.c: Regenerate.
 407         * aarch64-dis-2.c: Likewise.
 408         * aarch64-opc-2.c: Likewise.
 409
 410 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
 411
 412         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
 413
 414 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
 415
 416         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
 417         arch_sh_up.
 418         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
 419         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
 420
 421 2015-02-23  Vinay  <Vinay.G@kpit.com>
 422
 423         * rl78-decode.opc (MOV): Added space between two operands for
 424         'mov' instruction in index addressing mode.
 425         * rl78-decode.c: Regenerate.
 426
 427 2015-02-19  Pedro Alves  <palves@redhat.com>
 428
 429         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
 430
 431 2015-02-10  Pedro Alves  <palves@redhat.com>
 432             Tom Tromey  <tromey@redhat.com>
 433
 434         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
 435         microblaze_and, microblaze_xor.
 436         * microblaze-opc.h (opcodes): Adjust.
 437
 438 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
 439
 440         * Makefile.am: Add FT32 files.
 441         * configure.ac: Handle FT32.
 442         * disassemble.c (disassembler): Call print_insn_ft32.
 443         * ft32-dis.c: New file.
 444         * ft32-opc.c: New file.
 445         * Makefile.in: Regenerate.
 446         * configure: Regenerate.
 447         * po/POTFILES.in: Regenerate.
 448
 449 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 450
 451         * nds32-asm.c (keyword_sr): Add new system registers.
 452
 453 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 454
 455         * s390-dis.c (s390_extract_operand): Support vector register
 456         operands.
 457         (s390_print_insn_with_opcode): Support new operands types and add
 458         new handling of optional operands.
 459         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
 460         and include opcode/s390.h instead.
 461         (struct op_struct): New field `flags'.
 462         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
 463         (dumpTable): Dump flags.
 464         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
 465         string.
 466         * s390-opc.c: Add new operands types, instruction formats, and
 467         instruction masks.
 468         (s390_opformats): Add new formats for .insn.
 469         * s390-opc.txt: Add new instructions.
 470
 471 2015-01-01  Alan Modra  <amodra@gmail.com>
 472
 473         Update year range in copyright notice of all files.
 474
 475 For older changes see ChangeLog-2014
 476 \f
 477 Copyright (C) 2015 Free Software Foundation, Inc.
 478
 479 Copying and distribution of this file, with or without modification,
 480 are permitted in any medium without royalty provided the copyright
 481 notice and this notice are preserved.
 482
 483 Local Variables:
 484 mode: change-log
 485 left-margin: 8
 486 fill-column: 74
 487 version-control: never
 488 End: