opcodes/ChangeLog

   1 2021-03-29  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl (psadbw): Add <sse2:comm>.
   4         (vpsadbw): Add C.
   5         * i386-tbl.h: Re-generate.
   6
   7 2021-03-29  Jan Beulich  <jbeulich@suse.com>
   8
   9         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
  10         pclmul, gfni): New templates. Use them wherever possible. Move
  11         SSE4.1 pextrw into respective section.
  12         * i386-tbl.h: Re-generate.
  13
  14 2021-03-29  Jan Beulich  <jbeulich@suse.com>
  15
  16         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
  17         strtoull(). Bump upper loop bound. Widen masks. Sanity check
  18         "length".
  19         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
  20         Convert all of their uses to representation in opcode.
  21
  22 2021-03-29  Jan Beulich  <jbeulich@suse.com>
  23
  24         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
  25         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
  26         value of None. Shrink operands to 3 bits.
  27
  28 2021-03-29  Jan Beulich  <jbeulich@suse.com>
  29
  30         * i386-gen.c (process_i386_opcode_modifier): New parameter
  31         "space".
  32         (output_i386_opcode): New local variable "space". Adjust
  33         process_i386_opcode_modifier() invocation.
  34         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
  35         invocation.
  36         * i386-tbl.h: Re-generate.
  37
  38 2021-03-29  Alan Modra  <amodra@gmail.com>
  39
  40         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
  41         (fp_qualifier_p, get_data_pattern): Likewise.
  42         (aarch64_get_operand_modifier_from_value): Likewise.
  43         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
  44         (operand_variant_qualifier_p): Likewise.
  45         (qualifier_value_in_range_constraint_p): Likewise.
  46         (aarch64_get_qualifier_esize): Likewise.
  47         (aarch64_get_qualifier_nelem): Likewise.
  48         (aarch64_get_qualifier_standard_value): Likewise.
  49         (get_lower_bound, get_upper_bound): Likewise.
  50         (aarch64_find_best_match, match_operands_qualifier): Likewise.
  51         (aarch64_print_operand): Likewise.
  52         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
  53         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
  54         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
  55         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
  56         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
  57         (print_insn_tic6x): Likewise.
  58
  59 2021-03-29  Alan Modra  <amodra@gmail.com>
  60
  61         * arc-dis.c (extract_operand_value): Correct NULL cast.
  62         * frv-opc.h: Regenerate.
  63
  64 2021-03-26  Jan Beulich  <jbeulich@suse.com>
  65
  66         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
  67         MMX form.
  68         * i386-tbl.h: Re-generate.
  69
  70 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
  71
  72         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
  73         immediate in br.n instruction.
  74
  75 2021-03-25  Jan Beulich  <jbeulich@suse.com>
  76
  77         * i386-dis.c (XMGatherD, VexGatherD): New.
  78         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
  79         (print_insn): Check masking for S/G insns.
  80         (OP_E_memory): New local variable check_gather. Extend mandatory
  81         SIB check. Check register conflicts for (EVEX-encoded) gathers.
  82         Extend check for disallowed 16-bit addressing.
  83         (OP_VEX): New local variables modrm_reg and sib_index. Convert
  84         if()s to switch(). Check register conflicts for (VEX-encoded)
  85         gathers. Drop no longer reachable cases.
  86         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
  87         vgatherdp*.
  88
  89 2021-03-25  Jan Beulich  <jbeulich@suse.com>
  90
  91         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
  92         zeroing-masking without masking.
  93
  94 2021-03-25  Jan Beulich  <jbeulich@suse.com>
  95
  96         * i386-opc.tbl (invlpgb): Fix multi-operand form.
  97         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
  98         single-operand forms as deprecated.
  99         * i386-tbl.h: Re-generate.
 100
 101 2021-03-25  Alan Modra  <amodra@gmail.com>
 102
 103         PR 27647
 104         * ppc-opc.c (XLOCB_MASK): Delete.
 105         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 106         XLBH_MASK.
 107         (powerpc_opcodes): Accept a BH field on all extended forms of
 108         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 109
 110 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 111
 112         * i386-gen.c (output_i386_opcode): Drop processing of
 113         opcode_length. Calculate length from base_opcode. Adjust prefix
 114         encoding determination.
 115         (process_i386_opcodes): Drop output of fake opcode_length.
 116         * i386-opc.h (struct insn_template): Drop opcode_length field.
 117         * i386-opc.tbl: Drop opcode length field from all templates.
 118         * i386-tbl.h: Re-generate.
 119
 120 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 121
 122         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 123         parameter "prefix". Drop local variable "regular_encoding".
 124         Record prefix setting / check for consistency.
 125         (output_i386_opcode): Parse opcode_length and base_opcode
 126         earlier. Derive prefix encoding. Drop no longer applicable
 127         consistency checking. Adjust process_i386_opcode_modifier()
 128         invocation.
 129         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 130         invocation.
 131         * i386-tbl.h: Re-generate.
 132
 133 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 134
 135         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 136         check.
 137         * i386-opc.h (Prefix_*): Move #define-s.
 138         * i386-opc.tbl: Move pseudo prefix enumerator values to
 139         extension opcode field. Introduce pseudopfx template.
 140         * i386-tbl.h: Re-generate.
 141
 142 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 143
 144         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 145         comment.
 146         * i386-tbl.h: Re-generate.
 147
 148 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 149
 150         * i386-opc.h (struct insn_template): Move cpu_flags field past
 151         opcode_modifier one.
 152         * i386-tbl.h: Re-generate.
 153
 154 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 155
 156         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 157         * i386-opc.h (OpcodeSpace): New enumerator.
 158         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 159         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 160         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 161         (struct i386_opcode_modifier): New field opcodespace. Shrink
 162         opcodeprefix field.
 163         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 164         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 165         OpcodePrefix uses.
 166         * i386-tbl.h: Re-generate.
 167
 168 2021-03-22  Martin Liska  <mliska@suse.cz>
 169
 170         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 171         * arc-dis.c (parse_option): Likewise.
 172         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 173         * cris-dis.c (print_with_operands): Likewise.
 174         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 175         * i386-dis.c (print_insn): Likewise.
 176         * ia64-gen.c (fetch_insn_class): Likewise.
 177         (parse_resource_users): Likewise.
 178         (in_iclass): Likewise.
 179         (lookup_specifier): Likewise.
 180         (insert_opcode_dependencies): Likewise.
 181         * mips-dis.c (parse_mips_ase_option): Likewise.
 182         (parse_mips_dis_option): Likewise.
 183         * s390-dis.c (disassemble_init_s390): Likewise.
 184         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 185
 186 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 187
 188         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 189
 190 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 191
 192         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 193         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 194
 195 2021-03-12  Alan Modra  <amodra@gmail.com>
 196
 197         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 198
 199 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 200
 201         * i386-dis.c (OP_XMM): Re-order checks.
 202
 203 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 204
 205         * i386-dis.c (putop): Drop need_vex check when also checking
 206         vex.evex.
 207         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 208         checking vex.b.
 209
 210 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 211
 212         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 213         checks. Move case label past broadcast check.
 214
 215 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 216
 217         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 218         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 219         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 220         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 221         EVEX_W_0F38C7_M_0_L_2): Delete.
 222         (REG_EVEX_0F38C7_M_0_L_2): New.
 223         (intel_operand_size): Handle VEX and EVEX the same for
 224         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 225         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 226         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 227         vex_vsib_q_w_d_mode uses.
 228         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 229         0F38A1, and 0F38A3 entries.
 230         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 231         entry.
 232         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 233         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 234         0F38A3 entries.
 235
 236 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 237
 238         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 239         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 240         MOD_VEX_0FXOP_09_12): Rename to ...
 241         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 242         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 243         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 244         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 245         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 246         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 247         (reg_table): Adjust comments.
 248         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 249         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 250         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 251         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 252         (vex_len_table): Adjust opcode 0A_12 entry.
 253         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 254         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 255         (rm_table): Move hreset entry.
 256
 257 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 258
 259         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 260         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 261         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 262         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 263         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 264         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 265         (get_valid_dis386): Also handle 512-bit vector length when
 266         vectoring into vex_len_table[].
 267         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 268         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 269         entries.
 270         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 271         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 272         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 273         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 274         entries.
 275
 276 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 277
 278         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 279         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 280         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 281         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 282         entries.
 283         * i386-dis-evex-len.h (evex_len_table): Likewise.
 284         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 285
 286 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 287
 288         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 289         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 290         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 291         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 292         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 293         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 294         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 295         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 296         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 297         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 298         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 299         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 300         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 301         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 302         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 303         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 304         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 305         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 306         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 307         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 308         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 309         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 310         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 311         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 312         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 313         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 314         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 315         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 316         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 317         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 318         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 319         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 320         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 321         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 322         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 323         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 324         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 325         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 326         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 327         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 328         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 329         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 330         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 331         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 332         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 333         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 334         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 335         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 336         EVEX_W_0F3A43_L_n): New.
 337         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 338         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 339         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 340         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 341         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 342         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 343         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 344         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 345         0F385B, 0F38C6, and 0F38C7 entries.
 346         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 347         0F38C6 and 0F38C7.
 348         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 349         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 350         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 351         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 352
 353 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 354
 355         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 356         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 357         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 358         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 359         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 360         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 361         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 362         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 363         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 364         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 365         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 366         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 367         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 368         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 369         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 370         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 371         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 372         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 373         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 374         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 375         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 376         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 377         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 378         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 379         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 380         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 381         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 382         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 383         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 384         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 385         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 386         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 387         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 388         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 389         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 390         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 391         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 392         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 393         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 394         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 395         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 396         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 397         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 398         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 399         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 400         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 401         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 402         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 403         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 404         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 405         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 406         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 407         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 408         VEX_W_0F99_P_2_LEN_0): Delete.
 409         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 410         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 411         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 412         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 413         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 414         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 415         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 416         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 417         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 418         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 419         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 420         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 421         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 422         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 423         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 424         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 425         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 426         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 427         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 428         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 429         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 430         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 431         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 432         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 433         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 434         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 435         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 436         (prefix_table): No longer link to vex_len_table[] for opcodes
 437         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 438         0F92, 0F93, 0F98, and 0F99.
 439         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 440         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 441         0F98, and 0F99.
 442         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 443         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 444         0F98, and 0F99.
 445         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 446         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 447         0F98, and 0F99.
 448         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 449         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 450         0F98, and 0F99.
 451
 452 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 453
 454         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 455         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 456         REG_VEX_0F73_M_0 respectively.
 457         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 458         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 459         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 460         MOD_VEX_0F73_REG_7): Delete.
 461         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 462         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 463         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 464         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 465         PREFIX_VEX_0F3AF0_L_0 respectively.
 466         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 467         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 468         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 469         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 470         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 471         VEX_LEN_0F38F7): New.
 472         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 473         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 474         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 475         0F38F3.
 476         (prefix_table): No longer link to vex_len_table[] for opcodes
 477         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 478         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 479         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 480         0F38F6, 0F38F7, and 0F3AF0.
 481         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 482         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 483         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 484         0F73.
 485
 486 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 487
 488         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 489         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 490         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 491         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 492         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 493         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 494         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 495         73.
 496         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 497         0F72, and 0F73.
 498         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 499         0F73.
 500
 501 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 502
 503         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 504         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 505         (reg_table): Don't link to mod_table[] where not needed. Add
 506         PREFIX_IGNORED to nop entries.
 507         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 508         (mod_table): Add nop entries next to prefetch ones. Drop
 509         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 510         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 511         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 512         PREFIX_OPCODE from endbr* entries.
 513         (get_valid_dis386): Also consider entry's name when zapping
 514         vindex.
 515         (print_insn): Handle PREFIX_IGNORED.
 516
 517 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 518
 519         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 520         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 521         element.
 522         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 523         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 524         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 525         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 526         (struct i386_opcode_modifier): Delete notrackprefixok,
 527         islockable, hleprefixok, and repprefixok fields. Add prefixok
 528         field.
 529         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 530         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 531         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 532         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 533         Replace HLEPrefixOk.
 534         * opcodes/i386-tbl.h: Re-generate.
 535
 536 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 537
 538         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 539         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 540         64-bit form.
 541         * opcodes/i386-tbl.h: Re-generate.
 542
 543 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 544
 545         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 546         for {} instead of {0}. Don't look for '0'.
 547         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 548         size specifiers.
 549
 550 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 551
 552         PR 27158
 553         * riscv-dis.c (print_insn_args): Updated encoding macros.
 554         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 555         (match_c_addi16sp): Updated encoding macros.
 556         (match_c_lui): Likewise.
 557         (match_c_lui_with_hint): Likewise.
 558         (match_c_addi4spn): Likewise.
 559         (match_c_slli): Likewise.
 560         (match_slli_as_c_slli): Likewise.
 561         (match_c_slli64): Likewise.
 562         (match_srxi_as_c_srxi): Likewise.
 563         (riscv_insn_types): Added .insn css/cl/cs.
 564
 565 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 566
 567         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 568         (default_priv_spec): Updated type to riscv_spec_class.
 569         (parse_riscv_dis_option): Updated.
 570         * riscv-opc.c: Moved stuff and make the file tidy.
 571
 572 2021-02-17  Alan Modra  <amodra@gmail.com>
 573
 574         * wasm32-dis.c: Include limits.h.
 575         (CHAR_BIT): Provide backup define.
 576         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 577         Correct signed overflow checking.
 578
 579 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 580
 581         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 582         * i386-tbl.h: Re-generate.
 583
 584 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 585
 586         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 587         Oword.
 588         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 589
 590 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 591
 592         * s390-mkopc.c (main): Accept arch14 as cpu string.
 593         * s390-opc.txt: Add new arch14 instructions.
 594
 595 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 596
 597         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 598         favour of LIBINTL.
 599         * configure: Regenerated.
 600
 601 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 602
 603         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 604         * tic54x-opc.c (regs): Rename to ...
 605         (tic54x_regs): ... this.
 606         (mmregs): Rename to ...
 607         (tic54x_mmregs): ... this.
 608         (condition_codes): Rename to ...
 609         (tic54x_condition_codes): ... this.
 610         (cc2_codes): Rename to ...
 611         (tic54x_cc2_codes): ... this.
 612         (cc3_codes): Rename to ...
 613         (tic54x_cc3_codes): ... this.
 614         (status_bits): Rename to ...
 615         (tic54x_status_bits): ... this.
 616         (misc_symbols): Rename to ...
 617         (tic54x_misc_symbols): ... this.
 618
 619 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 620
 621         * riscv-opc.c (MASK_RVB_IMM): Removed.
 622         (riscv_opcodes): Removed zb* instructions.
 623         (riscv_ext_version_table): Removed versions for zb*.
 624
 625 2021-01-26  Alan Modra  <amodra@gmail.com>
 626
 627         * i386-gen.c (parse_template): Ensure entire template_instance
 628         is initialised.
 629
 630 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 631
 632         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 633         (riscv_fpr_names_abi): Likewise.
 634         (riscv_opcodes): Likewise.
 635         (riscv_insn_types): Likewise.
 636
 637 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 638
 639         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 640
 641 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 642
 643         * riscv-dis.c: Comments tidy and improvement.
 644         * riscv-opc.c: Likewise.
 645
 646 2021-01-13  Alan Modra  <amodra@gmail.com>
 647
 648         * Makefile.in: Regenerate.
 649
 650 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 651
 652         PR binutils/26792
 653         * configure.ac: Use GNU_MAKE_JOBSERVER.
 654         * aclocal.m4: Regenerated.
 655         * configure: Likewise.
 656
 657 2021-01-12  Nick Clifton  <nickc@redhat.com>
 658
 659         * po/sr.po: Updated Serbian translation.
 660
 661 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 662
 663         PR ld/27173
 664         * configure: Regenerated.
 665
 666 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 667
 668         * aarch64-asm-2.c: Regenerate.
 669         * aarch64-dis-2.c: Likewise.
 670         * aarch64-opc-2.c: Likewise.
 671         * aarch64-opc.c (aarch64_print_operand):
 672         Delete handling of AARCH64_OPND_CSRE_CSR.
 673         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 674         (CSRE): Likewise.
 675         (_CSRE_INSN): Likewise.
 676         (aarch64_opcode_table): Delete csr.
 677
 678 2021-01-11  Nick Clifton  <nickc@redhat.com>
 679
 680         * po/de.po: Updated German translation.
 681         * po/fr.po: Updated French translation.
 682         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 683         * po/sv.po: Updated Swedish translation.
 684         * po/uk.po: Updated Ukranian translation.
 685
 686 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 687
 688         * configure: Regenerated.
 689
 690 2021-01-09  Nick Clifton  <nickc@redhat.com>
 691
 692         * configure: Regenerate.
 693         * po/opcodes.pot: Regenerate.
 694
 695 2021-01-09  Nick Clifton  <nickc@redhat.com>
 696
 697         * 2.36 release branch crated.
 698
 699 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 700
 701         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 702         (DW, (XRC_MASK): Define.
 703         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 704
 705 2021-01-09  Alan Modra  <amodra@gmail.com>
 706
 707         * configure: Regenerate.
 708
 709 2021-01-08  Nick Clifton  <nickc@redhat.com>
 710
 711         * po/sv.po: Updated Swedish translation.
 712
 713 2021-01-08  Nick Clifton  <nickc@redhat.com>
 714
 715         PR 27129
 716         * aarch64-dis.c (determine_disassembling_preference): Move call to
 717         aarch64_match_operands_constraint outside of the assertion.
 718         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 719         Replace with a return of FALSE.
 720
 721         PR 27139
 722         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 723         core system register.
 724
 725 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 726
 727         * configure: Regenerate.
 728
 729 2021-01-07  Nick Clifton  <nickc@redhat.com>
 730
 731         * po/fr.po: Updated French translation.
 732
 733 2021-01-07  Fredrik Noring  <noring@nocrew.org>
 734
 735         * m68k-opc.c (chkl): Change minimum architecture requirement to
 736         m68020.
 737
 738 2021-01-07  Philipp Tomsich  <prt@gnu.org>
 739
 740         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
 741
 742 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
 743             Jim Wilson  <jimw@sifive.com>
 744             Andrew Waterman  <andrew@sifive.com>
 745             Maxim Blinov  <maxim.blinov@embecosm.com>
 746             Kito Cheng  <kito.cheng@sifive.com>
 747             Nelson Chu  <nelson.chu@sifive.com>
 748
 749         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
 750         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
 751
 752 2021-01-01  Alan Modra  <amodra@gmail.com>
 753
 754         Update year range in copyright notice of all files.
 755
 756 For older changes see ChangeLog-2020
 757 \f
 758 Copyright (C) 2021 Free Software Foundation, Inc.
 759
 760 Copying and distribution of this file, with or without modification,
 761 are permitted in any medium without royalty provided the copyright
 762 notice and this notice are preserved.
 763
 764 Local Variables:
 765 mode: change-log
 766 left-margin: 8
 767 fill-column: 74
 768 version-control: never
 769 End: